ISL55110IVZ-T

DATASHEET ISL55110, ISL55111 FN6228 Rev 9.0 Apr 29, 2021 Dual, High Speed MOSFET Driver The ISL55110 and ISL55111 are dual high speed MOSFET drivers intended for applications requiring accurate pulse generation and buffering. Target applications include ultrasound, CCD imaging, piezoelectric distance sensing and clock generation circuits. Features With a wide output voltage range and low ON-resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high-speed operation with low skew, as required in large CCD array imaging applications. • 1.5ns rise and fall times, 100pF load The ISL55110, ISL55111 are compatible with 3.3V and 5V logic families and incorporate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. The ISL55110 has a pair of in-phase drivers while the ISL55111 has two drivers operating in anti-phase. • Small QFN and TSSOP packaging ISL55110 and ISL55111 have a power-down mode for low power consumption during equipment standby times, making it ideal for portable products. The ISL55110 and ISL55111 are available in 16 Ld Exposed pad QFN packaging and 8 Ld TSSOP. Both devices are specified for operation over the full -40°C to +85°C temperature range. • 5V to 12V pulse amplitude • High current drive 3.5A • 6ns minimum pulse width • Low skew • 3.3V and 5V logic compatible • In-phase (ISL55110) and anti-phase outputs (ISL55111) • Low quiescent current • Pb-free (RoHS compliant) Applications • Ultrasound MOSFET driver • CCD array horizontal driver • Clock driver circuits ISL55110 AND ISL55111 DUAL DRIVER o o VDD IN-A VH OA o o o ENABLE-QFN* o IN-B OB ** GND o o o PD *ENABLE AVAILABLE IN QFN PACKAGE ONLY **ISL55111 IN-B IS INVERTING FIGURE 1. FUNCTIONAL BLOCK DIAGRAM FN6228 Rev 9.0 Apr 29, 2021 Page 1 of 18 © 2007 Renesas Electronics ISL55110, ISL55111 Pin Configurations ISL55111 (16 LD QFN) TOP VIEW NC NC NC NC NC NC NC NC ISL55110 (16 LD QFN) TOP VIEW 16 15 14 13 16 15 14 13 VDD 1 12 OB ENABLE 2 11 GND EP VDD 1 ENABLE 2 12 OB 11 EP GND 4 9 OA IN-B 4 9 IN-A 5 6 7 8 5 6 7 8 NC IN-B NC 10 VH NC 3 IN-A PD NC 10 VH NC 3 NC PD OA ISL55111 (8 LD TSSOP) TOP VIEW ISL55110 (8 LD TSSOP) TOP VIEW VDD 1 8 OB VDD 1 8 OB PD 2 7 GND PD 2 7 GND IN-B 3 6 VH IN-B 3 6 VH IN-A 4 5 IN-A 4 5 OA OA Pin Descriptions 16 LD QFN 8 LD TSSOP PIN 1 1 VDD 10 6 VH 11 7 GND 3 2 PD 2 - ENABLE 5 4 IN-A 4 3 IN-B, IN-B 9 5 OA Driver output related to IN-A. 12 8 OB Driver output related to IN-B. 6, 7, 8, 13, 14, 15, 16 - NC No internal connection. EP - EP Exposed thermal pad. Connect to GND and follow good thermal pad layout guidelines. FN6228 Rev 9.0 Apr 29, 2021 FUNCTION Logic power. Driver high rail supply. Ground, return for both VH rail and VDD logic supply. This is also the potential of the QFN’s exposed pad (EP). Power-down. Active logic high places part in power-down mode. QFN packages only. When the ENABLE pin is low, the device will operate normally (outputs controlled by the inputs). When the ENABLE pin is tied high, the output will be tri-stated. In other words, it will act as if it is open or floating regardless of what is on the IN-x pins. This provides high-speed enable control over the driver outputs. Logic level input that drives OA to VH rail or ground. Not inverted. Logic level input that drives OB to VH rail or ground. Not inverted on ISL55110, inverted on ISL55111. Page 2 of 18 ISL55110, ISL55111 Ordering Information PART NUMBER (Notes 2, 3) ISL55110IRZ PART MARKING 55110IRZ PACKAGE DESCRIPTION (RoHS Compliant) 16 Ld QFN PKG. DWG. # L16.4x4A ISL55110IRZ-T TEMP. RANGE Tube -40 to +85°C Reel, 6k ISL55110IRZ-T7A ISL55110IVZ CARRIER TYPE (Note 1) Reel, 250 55110 IVZ 8 Ld TSSOP M8.173 Tube ISL55110IVZ-T Reel, 2.5k ISL55110IVZ-T7A Reel, 250 ISL55111IRZ 55111IRZ 16 Ld QFN L16.4x4A ISL55111IRZ-T ISL55111IVZ Tube Reel, 6k 55111 IVZ ISL55111IVZ-T 8 Ld TSSOP M8.173 Tube Reel, 2.5k ISL55110EVAL1Z TSSOP Evaluation Board ISL55110EVAL2Z QFN Evaluation Board ISL55111EVAL1Z TSSOP Evaluation Board ISL55111EVAL2Z QFN Evaluation Board NOTES: 1. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see the device information pages for ISL55110 and ISL55111. For more information about MSL, see TB363. FN6228 Rev 9.0 Apr 29, 2021 Page 3 of 18 ISL55110, ISL55111 Absolute Maximum Ratings (TA = +25°C) Thermal Information VH to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V VIN-A, VIN-B, PD, ENABLE . . . . . . . . . . . . . . . . (GND - 0.5V) to (VDD + 0.5V) OA, OB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.5) to (VH + 0.5V) Maximum Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV Thermal Resistance JA (°C/W) JC (°C/W) 16 Ld (4x4) QFN Package (Notes 5, 6) . . . 45 3.0 8 Ld TSSOP Package (Notes 4, 7) . . . . . . . 140 46 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Drive Supply Voltage (VH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 13.2V Logic Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details. 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See TB379. 6. For JC, the case temperature location is the center of the exposed metal pad on the package underside. 7. For JC, the case temperature location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VH = +12V, VDD = 2.7V to 5.5V, TA = +25°C, unless otherwise specified. MIN (Note 8) TYP MAX (Note 8) UNITS lIH = 1µA: VIN-A, VIN-B 1.32 1.42 1.52 V 1.12 1.22 1.32 DESCRIPTION TEST CONDITIONS LOGIC CHARACTERISTICS VIX_LH Logic Input Threshold - Low-to-High VIX_HL Logic Input Threshold - High-to-Low lIL = 1µA: VIN-A, VIN-B Logic Input Hysteresis VIN-A, VIN-B VIH Logic Input High Threshold PD 2.0 VDD V VIL Logic Input Low Threshold PD 0 0.8 V VIH Logic Input High Threshold ENABLE - QFN only 2.0 VDD V VIL Logic Input Low Threshold ENABLE - QFN only 0 0.8 V VHYS 0.2 V V IIX_H Input Current Logic High VIN-A, VIN-B = VDD 10 20 nA IIX_L Input Current Logic Low VIN-A, VIN-B = 0V 10 20 nA II_H Input Current Logic High PD = VDD 10 20 nA II_L Input Current Logic Low PD = 0V 10 15 nA II_H Input Current Logic High ENABLE = VDD (QFN only) 12 µA II_L Input Current Logic Low ENABLE = 0V (QFN only) -25 nA DRIVER CHARACTERISTICS rDS Driver Output Resistance IDC Driver Output DC Current (>2s) IAC Peak Output Current Design Intent; verified via simulation. Driver Output Swing Range OA or OB = “1”, voltage referenced to GND VOH to VOL FN6228 Rev 9.0 Apr 29, 2021 OA, OB 3 3 6 Ω 100 mA 3.5 A 13.2 V Page 4 of 18 ISL55110, ISL55111 DC Electrical Specifications PARAMETER VH = +12V, VDD = 2.7V to 5.5V, TA = +25°C, unless otherwise specified. (Continued) DESCRIPTION TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNITS 4.0 6.0 mA SUPPLY CURRENTS IDD IDD-PDN IH IH_PDN Logic Supply Quiescent Current PD = Low Logic Supply Power-down Current PD = High 12 µA Driver Supply Quiescent Current PD = Low, outputs unloaded 15 µA Driver Supply Power-down Current PD = High 2.5 µA MAX (Note 8) UNITS AC Electrical Specifications PARAMETER VH = +12V, VDD = +3.6V, TA = +25°C, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN (Note 8) TYP SWITCHING CHARACTERISTICS tR Driver Rise Time Figure 2, OA, OB: CL = 100pF/1k 10% to 90%, VOH - VOL = 12V 1.2 ns tF Driver Fall Time Figure 2, OA, OB: CL = 100pF/1k 10% to 90%, VOH - VOL = 12V 1.4 ns tR Driver Rise Time Figure 2, OA, OB: CL = 1nF 10% to 90%, VOH - VOL = 12V 6.2 ns tF Driver Fall Time Figure 2, OA, OB: CL = 1nF 10% to 90%, VOH - VOL = 12V 6.9 ns tpdR Input to Output Propagation Delay Figure 3, load 100pF/1k 10.9 ns tpdF Input to Output Propagation Delay 10.7 ns tpdR Input to Output Propagation Delay 12.8 ns tpdF Input to Output Propagation Delay 12.5 ns tpdR Input to Output Propagation Delay 14.5 ns tpdF Input to Output Propagation Delay 14.1 ns Figure 3, load 330pF Figure 3, load 680pF tSkewR Channel-to-Channel tpdR Spread with Same Loads Both Channels Figure 3, All loads