DATASHEET
ISL59910, ISL59913
FN6406
Rev 1.00
Sep 28, 2018
Triple Differential Receiver/Equalizer
The ISL59910 and ISL59913 are triple channel differential
receivers and equalizers. They each contain three high speed
differential receivers with five programmable poles. The
outputs of these pole blocks are then summed into an output
buffer. The equalization length is set with the voltage on a
single pin. The ISL59910 and ISL59913 output can also be
put into a high impedance state, enabling multiple devices to
be connected in parallel and used in multiplexing applications.
The gain can be adjusted up or down on each channel by 6dB
using the VGAIN control signal. In addition, a further 6dB of gain
can be switched in to provide a matched drive into a cable.
The ISL59910 and ISL59913 have a bandwidth of 150MHz
and consume just 108mA on ±5V supply. A single input
voltage sets the compensation levels for the required length
of cable.
The ISL59910 is a special version of the ISL59913 that
decodes syncs encoded onto the common modes of three
pairs of CAT-5 cable by the EL4543 refer to the EL4543
datasheet for details.
The ISL59910 and ISL59913 are available in a 28 Ld QFN
package and are specified for operation across the full -40°C
to +85°C temperature range.
Features
• 150MHz -3dB bandwidth
• CAT-5 compensation
- 100MHz at 600ft
- 135MHz at 300ft
• 108mA supply current
• Differential input range: 3.2V
• Common-mode input range: -4V to +3.5V
• ±5V supply
• Output to within 1.5V of supplies
• Available in 28 Ld QFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Twisted-pair receiving/equalizer
• KVM (Keyboard/Video/Mouse)
• VGA over twisted-pair
• Security video
Related Literature
For a full list of related documents, visit our website:
• ISL59910 and ISL59913 product pages
FN6406 Rev 1.00
Sep 28, 2018
Page 1 of 13
ISL59910, ISL59913
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TAPE AND REEL
(UNITS) (Note 1)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL59910IRZ
59910 CRZ
-
28 Ld QFN
L28.4x5
ISL59910IRZ-T7
59910 CRZ
1k
28 Ld QFN
L28.4x5
ISL59913IRZ
59913 IRZ
-
28 Ld QFN
L28.4x5
ISL59913IRZ-T7
59913 IRZ
1k
28 Ld QFN
L28.4x5
ISL59913IRZ-EVALZ
Evaluation Board
ISL59910IRZ-EVALZ
Evaluation Board
NOTES:
1. Refer to TB347 for details about reel specifications.
2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL59910 and ISL59913 product information pages. For more information about MSL, see TB363.
Pinouts
23 VCM_R
24 VCM_G
25 VCM_B
27 ENABLE
28 0V
23 HOUT
24 VOUT
25 SYNCREF
26 X2
27 ENABLE
28 0V
26 X2
ISL59913
(28 LD QFN)
TOP VIEW
ISL59910
(28 LD QFN)
TOP VIEW
VSMO_B 1
22 VSP
VSMO_B 1
22 VSP
VOUT_B 2
21 VINM_B
VOUT_B 2
21 VINM_B
VSPO_B 3
20 VINP_B
VSPO_B 3
20 VINP_B
19 VINM_G
VSPO_G 4
18 VINP_G
VOUT_G 5
VSMO_G 6
17 VINM_R
VSMO_G 6
17 VINM_R
VSMO_R 7
16 VINP_R
VSMO_R 7
16 VINP_R
VOUT_R 8
15 VSM
VOUT_R 8
15 VSM
19 VINM_G
VGAIN_B 14
18 VINP_G
VGAIN_G 13
VGAIN_R 12
VREF 11
THERMAL
PAD
VCTRL 10
VGAIN_B 14
VGAIN_G 13
VGAIN_R 12
VCTRL 10
VSPO_R 9
VOUT_G 5
VREF 11
THERMAL
PAD
VSPO_R 9
VSPO_G 4
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
Pin Descriptions
ISL59910
PIN
NUMBER
PIN NAME
1
VSMO_B
PIN FUNCTION
ISL59913
PIN NAME
PIN FUNCTION
-5V to blue output buffer
VSMO_B
-5V to blue output buffer
2
VOUT_B
Blue output voltage referenced to 0V pin
VOUT_B
Blue output voltage referenced to 0V pin
3
VSPO_B
+5V to blue output buffer
VSPO_B
+5V to blue output buffer
4
VSPO_G
+5V to green output buffer
VSPO_G
+5V to green output buffer
FN6406 Rev 1.00
Sep 28, 2018
Page 2 of 13
ISL59910, ISL59913
Pin Descriptions
(Continued)
ISL59910
ISL59913
PIN
NUMBER
PIN NAME
5
VOUT_G
Green output voltage referenced to 0V pin
VOUT_G
Green output voltage referenced to 0V pin
6
VSMO_G
-5V to green output buffer
VSMO_G
-5V to green output buffer
7
VSMO_R
-5V to red output buffer
VSMO_R
-5V to red output buffer
8
VOUT_R
Red output voltage referenced to 0V pin
VOUT_R
Red output voltage referenced to 0V pin
9
VSPO_R
+5V to red output buffer
VSPO_R
+5V to red output buffer
10
VCTRL
11
VREF
12
VGAIN_R
Red channel gain voltage (0V to 1V)
VGAIN_R
Red channel gain voltage (0V to 1V)
13
VGAIN_G
Green channel gain voltage (0V to 1V)
VGAIN_G
Green channel gain voltage (0V to 1V)
14
VGAIN_B
Blue channel gain voltage (0V to 1V)
VGAIN_B
Blue channel gain voltage (0V to 1V)
15
VSM
PIN FUNCTION
Equalization control voltage (0V to 0.95V)
Reference voltage for logic signals, VCTRL, and
VGAIN pins
-5V to core of chip
PIN NAME
VCTRL
VREF
VSM
PIN FUNCTION
Equalization control voltage (0V to 0.95V)
Reference voltage for logic signals, VCTRL, and
VGAIN pins
-5V to core of chip
16
VINP_R
Red positive differential input
VINP_R
Red positive differential input
17
VINM_R
Red negative differential input
VINM_R
Red negative differential input
18
VINP_G
Green positive differential input
VINP_G
Green positive differential input
19
VINM_G
Green negative differential input
VINM_G
Green negative differential input
20
VINP_B
Blue positive differential input
VINP_B
Blue positive differential input
21
VINM_B
Blue negative differential input
VINM_B
Blue negative differential input
22
VSP
23
HOUT
Decoded horizontal sync referenced to
SYNCREF
VCM_R
Red common-mode voltage at inputs
24
VOUT
Decoded vertical sync referenced to SYNCREF
VCM_G
Green common-mode voltage at inputs
25
SYNCREF
Reference level for HOUT and VOUT logic outputs
VCM_B
Blue common-mode voltage at inputs
26
X2
27
ENABLE
28
0V
Thermal Pad
FN6406 Rev 1.00
Sep 28, 2018
+5V to core of chip
Logic signal for x1/x2 output gain setting
Chip enable logic signal
0V reference for output voltage
VSP
X2
ENABLE
0V
+5V to core of chip
Logic signal for x1/x2 output gain setting
Chip enable logic signal
0V reference for output voltage
Must be connected to -5V
Page 3 of 13
ISL59910, ISL59913
Absolute Maximum Ratings
Operating Conditions
(TA = +25°C)
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . .12V
Maximum Continuous Output Current per Channel. . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . See “Typical Performance Curves”
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can permanently damage the device. This is a stress only rating and operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are ensured. Typ values are for information purposes only. Unless otherwise noted, all tests are at
the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
Bandwidth
BW
(See Figure 1)
150
MHz
Slew Rate
SR
VIN = -1V to +1V, VG = 0.39, VC = 0,
RL = 75 + 75
1.5
kV/µs
THD
10MHz 2VP-P out, VG = 1V, X2 gain,
VC = 0
-50
dBc
Total Harmonic Distortion
DC PERFORMANCE
Offset Voltage
Channel-to-Channel Offset Matching
V(VOUT)OS
X2 = high, no equalization
-110
-15
+110
mV
VOS
X2 = high, no equalization
-140
0
+140
mV
INPUT CHARACTERISTICS
Common-Mode Input Range
CMIR
-4/+3.5
V
Output Noise
ONOISE
VG = 0V, VC = 0V, X2 = HIGH,
RLOAD = 150Ω Input 50Ω to GND,
10MHz
-110
dBm
Common-Mode Rejection Ratio
CMRR
Measured at 10kHz
-80
dB
Common-Mode Rejection Ratio
CMRR
Measured at 10MHz
-55
dB
CM Amplifier Bandwidth
CMBW
10k || 10pF load
50
MHz
CM Slew Rate
CMSLEW
Measured at +1V to -1V
100
V/µs
Differential Input Capacitance
CINDIFF
Capacitance VINP to VINM
600
fF
Differential Input Resistance
RINDIFF
Resistance VINP to VINM
CM Input Capacitance
CINCM
Capacitance VINP = VINM to GND
CM Input Resistance
RINCM
Resistance VINP = VINM to GND
Positive Input Current
+IIN
DC bias at VINP = VINM = 0V
Negative Input Current
-IIN
DC bias at VINP = VINM = 0V
Differential Input Range
VINDIFF
VINP - VINM when slope gain falls to 0.9
Output Voltage Swing
V(VOUT)
RL = 150Ω
Output Drive Current
I(VOUT)
RL = 10Ω, VINP = 1V, VINM = 0V,
X2 = high, VG = 0.39
CM Output Resistance of
VCM_R/G/B (ISL59913 only)
R(VCM)
At 100kHz
1
MΩ
1.2
pF
1
MΩ
1
µA
1
µA
2.5
V
OUTPUT CHARACTERISTICS
Gain
VC = 0, VG = 0.39, X2 = 5, RL = 150Ω
Channel-to-Channel Gain Matching
Gain at DC
Channel-to-Channel Gain Matching
Gain at
15MHz
Gain
FN6406 Rev 1.00
Sep 28, 2018
50
0.85
±3.5
V
60
mA
30
Ω
1.0
1.1
VC = 0, VG = 0.39, X2 = 5, RL = 150Ω
3
8
%
VC = 0.6, VG = 0.39, X2 = 5, RL = 150Ω,
Frequency = 15MHz
3
11
%
Page 4 of 13
ISL59910, ISL59913
Electrical Specifications
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25°C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
High Level output on V/HOUT
(ISL59910 only)
V(SYNC)HI
V(VSP)
- 0.1V
V(VSP)
Low Level output on V/HOUT
(ISL59910 only)
V(SYNC)LO
V(SYNCREF)
V(SYNCREF)
+ 0.1V
UNIT
SUPPLY
Supply Current per Channel
ISON
VENBL = 5, VINM = 0
32
Supply Current per Channel
ISOFF
VENBL = 0, VINM = 0
0.2
Power Supply Rejection Ratio
PSRR
DC to 100kHz, ±5V supply
36
39
mA
0.4
mA
65
dB
LOGIC CONTROL PINS (ENABLE, X2)
Logic High Level
VHI
VIN - VLOGIC reference for ensured high
level
Logic Low Level
VLOW
VIN - VLOGIC reference for ensured low
level
0.8
V
1.4
V
Logic High Input Current
ILOGICH
VIN = 5V, VLOGIC = 0V
50
µA
Logic Low Input Current
ILOGICL
VIN = 0V, VLOGIC = 0V
15
µA
Typical Performance Curves
5
X2 = HIGH
VGAIN = 0.35V
VCTRL = 0V
RLOAD = 150Ω
GAIN (dB)
X2 = LOW
VGAIN = 0V
3 VCTRL = 0V
RLOAD = 150Ω
1
-1
-3
-5
1M
10M
100M 200M
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE OF ALL CHANNELS
X2 = LOW
VS = ±5V
RL = 150Ω
VGAIN = 0V
VCTRL = 0.1V STEPS
Source = -20dBm
VCTRL = 1V
FIGURE 2. GAIN vs FREQUENCY ALL CHANNELS
X2 = LOW
VS = ±5V
RL = 150Ω
Source = -20dBm
VCTRL = 0.25V
VGAIN = 0.25V
VCTRL = 0V
VGAIN = 0.25V
VCTRL = 0V
VGAIN = 0V
VCTRL = 0V
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS VCTRL
FN6406 Rev 1.00
Sep 28, 2018
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS VCTRL AND
VGAIN
Page 5 of 13
ISL59910, ISL59913
Typical Performance Curves (Continued)
VCTRL = 1V
CABLE = 600FT
X2 = LOW
VCTRL = 1V
VS = ±5V
CABLE = 3FT
RL = 150
VGAIN = 1V
SOURCE = -20dBm
X2 = LOW
VGAIN = 0.5V
VCTRL = 0.5V
RLOAD = 150Ω
VCTRL = 0V
CABLE = 3FT
VCTRL = 0V
CABLE = 600FT
FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS VCTRL AND
CABLE LENGTHS
VS = ±5V, RL = 150Ω
INPUT 50Ω TO GROUND
X2 = LOW
X2 = HIGH
X2 = HiGH
VCTRL = 0V
FIGURE 7. OFFSET vs VCTRL
X2 = HIGH
VS = ±5V
RL = 150Ω
VCTRL = 0V
VGAIN = 1V
FIGURE 8. DC GAIN vs VGAIN
X2 = HIGH
VS = ±5V
RL = 150Ω
INPUT = 50Ω TO GROUND
VCTRL = 0V
VGAIN = 0V
3rd
HARMONIC
2nd
HAMONIC
FIGURE 9. HARMONIC DISTORTION vs FREQUENCY
FN6406 Rev 1.00
Sep 28, 2018
VCTRL = 0V
RLOAD = 150Ω
INPUT = 50ΩTO GND
VGAIN = 1V
X2 = LOW
VCTRL = 0V
TOTAL
HARMONIC
FIGURE 6. CHANNEL MISMATCH
VCTRL = 0V
VGAIN = 1V
VCTRL = 1V
VGAIN = 1V
VCTRL = 1V
VGAIN = 0V
FIGURE 10. OUTPUT NOISE
Page 6 of 13
ISL59910, ISL59913
Typical Performance Curves (Continued)
-10
4
VGAIN = 0.35V
(ALL CHANNELS)
2 VCTRL = 0V
RLOAD = 150Ω
X2 = HIGH
GAIN (dB)
CMRR (dB)
VGAIN = 0.35V
(ALL CHANNELS)
-20 VCTRL = 0V
X2 = HIGH
-40
-60
-80
0
-2
-4
-100
100k
1M
10M
-6
100k
100M
1M
FIGURE 11. COMMON-MODE REJECTION
FIGURE 12. CM AMPLIFIER BANDWIDTH
0
-20
VCC = 5V
VCTRL = 0V
-20 VGAIN = 0V
(ALL CHANNELS)
INPUTS ON GND
VEE = -5V
VCTRL = 0V
-40 VGAIN = 0V
(ALL CHANNELS)
INPUTS ON GND
-PSRR (dB)
+PSRR (dB)
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
-40
-60
-60
-80
-100
-80
-100
10
10M
100
1k
10k
100k
1M
10M
100M
-120
10
100
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. (+)PSRR vs FREQUENCY
1k
FIGURE 14. (-)PSRR vs FREQUENCY
BLUE
GREEN
X2 = HGH
RLOAD = 150Ω
VGAIN = 0V
VCTRL = 0V
CABLE = 3 FT
FIGURE 15. BLUE CROSSTALK (CABLE LENGTH = 3ft.)
FN6406 Rev 1.00
Sep 28, 2018
RED
X2 = LOW
VS = ±5V
RL = 150Ω
VCTRL = 1V
VGAIN = 1V
FIGURE 16. BLUE CROSSTALK (CABLE LENGTH = 600ft.)
Page 7 of 13
ISL59910, ISL59913
Typical Performance Curves (Continued)
GREEN
RED
X2 = LOW
VS = ±5V
RL = 150Ω
VCTRL = 1V
VGAIN = 1V
BLUE
FIGURE 17. GREEN CROSSTALK (CABLE LENGTH = 3ft.)
FIGURE 18. GREEN CROSSTALK (CABLE LENGTH = 600ft.)
RED
GREEN
BLUE
FIGURE 19. RED CROSSTALK (CABLE LENGTH = 3ft.)
X2 = LOW
VS = ±5V
RL = 150Ω
VCTRL = 1V
VGAIN = 1V
FIGURE 20. RED CROSSTALK (CABLE LENGTH =600ft.)
VCTRL = 0V
CABLE = 3FT
VCTRL = 0.2V
CABLE = 600FT
X2 = HIGH
VS = ±5V
RL = 150Ω
VGAIN = 0V
INPUT = 10MHz
FIGURE 21. RISE TIME AND FALL TIME
FN6406 Rev 1.00
Sep 28, 2018
FIGURE 22. PULSE RESPONSE FOR VARIOUS CABLE
LENGTHS
Page 8 of 13
ISL59910, ISL59913
Typical Performance Curves (Continued)
4.5
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
1.2
POWER DISSIPATION (W)
POWER DISSIPATION (W)
4
3.5 3.378W
3
JA
2.5
=
QF
37
2
N2
°C
8
/W
1.5
1
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
893mW
0.8
JA
0.6
QF
N
= 1 28
40
°C
/W
0.4
0.2
0.5
0
0
0
25
50
75 85 100
125
150
Applications Information
Logic Control
The ISL59913 has two logical input pins, Chip Enable
(ENABLE) and Switch Gain (X2). The logic circuits all have a
nominal threshold of 1.1V above the potential of the logic
reference pin (VREF). In most applications it is expected that
this chip runs from a +5V, 0V, -5V supply system with logic
being run between 0V and +5V. In this case, tie the logic
reference voltage to the 0V supply. If the logic is referenced to
the -5V rail, connect the logic reference to -5V. The logic
reference pin sources about 60µA and this rises to about
200µA if all inputs are true (positive).
The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs sink a
current dependent on the high level, up to 50µA for a high level
5V above the reference level.
If the logic inputs are not used, tie them to the appropriate
voltage to define their state.
Control Reference and Signal Reference
Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range 0V to
1V, which are referenced to the control reference pin. It is
expected that the control reference pin is tied to 0V and the
control voltage varies from 0V to 1V. It is, however, acceptable
to connect the control reference to any potential between -5V
and 0V to which the control voltages are referenced.
The control voltage pins themselves are high impedance. The
control reference pin sources between 0µA and 200µA
depending on the control voltages being applied.
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
0
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
define the 0V level of the single-ended output signal. The
reference for the output signal is provided by the 0V pin. The
output stage cannot pull fully up or down to either supply so it is
important that the reference is positioned to allow full output
swing. Tie the 0V reference to a quiet reference as any noise on
this pin is transferred directly to the output. The 0V pin is a high
impedance pin and draws DC bias currents of a few µA and
similar levels of AC current.
Equalizing
When transmitting a signal across a twisted pair cable, the high
frequency (above 1MHz) information is attenuated more
significantly than the information at low frequencies. The
attenuation is predominantly due to resistive skin effect losses
and has a loss curve which depends on the resistivity of the
conductor, surface condition of the wire, and the wire diameter.
For the range of high performance twisted pair cables based
on 24awg copper wire (CAT-5 etc), these parameters vary only
a little between cable types and in general cables exhibit the
same frequency dependence of loss. (The lower loss cables
can be compared with somewhat longer lengths of similar
cables.) This enables a single equalizing law equation to be
built into the ISL59913.
With a control voltage applied between pins VCTRL and VREF,
the frequency dependence of the equalization is shown in
Figure 8 on page 6. The equalization matches the cable loss
up to about 100MHz. Above this, system gain is rolled off
rapidly to reduce noise bandwidth. The roll-off occurs more
rapidly for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise increases as the equalization
increases.
The control reference and logic reference effectively remove the
necessity for the 0V rail and operation from ±5V (or 0V and 10V)
only is possible. However, we still need a further reference to
FN6406 Rev 1.00
Sep 28, 2018
Page 9 of 13
ISL59910, ISL59913
Contrast
VOLTAGE
(0.5V/DIV)
BLUE CM
OUT (CH A)
GREEN CM
OUT (CH B)
RED CM
OUT (CH C)
VSYNC
VOLTAGE
(2.5V/DIV)
By varying the voltage between pins VGAIN and VREF, the gain
of the signal path can be changed in the ratio 4:1. The gain
change varies almost linearly with control voltage. For normal
operation it is anticipated the X2 mode is selected and the
output load is back matched. A unity gain to the output load is
achieved with a gain control voltage of about 0.35V. This allows
the gain to be trimmed up or down by 6dB to compensate for
any gain/loss errors that affect the contrast of the video signal.
Figure 25 shows an example plot of the gain to the load with
gain control voltage.
HSYNC
TIME (0.5ms/DIV)
2
FIGURE 26. H AND V SYNCS ENCODED
1.8
GAIN (V)
1.6
TABLE 1. H AND V SYNC DECODING
1.4
1.2
1
0.8
0.6
0.4
0
0.2
0.4
0.6
0.8
1
RED CM
GREEN CM
BLUE CM
HSYNC
VSYNC
Mid
High
Low
Low
Low
High
Low
Mid
Low
High
Low
High
Mid
High
Low
Mid
Low
High
High
High
NOTE: Level ‘Mid’ is halfway between ‘High’ and ‘Low’
VGAIN
FIGURE 25. VARIATION OF GAIN WITH GAIN CONTROL
VOLTAGE
Common-Mode Sync Decoding
The ISL59910 features common-mode decoding to allow
horizontal and vertical synchronization information, which has
been encoded on the three differential inputs by the EL4543, to
be decoded. The entire RGB video signal can therefore be
transmitted, along with the associated synchronization
information, by using just three twisted pairs.
Decoding is based on the EL4543 encoding scheme, as
described in Figure 26 and Table 1. The scheme is a three-level
system, which has been designed such that the sum of the
common-mode voltages results in a fixed average DC level with
no AC content. This eliminates the effect of EMI radiation into the
common-mode signals along the twisted pairs of the cable
The common-mode voltages are initially extracted by the
ISL59910 from the three input pairs. These are then passed to an
internal logic decoding block to provide Horizontal and Vertical
sync output signals (HOUT and VOUT).
FN6406 Rev 1.00
Sep 28, 2018
Power Dissipation
The ISL59910 and ISL59913 are designed to operate with ±5V
supply voltages. The supply currents are tested in production
and specified to be less than 39mA per channel. Operating at
±5V power supply, the total power dissipation is:
V OUTMAX
PD MAX = 3 2 V S I SMAX + V S - V OUTMAX ---------------------------R
L
(EQ. 1)
where:
• PDMAX = Maximum power dissipation
• VS = Supply voltage = 5V
• ISMAX = Maximum quiescent supply current per
channel = 39mA
• VOUTMAX = Maximum output voltage swing of the
application = 2V
• RL = Load resistance = 150Ω
PD MAX = 1.29W
(EQ. 2)
Page 10 of 13
ISL59910, ISL59913
JA required for long term reliable operation can be calculated
using Equation 3:
TJ – TA
JA = ------------------------ = 50.4CW
PD
(EQ. 3)
where
• TJ is the maximum junction temperature (+150°C)
• TA is the maximum ambient temperature (+85°C)
For a QFN 28 package in a properly laid out PCB heatsinking
copper area, +37°C/W JA thermal resistance can be
achieved. To disperse the heat, the bottom heatspreader must
be soldered to the PCB. Heat flows through the heatspreader
to the circuit board copper, then spreads and converts to air.
Thus the PCB copper plane becomes the heatsink. This has
proven to be a very effective technique.
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
Sep 28, 2018
FN6406.1
FN6406 Rev 1.00
Sep 28, 2018
CHANGE
Added Related Literature section.
Moved Pinouts after Ordering Information table.
Updated Ordering Information table by updating brand for ISL59913 parts, adding Notes 1 and 3,
adding Evaluation boards, updating POD number, and updating tape and reel column.
Added Revision History.
Updated disclaimer and moved to end of document.
Updated POD from MDP0046 to L28.4x5.
Page 11 of 13
ISL59910, ISL59913
Package Outline Drawing
L28.4x5
For the most recent package outline drawing, see L28.4x5.
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/06
A
2.65
0.40
B
23
22
1
3.65
5.00
PIN #1 INDEX AREA
CHAMFER 0.400 X 45°
28
0.50
0.10
2X
4.20
4.00
0.5x7=3.50 REF
PIN 1
INDEX AREA
8
15
14
9
0.50
0.25
TOP VIEW
0.10 M C A B
0.5x5=2.50 REF
3.20 REF
BOTTOM VIEW
SEE DETAIL ''X''
MAX. 1.00
0.10 C
PACKAGE
BOUNDARY
C
(0.40)
SEATING PLANE
0.08 C
0.00-0.05
SIDE VIEW
(3.65)
(4.200)
(28X 0.25)
(0.50)
C
0.20REF
5
0~0.05
(28X 0.60)
(2.65)
DETAIL "X"
(3.20)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal ±0.05
Angular ±2°
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994.
4. Bottom side Pin#1 ID is diepad chamfer as shown.
5. Tiebar shown (if present) is a non-functional feature.
FN6406 Rev 1.00
Sep 28, 2018
Page 12 of 13
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