DATASHEET
ISL6161
FN9104
Rev.7.00
Aug 16, 2018
Dual Power Distribution Controller
The ISL6161 is a hot swap dual supply power distribution
controller that can be used in PCI Express (PCIe) applications.
Two external N-channel MOSFETs are driven to distribute and
control power while providing load fault isolation. At turn-on,
the gate of each external N-channel MOSFET is charged with a
10µA current source. Capacitors on each gate create a
programmable ramp (soft turn-on) to control in-rush currents,
as Figure 1 shows. A built-in charge pump supplies the gate
drive for the 12V supply N-channel MOSFET switch.
Two external current sense resistors and FETs provide
overcurrent (OC) protection. When the current through either
resistor exceeds the user programmed value, the controller
enters Current Regulation mode. The timeout capacitor, CTIM,
starts charging as the controller enters the timeout period.
When CTIM charges to a 2V threshold, both N-Channel
MOSFETs are latched off. In the event of a hard and fast fault
of at least three times the programmed current limit level, the
N-channel MOSFET gates are pulled low immediately before
entering the timeout period. The controller is reset by a rising
edge on the ENABLE pin.
The ISL6161 constantly monitors both output voltages and
reports either one being low on the PGOOD output as a low.
The 12V PGOOD Voltage Threshold (Vth) is ~10.8V and the
3.3V Vth is ~2.85V nominally.
Features
• Hot swap dual power distribution and control for +12V and
+3.3V rails
• Provides fault isolation
• Programmable current regulation level
• Programmable timeout
• Charge pump allows the use of N-channel MOSFETs
• Power-good and OC latch indicators
• Adjustable turn-on ramp
• Protection during turn-on
• Two levels of current limit detection provide fast response to
varying fault conditions
• 1µs response time to dead short
• 3µs response time to 200% current overshoot
• Pb-free available (RoHS compliant)
Applications
• PCIe applications
• Power distribution and control
• Hot plug and hot swap components
Related Literature
For a full list of related documents, visit our website
• ISL6161 product information page
CPUMP
RSENSE
RLOAD
12V
OPTIONAL
VDD RFILTER
CGATE
ISL6161
12VS 12VISEN
RILIM
12VG
VDD
CFILTER
ENABLE
INPUT
3.3V
ENABLE CTIM
PGOOD
3VG
3VS
CGATE
GND
CPUMP
RILIM
CTIM
3.3V
3ISEN
RSENSE
RLOAD
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FN9104 Rev.7.00
Aug 16, 2018
Page 1 of 14
12VS
OC
TO LOAD
12V
R
CLIM
100µA
+
2R
12VG
10µA
ENABLE
R QN
R
Q
S
VDD RFILTER
NC
POR
ENABLE
GND
QPUMP
12V
CPUMP
RISING
EDGE
RESET
10A
ENABLE
12V
CGATE
10µA
TO VDD
CPUMP
12V
100µA
ENABLE
3VG
RILIM
18V
VDD
OPTIONAL
CFILTER
RILIM
+
3X
18V
CGATE
FALLING
EDGE
DELAY
12ISEN
FALLING
EDGE
DELAY
CTIM
3X
+
CLIM
2R
R
3VS
+
2V
+
OC
CTIM
+
-
-
PGOOD
OC
LATCH
PGOOD
3ISEN
OPTIONAL
ISL6161
Page 2 of 14
RSENSE
3.3VIN
FIGURE 2. SIMPLIFIED SCHEMATIC (for 14 LD SOIC)
TO LOAD
ISL6161
FN9104 Rev.7.00
Aug 16, 2018
RSENSE
12VIN
ISL6161
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(Units) (Note 1)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
ISL6161IVZA-T
6161IVZ
-40 to +85
2.5k
16 Ld TSSOP
M16.173
ISL6161CBZA
6161CBZ
0 to +70
-
14 Ld SOIC
M14.15
ISL6161CBZA-T
6161CBZ
0 to +70
2.5k
14 Ld SOIC
M14.15
NOTE:
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL6161 product information. For more information about MSL, refer to TB363.
Pin Configurations
14 LD SOIC
TOP VIEW
16 LD TSSOP
TOP VIEW
12VS
1
14 12VISEN
12VS
1
16 12VISEN
12VG
2
13 RILIM
12VG
2
15 RILIM
VDD
3
12 GND
NC
4
11 CPUMP
ENABLE
5
10 CTIM
3VG
6
9
3VS
7
8
FN9104 Rev.7.00
Aug 16, 2018
NC
3
14 NC
VDD
4
13 GND
ENABLE
5
PGOOD
NC
6
12 CPUMP
11 CTIM
3VISEN
3VG
7
10 PGOOD
3VS
8
9
3VISEN
Page 3 of 14
ISL6161
Pin Descriptions
PIN #
SOIC
PIN #
TSSOP
SYMBOL
1
1
12VS
12V Source
Connect to the associated external N-channel MOSFET switch source to sense output voltage.
2
2
12VG
12V Gate
Connect to the associated N-channel MOSFET switch gate. A capacitor from this node to ground
sets the turn-on ramp. At turn-on, this capacitor will be charged to ~17.4V by a 10µA current
source.
3
4
VDD
Chip Supply
Connect to the 12V supply. This can be connected directly to the +12V rail supplying the load
voltage or to a dedicated VDD +12V supply. If connecting to the +12V rail supplying the load
voltage, pay special attention to VDD decoupling to prevent sagging as heavy loads are switched
on.
4
3,6,14
NC
Not Connected
Not connected.
5
5
ENABLE
Enable/Reset
Turns on and resets the chip. Both outputs turn on when this pin is driven low. After a current limit
timeout, the chip is reset by the rising edge of a reset signal applied to the ENABLE pin. This input
has 100µA pull-up capability, which is compatible with 3V and 5V open drain and standard logic.
6
7
3VG
3V Gate
Connect to the gate of the external 3V N-channel MOSFET. A capacitor from this node to ground
sets the turn-on ramp. At turn-on, this capacitor will be charged to ~11.9V by a 10µA current
source.
7
8
3VS
3V Source
Connect to the source side of 3V external N-channel MOSFET switch to sense output voltage.
8
9
3VISEN
3V Current Sense
Connect to the load side of the 3V sense resistor to measure the voltage drop across this resistor
between the 3VS and 3VISEN pins.
9
10
PGOOD
Power-Good
Indicator
Indicates that all output voltages are within specification. PGOOD is driven by an open drain
N-Channel MOSFET. It is pulled low when any output is not within specification.
10
11
CTIM
11
12
CPUMP
Charge Pump
Capacitor
Connect a 0.1µF capacitor between this pin and VDD (Pin 3). Provides charge storage for the
12VG drive.
12
13
GND
Chip Ground
Chip ground.
13
15
RILIM
Current Limit Set
Resistor
A resistor connected between this pin and ground determines the current level at which current
limit is activated. This current is determined by the ratio of the RILIM resistor to the sense resistor
(RSENSE). The current at current limit onset is equal to 10µA x (RILIM/RSENSE). The ISL6161 can
accommodate either a 10kΩ resistor (OC Vth = 100mV) or a 4.99kΩresistor for a lower trip
(OC Vth = 53mV). See Table 2 on page 7 for more details.
14
16
12VISEN
12V Current Sense
Connect to the load side of the sense resistor to measure the voltage drop across this resistor.
FN9104 Rev.7.00
Aug 16, 2018
FUNCTION
DESCRIPTION
Current Limit Timing Connect a capacitor from this pin to ground. This capacitor controls the time between the onset
Capacitor
of current limit and chip shutdown (current limit timeout). The duration of current limit timeout
(in seconds) = 200kΩ x CTIM (Farads).
Page 4 of 14
ISL6161
Absolute Maximum Ratings
Thermal Information
TA = 25°C
JA (°C/W)
Thermal Resistance (Typical, Note 4)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +16V
12VG, CPUMP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 21V
12VISEN, 12VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD + 0.3V
3VISEN, 3VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V to 7.5V
PGOOD, RILIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V
ENABLE, CTIM, 3VG. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
Maximum Junction Temperature (Plastic Package) . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to TB493
Operating Conditions
VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . +10.5V to +13.2V
Temperature Range (TA)
ISL6161IVZA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
ISL6161CBZA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. Refer to TB379 for details.
5. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5W, TA = TJ = -40°C to +85°C,
unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
92
100
108
mV
12V CONTROL
Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
3x Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
VIL12V
3 x VIL12V
RILIM = 10kΩ
RILIM = 5kΩ
47
53
59
mV
RILIM = 10kΩ
250
300
350
mV
RILIM = 5kΩ
100
165
210
mV
±20% Current Limit Response Time
(Current within 20% of Regulated Value)
20%iLrt
200% Current Overload, RILIM = 10kΩ,
RSHORT = 6.0Ω
-
2
-
µs
±10% Current Limit Response Time
(Current within 10% of Regulated Value)
10%iLrt
200% Current Overload, RILIM = 10kΩ,
RSHORT = 6.0Ω
-
4
-
µs
±1% Current Limit Response Time
(Current within 1% of Regulated Value)
1%iLrt
200% Current Overload, RILIM = 10kΩ,
RSHORT = 6.0Ω
-
10
-
µs
RTSHORT
C12VG = 0.01µF
-
500
-
ns
Gate Turn-On Time
tON12V
C12VG = 0.01µF
-
12
-
ms
Gate Turn-On Current
ION12V
C12VG = 0.01µF
8
10
12
µA
3x Gate Discharge Current
3XdisI
12VG = 18V
-
0.75
-
A
12V Undervoltage Threshold
12VVUV
10.5
10.8
11.0
V
Charge Pumped 12VG Voltage
V12VG
16.8
17.3
17.9
V
RILIM = 10kΩ
92
100
108
mV
RILIM = 5kΩ
47
53
59
mV
RILIM = 10kΩ
250
300
350
mV
RILIM = 5kΩ
100
155
210
mV
Response Time to Dead Short
CPUMP = 0.1µF
3.3V CONTROL
Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
3x Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
VIL3V
3 x VIL3V
±20% Current Limit Response Time
(Current within 20% of Regulated Value)
200% Current Overload, RILIM = 10kΩ,
RSHORT = 2.5Ω
-
2
-
µs
±10% Current Limit Response Time
(Current within 10% of Regulated Value)
200% Current Overload, RILIM = 10kΩ,
RSHORT = 2.5Ω
-
4
-
µs
FN9104 Rev.7.00
Aug 16, 2018
Page 5 of 14
ISL6161
Electrical Specifications VDD = 12V, CVG = 0.01µF, CTIM = 0.1µF, RSENSE = 0.1Ω, CBULK = 220µF, ESR = 0.5W, TA = TJ = -40°C to +85°C,
unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
200% Current Overload, RILIM = 10kΩ,
RSHORT = 2.5Ω
-
10
-
µs
RTSHORT
CVG = 0.01µF
-
500
Gate Turn-On Time
tON3V
CVG = 0.01µF
-
5
-
ms
Gate Turn-On Current
ION3V
CVG = 0.01µF
8
10
12
µA
3xdisI
CVG = 0.01µF, ENABLE = Low
0.75
-
A
3.3VVUV
2.7
2.85
3.0
V
3VG
11.2
11.9
-
V
IVDD
4
8
10
mA
VDD POR Rising Threshold
9.5
10.0
10.7
V
VDD POR Falling Threshold
9.0
9.4
9.8
V
-
20
-
ms
±1% Current Limit Response Time
(Current within 1% of Regulated Value)
Response Time To Dead Short
3x Gate Discharge Current
3.3V Undervoltage Threshold
3.3VG High Voltage
TEST CONDITIONS
ns
SUPPLY CURRENT AND IO SPECIFICATIONS
VDD Supply Current
Current Limit Timeout
tILIM
CTIM = 0.1µF
ENABLE Pull-Up Voltage
PWRN_V
1.8
2.4
3.2
V
ENABLE Rising Threshold
PWR_Vth
1.1
1.5
2
V
ENABLE Hysteresis
PWR_hys
0.1
0.2
0.3
V
ENABLE Pull-Up Current
PWRN_I
60
80
100
µA
Current Limit Timeout Threshold (CTIM)
CTIM_Vth
1.8
2
2.2
V
CTIM Charging Current
CTIM_I
8
10
12
µA
CTIM Discharge Current
CTIM_disI
1.7
2.6
3.5
mA
CTIM Pull-Up Current
CTIM_disI
VCTIM = 8V
3.5
5
6.5
mA
ENABLE Pin Open
RILIM Pin Current Source Output
RILIM_Io
90
100
110
µA
Charge Pump Output Current
Qpmp_Io
CPUMP = 0.1µF, CPUMP = 16V
320
560
900
µA
Charge Pump Output Voltage
Qpmp_Vo
No Load
17.2
17.4
-
V
Charge Pump Output Voltage - Loaded
Qpmp_VIo
Load Current = 100µA
16.2
16.7
-
V
Charge Pump POR Rising Threshold
Qpmp + Vth
15.6
16
16.5
V
Charge Pump POR Falling Threshold
Qpmp - Vth
15.2
15.7
16.2
V
ISL6161 Description and
Operation
The ISL6161 is a multi-featured +12V and +3.3V dual power supply
distribution controller. Its features include programmable Current
Regulation (CR) limiting and time to latch off.
At turn-on, the gate capacitor of each external N-channel MOSFET is
charged with a 10µA current source. These capacitors create a
programmable ramp (soft turn-on). A charge pump supplies the
gate drive for the 12V supply control FET switch, driving that gate to
17V.
capacitor, CTIM, starts charging with a 10µA current source and the
controller enters the timeout period. The timeout period length is set
by the single external capacitor (see Table 1 on page 7) placed from
the CTIM pin (Pin 10) to ground and is characterized by a lowered
gate drive voltage to the appropriate external N-channel MOSFET.
When CTIM charges to 2V, an internal comparator is tripped, and
both N-channel MOSFETs are latched off. If the voltage across the
sense resistors rises slowly in response to an OC condition, CR mode
is entered at ~95% of the programmed CR level. This is due to the
necessary hysteresis and response time in the CR control circuitry.
The load currents pass through two external current sense resistors.
When the voltage across either resistor quickly exceeds the user
programmed Current Regulation Voltage Threshold (CRVth) level,
the controller enters current regulation. The CRVth is set by the
external resistor value on the RILIM pin. At this time, the timeout
FN9104 Rev.7.00
Aug 16, 2018
Page 6 of 14
ISL6161
Application Considerations
TABLE 1. CTIM RECOMMENDATIONS
CTIM CAPACITOR
(µF)
NOMINAL TIME-OUT PERIOD (ms)
0.022
4.4
0.047
9.4
0.1
20
NOTE:
6. Nominal time-out period in seconds = CTIM x 200kΩ
Table 2 shows RSENSE and RILIM recommendations and the
resulting CR level for the specified PCIe add-in card connector sizes.
First select an RILIM value for the appropriate CRVth, then choose
the RSENSE value for the desired OC trip. Other applications can
select either 4.99kΩ or 10kΩ for RILIM; the accuracy of the CRVth is
measured for both. Values below 4.99kΩ are not recommended due
to possible noise sensitivity. Values between 4.99kΩ and 10kΩ can
be used, but are not measured for accuracy.
TABLE 2. RSENSE AND RILIM RECOMMENDATIONS
3.3V RSENSE 12V RSENSE
(mΩ
(mΩ
NOMINAL CR NOMINAL CR
(A)
(A)
NOMINAL
CRVth
(mV)
PCIe
ADD-IN CARD
CONNECTOR
RILIM
(kΩ
X1
10
30, 3.3
150, 0.7
100
4.99
15, 3.5
90, 0.6
53
10
30, 3.3
40, 2.5
100
4.99
15, 3.5
20, 2.6
53
10
30, 3.3
16, 6.3
100
4.99
15, 3.5
8, 6.6
53
X4/X8
X16
NOTE:
7. Nominal CR Vth = RILIM x 10µA = OC x RSENSE
The ISL6161 responds to a load short (defined as a current level
three times the OC set point with a fast transition) by
immediately driving the relevant N-channel MOSFET gate to 0V in
~3µs. The gate voltage is then slowly ramped up, soft-starting
the N-channel MOSFET to the programmed current regulation
limit level. This is the start of the timeout period if the abnormal
load condition still exists. The programmed current regulation
level is held until either the OC event ends or the timeout period
expires. If the OC event ends, the N-channel MOSFET is fully
enhanced and the CTIM charging current is diverted away from
the capacitor. If the timeout period expires before the OC event
ends, then both gates are quickly pulled to 0V, turning off both
N-Channel MOSFETs simultaneously.
Upon any UV condition, the PGOOD signal will pull low when tied
high through a resistor to the logic supply. This pin is a fault
indicator, but is not the OC latch-off indicator. For an OC latch-off
indication, monitor CTIM (Pin 10). This pin will rise rapidly to 12V
when the timeout period expires. See Figure 2 on page 2 for an
OC latch-off circuit suggestion.
The ISL6161 is reset by a rising edge on the ENABLE pin and is
turned on by the ENABLE pin being driven low.
FN9104 Rev.7.00
Aug 16, 2018
In a non PCIe, motor drive application, current loop stabilization
is facilitated through a small value resistor in series with the gate
timing capacitor. As the ISL6161 drives a highly inductive current
load, instability characterized by the gate voltage repeatedly
ramping up and down may occur. Stability can be easily
enhanced by substituting a larger gate resistor. Improve stability
by eliminating long point-to-point wiring to the load.
The ENABLE internal pull-up makes the ISL6161 well suited for
implementation on either side of the connector in which a
motherboard prebiased condition or a load board staggered
connection is present. In either case, the ISL6161 turns on in
Soft-Start mode, protecting the supply rail from sudden current
loading.
During the timeout delay period with the ISL6161 in current limit
mode, the VGS of the external N-channel MOSFETs is reduced,
driving the N-channel MOSFET switch into a high rDS(ON) state.
Thus, avoid extended timeout periods, because the external
N-Channel MOSFETs may be damaged or destroyed due to
excessive internal power dissipation. Refer to the MOSFET
manufacturer’s datasheet for SOA information.
With the high levels of inrush current (highly capacitive loads and
motor start-up currents), choosing the current regulation (CR)
level is crucial to provide both protection and still allow for this
inrush current without latching off. Consider this in addition to
the timeout delay when choosing MOSFETs for your design.
Physical layout of the RSENSE resistors is critical to avoid
inadvertently lowering the CR and trip levels. Ideally, trace
routing between the RSENSE resistors and the ISL6161 should be
as direct and as short as possible with zero current in the sense
lines.
CORRECT
INCORRECT
TO ISEN AND
RISET
CURRENT
SENSE RESISTOR
FIGURE 3. SENSE RESISTOR PCB LAYOUT
Monitor the xISEN pins to detect open loads. Although gated off,
the external FET IDSS will cause the xISEN pins to float above
ground to some voltage when no load is attached. If this is not
desired, 5k resistors from the xISEN pins to ground will prevent
the outputs from floating when the external switch FETs are
disabled and the outputs are open.
For PCIe applications, the ISL6161 and the ISL6118 provide the
fundamental hotswap function for the +12V and +3.3V main rails
and the +3.3V auxiliary rails, respectively, as shown in “PCI
Express Implementation” on page 10.
Page 7 of 14
ISL6161
Typical Performance Curves
.
8.4
105
SUPPLY CURRENT (mA)
8.2
CURRENT (µA)
8.0
7.8
7.6
104
103
7.4
7.2
-40
-30
-20 -10
0
10
20
30
40
50
60
70
80
102
-40
-30
-20
-10
TEMPERATURE (°C)
FIGURE 4. SUPPLY CURRENT
CTIM OC VOLTAGE THRESHOLD (V)
CTIM CURRENT SOURCE (µA)
60
70
80
2.04
10.6
10.5
10.4
-30 -20
-10
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
80
2.02
2.00
1.98
1.96
1.94
-40
10.920
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
80
3.3V UV THRESHOLD (V)
2.8750
10.902
10.886
10.870
-40
-30 -20 -10
FIGURE 7. CTIM OC VOLTAGE THRESHOLD
FIGURE 6. CTIM CURRENT SOURCE
12V UV THRESHOLD (V)
50
FIGURE 5. RILIM SOURCE CURRENT
10.7
10.3
-40
10 20 30 40
0
TEMPERATURE (°C)
-20
0
20
40
TEMPERATURE (°C)
FIGURE 8. 12V UV THRESHOLD
FN9104 Rev.7.00
Aug 16, 2018
60
80
2.8725
2.8700
2.8675
2.8650
-40
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 9. 3.3V UV THRESHOLD
Page 8 of 14
80
ISL6161
Typical Performance Curves
11.935
17.36
12V VG
17.32
11.920
11.915
17.30
11.910
3.3V VG
17.28
17.4
CHARGE PUMP VOLTAGE
NO LOAD
VOLTAGE (V)
11.925
3.3V GATE DRIVE (V)
12V GATE DRIVE (V)
17.6
11.930
17.34
17.26
-40
(Continued)
0
20
40
11.900
80
60
17.0
CHARGE PUMP VOLTAGE
100µA LOAD
16.8
11.905
-20
17.2
16.6
-40
-20
0
20
40
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 10. 12V, 3.3V GATE DRIVE
102.5
54.0
VOLTAGE THRESHOLD (mV)
VOLTAGE THRESHOLD (mV)
80
FIGURE 11. PUMP VOLTAGE
54.5
12V OC Vth
53.5
3.3V OC Vth
53.0
52.5
-40
60
-20
0
20
40
60
12V OC Vth
102.0
101.5
3.3V OC Vth
101.0
100.5
-40
80
-20
0
20
40
60
FIGURE 13. OC VOLTAGE THRESHOLD WITH RLIM = 10kΩ
FIGURE 12. OC VOLTAGE THRESHOLD WITH RLIM = 5kΩ
10.2
POWER ON RESET (V)
VDD LOW TO HIGH
10.0
9.8
9.6
-40
VDD HIGH TO LOW
-30 -20 -10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
FIGURE 14. POWER-ON RESET VOLTAGE THRESHOLD
FN9104 Rev.7.00
Aug 16, 2018
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Page 9 of 14
ISL6161
INTERSIL
ISL6161
INTERSIL
ISL6161
12V, 3.3V
POWER CONTROLLER
SLOT 1 PWREN#
SLOT 2 PWREN#
SLOT 1 PWRGD
+12V GATE SWITCH
SLOT 2 PWRGD
3.3V GATE SWITCH
3.3V
3.3V
+12V GATE SWITCH
12V, 3.3V
POWER CONTROLLER
3.3V GATE SWITCH
FN9104 Rev.7.00
Aug 16, 2018
PCI Express Implementation
CONTROLLER
3.3V
+12V
3.3V
PCI-EXPRESS SLOT 1
PCI-EXPRESS SLOT 2
SLOT 2 PWREN#
SLOT 1 PWREN#
3.3VAUX
Page 10 of 14
3.3VAUX
SLOT 2 PWRFLT#
SLOT 1 PWRFLT#
INTERSIL ISL6118
3.3VSB
DUAL 3.3VAUX
POWER CONTROLLER
FIGURE 15. PCI EXPRESS IMPLEMENTATION OF THE ISL6161 AND ISL6118
SLOT 2
PRSNT
SLOT 1 PRSNT
+12V
12V
+12V
ISL6161
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
Aug 16, 2018
FN9104.7
Updated Ordering information table by removing ISL6161IVZA, adding tape and reel parts, adding tape and
reel unit column, and updating Note 1.
Updated Disclaimer.
Jan 23, 2018
FN9104.6
-Applied new Header/Footer.
-Added Related Literature section to page 1.
-Cleaned up simplified schematic on page 2.
-Added ISL6161IVZA Information throughout document.
-Added MSL note (Note 3).
-Clarified RILIM in Pin Descriptions table on page 4.
-Fixed unit typo on page 9.
-Added caption to figure on page 10.
-Removed About Intersil verbiage.
Updated Disclaimer.
December 3, 2015
FN9104.5
Added Rev History and About Intersil Verbiage.
Updated Ordering Information on page 1.
Updated POD M14.15 to most current version. Rev change is as follows:
Added land pattern and moved dimensions from table onto drawing.
FN9104 Rev.7.00
Aug 16, 2018
Page 11 of 14
ISL6161
Package Outline Drawings
For the most recent package outline drawing, see M16.173.
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.65
0.09-0.20
END VIEW
TOP VIEW
H
1.00 REF
- 0.05
C
1.20 MAX
SEATING
PLANE
0.90 +0.15/-0.10
GAUGE
PLANE
0.25 +0.05/-0.06 5
0.10 M C B A
0.10 C
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
FN9104 Rev.7.00
Aug 16, 2018
Page 12 of 14
ISL6161
M14.15
For the most recent package outline drawing, see M14.15.
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 10/09
8.65
A 3
4
0.10 C A-B 2X
6
14
DETAIL"A"
8
0.22±0.03
D
6.0
3.9
4
0.10 C D 2X
0.20 C 2X
7
PIN NO.1
ID MARK
5
0.31-0.51
B 3
(0.35) x 45°
4° ± 4°
6
0.25 M C A-B D
TOP VIEW
0.10 C
1.75 MAX
H
1.25 MIN
0.25
GAUGE PLANE C
SEATING PLANE
0.10 C
0.10-0.25
1.27
SIDE VIEW
(1.27)
DETAIL "A"
(0.6)
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Datums A and B to be determined at Datum H.
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5. The pin #1 indentifier may be either a mold or mark feature.
(1.50)
6. Does not include dambar protrusion. Allowable dambar protrusion
shall be 0.10mm total in excess of lead width at maximum condition.
7. Reference to JEDEC MS-012-AB.
TYPICAL RECOMMENDED LAND PATTERN
FN9104 Rev.7.00
Aug 16, 2018
Page 13 of 14
Notice
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(Note 1)
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(Note 2)
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