DATASHEET
ISL6266, ISL6266A
FN6398
Rev 4.00
August 25, 2015
Two-phase Core Controllers (Montevina, IMVP-6+)
The ISL6266 and ISL6266A are two-phase buck converter
regulators implementing Intel® IMVP-6 protocol with
embedded gate drivers. Both converters use interleaved
channels to double the output voltage ripple frequency and
thereby reduce output voltage ripple amplitude with fewer
components, lower component cost, reduced power
dissipation, and smaller real estate area.
The ISL6266A utilizes the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
traditional multiphase buck regulators, the R3 Technology™
has the fastest transient response. This is due to the R3
modulator commanding variable switching frequency during
load transient events.
Intel Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology, which effectively reduces power
dissipation in Intel Pentium processors. To boost battery life,
the ISL6266A supports DPRSLRVR (deeper sleep),
DPRSTP# and PSI# functions, which maximizes efficiency
by enabling different modes of operation. In active mode
(heavy load), the regulator commands the two phase
continuous conduction mode (CCM) operation. When PSI#
is asserted in active mode (medium load), the ISL6266A
operates in one-phase CCM. When the CPU enters deeper
sleep mode, the ISL6266A enables diode emulation to
maximize efficiency.
For better system power management, the ISL6266A
provides a CPU power monitor output. The analog output at
the power monitor pin can be fed into an A/D converter to
report instantaneous or average CPU power.
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
Over-temperature, the ISL6266A achieves a 0.5% system
accuracy of core output voltage.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per Intel IMVP-6+
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or discrete resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
The ISL6266 also includes all the functions for IMVP-6+
core power delivery. In addition, it has been optimized for
use with coupled-inductor solutions. More information on the
differences between ISL6266 and ISL6266A can be found in
the “Electrical Specifications” on page 3 and the “ISL6266
Features” on page 21.
FN6398 Rev 4.00
August 25, 2015
Features
• Precision Two/One-phase CORE Voltage Regulator
- 0.5% System Accuracy Over-Temperature
- Enhanced Load Line Accuracy
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Support VID Change On-the-Fly
• Multiple Current Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• CPU Power Monitor
• Thermal Monitor
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Support All Ceramic Output with Coupled Inductor
(ISL6266)
• Overvoltage, Undervoltage and Overcurrent Protection
• Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6266HRZ
(No longer
available or
supported)
ISL6266 HRZ
-10 to +100 48 Ld 7x7 QFN L48.7x7
ISL6266HRZ-T*
(No longer
available or
supported)
ISL6266 HRZ
-10 to +100 48 Ld 7x7 QFN L48.7x7
ISL6266AIRZ
ISL6266A IRZ -40 to +100 48 Ld 7x7 QFN L48.7x7
ISL6266AIRZ-T* ISL6266A IRZ -40 to +100 48 Ld 7x7 QFN L48.7x7
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Page 1 of 31
ISL6266, ISL6266A
Pinout
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISL6266, ISL6266A
(48 LD 7x7 QFN)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
1
36 BOOT1
PSI#
2
35 UGATE1
PMON
3
34 PHASE1
RBIAS
4
33 PGND1
VR_TT#
5
32 LGATE1
NTC
6
SOFT
7
OCSET
8
29 PGND2
VW
9
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FB2 12
FN6398 Rev 4.00
August 25, 2015
13
14
15
16
17
18
19
20
21
22
23
24
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
GND
VDD
ISEN2
ISEN1
25 NC
Page 2 of 31
ISL6266, ISL6266A
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT to PHASE). . . . . . -0.3V to +7V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V (120µs
-3.5
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 >1ms
Undervoltage Threshold
(VDIFF-SOFT)
UVf
VO falling below setpoint for >1ms
9
-360
-300
mV
-240
mV
1
V
LOGIC INPUTS
VR_ON, DPRSLPVR Input Low
VIL(3.3V)
VR_ON, DPRSLPVR Input High
VIH(3.3V)
Leakage Current of VR_ON
IIL(3.3V)
Logic input is low
IIH(3.3V)
Logic input is high at 3.3V
Leakage Current of DPRSLPVR
2.3
IIL_DPRSLP(3.3V) DPRSLPVR input is low
-1
VIL(1V)
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH(1V)
Leakage Current of DAC
(VID0-VID6), PSI# and DPRSTP#
IIL(1V)
Logic input is low
IIH(1V)
Logic input is high at 1V
0
0
-1
IIH_DPRSLP(3.3V) DPRSLPVR input is high at 3.3V
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
V
µA
1
0
0.45
µA
µA
1
µA
0.3
V
0.7
-1
V
0
µA
0.45
1
µA
53
60
67
µA
1.18
1.2
1.22
V
6.5
9
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-Temperature Threshold
V(NTC) falling
VR_TT# Low Output Resistance
RTT
I = 20mA
POWER MONITOR
PMON Output Voltage Range
PMON Maximum Voltage
FN6398 Rev 4.00
August 25, 2015
Vpmon
Vpmonmax
VSEN = 1.2V, Droop - VO = 80mV
1.638
1.680
1.722
V
VSEN = 1V, Droop - VO = 20mV
0.308
0.350
0.392
V
2.8
3.0
V
Page 5 of 31
ISL6266, ISL6266A
Electrical Specifications
VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4) UNITS
PMON Sourcing Current
Isc_pmon
VSEN = 1V, Droop - VO = 50mV
2
mA
PMON Sinking Current
Isk_pmon
VSEN = 1V, Droop - VO = 50mV
2
mA
Maximum Current Sinking Capability
Refer to Figure 29
PMON/
250
PMON Impedance
When PMON is within its sourcing/sinking
current range (Note 3)
PMON/
180
PMON/
100
A
7
3.1
V
CLK_EN# OUTPUT LEVELS
CLK_EN# High Output Voltage
VOH
3V3 = 3.3V, I = -4mA
CLK_EN# Low Output Voltage
VOL
ICLK_EN# = 4mA
2.9
0.26
0.4
V
NOTES:
3. Limits established by characterization and are not production tested.
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
ISL6266, ISL6266A Gate Driver Timing Diagram
PWM
tPDHU
1V
UGATE
1V
LGATE
tFL
FN6398 Rev 4.00
August 25, 2015
tFU
tRU
tRL
tPDHL
Page 6 of 31
ISL6266, ISL6266A
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Functional Pin Description
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
1
36 BOOT1
PSI#
2
35 UGATE1
PMON
3
34 PHASE1
RBIAS
4
33 PGND1
VR_TT#
5
32 LGATE1
NTC
6
SOFT
7
OCSET
8
29 PGND2
VW
9
28 PHASE2
COMP 10
27 UGATE2
31 PVCC
GND PAD
(BOTTOM)
30 LGATE2
FB 11
26 BOOT2
FN6398 Rev 4.00
August 25, 2015
13
14
15
16
17
18
19
20
21
22
23
24
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
GND
VDD
ISEN2
ISEN1
25 NC
VDIFF
FB2 12
Page 7 of 31
ISL6266, ISL6266A
PGOOD - Power good open-drain output. Connect externally
with 680 to VCCP or 1.9k to 3.3V.
PSI# - Current indicator input. When asserted low, indicates a
reduced load-current condition and initiates single-phase
operation.
PMON - Analog output. PMON is proportional to the product of
Vsen and droop voltage.
RBIAS - 147k resistor to VSS sets internal current reference.
VR_TT# - Thermal overload output indicator with open-drain
output. Over-temperature pull-down resistance is 10.
NTC - Thermistor input to VRTT# circuit and a 60µA current
source is connected internally to this pin.
SOFT - A capacitor from this pin to GND sets the maximum
slew rate of the output voltage. SOFT is the non-inverting input
of the error amplifier.
OCSET - Overcurrent set input. A resistor from this pin to VO
sets DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
VW - A resistor from this pin to COMP programs the switching
frequency (for example, 6.45k 400kHz).
COMP - This pin is the output of the error amplifier.
FB - This pin is the inverting input of error amplifier.
FB2 - There is a switch between FB2 pin and the FB pin. The
switch is closed in single-phase operation and is opened in two
phase operation. The components connecting to FB2 are to
adjust the compensation in single phase operation to achieve
optimum performance.
VDIFF - This pin is the output of the differential amplifier.
VSEN - Remote core voltage sense input.
RTN - Remote core voltage sense return.
DROOP - Output of the droop amplifier. The voltage level on
this pin is the sum of VO and the droop voltage.
BOOT2 - This pin is the upper gate driver supply voltage for
Phase 2. An internal boot strap diode is connected to the
PVCC pin.
UGATE2 - Upper MOSFET gate signal for Phase 2.
PHASE2 - The phase node of Phase 2. Connect this pin to the
source of the Channel 2 upper MOSFET.
PGND2 - The return path of the lower gate driver for Phase 2.
LGATE2 - Lower-side MOSFET gate signal for Phase 2.
PVCC - 5V power supply for gate drivers.
LGATE1 - Lower-side MOSFET gate signal for Phase 1.
PGND1 - The return path of the lower gate driver for Phase 1.
PHASE1 - The phase node of phase 1. Connect this pin to the
source of the Channel 1 upper MOSFET.
UGATE1 - Upper MOSFET gate signal for Phase 1.
BOOT1 - This pin is the upper-gate-driver supply voltage for
Phase 1. An internal boot strap diode is connected to the
PVCC pin.
VID0, VID1, VID2, VID3, VID4, VID5, VID6 - VID input with
VID0 is the least significant bit (LSB) and VID6 is the most
significant bit (MSB).
VR_ON - Digital enable input. A logic high signal on this pin
enables the regulator.
DPRSLPVR - Deeper sleep enable signal. A logic high signal
on this pin indicates the micro-processor is in deeper-sleep
mode and also indicates a slow C4 entry or exit rate with 41µA
discharging or charging the SOFT capacitor.
DPRSTP# - Deeper sleep slow wake up signal. A logic low
signal on this pin indicates the micro-processor is in
deeper-sleep mode.
CLK_EN# - Digital output for system clock. Goes active 10µs
after VCORE is within 10% of Boot voltage.
3V3 - 3.3V supply voltage for CLK_EN#.
DFB - Inverting input to droop amplifier.
VO - An input to the IC that reports the local output voltage.
VSUM - This pin is connected to the summation junction of
channel current sensing.
VIN - Battery supply voltage. It is used for input voltage feed
forward to improve input line transient performance.
VSS - Signal ground. Connect to local controller ground.
VDD - 5V control power supply.
ISEN2 - Individual current sharing sensing for Channel 2.
ISEN1 - Individual current sharing sensing for Channel 1.
N/C - Not connected. Grounding this pin to signal ground in the
practical layout.
FN6398 Rev 4.00
August 25, 2015
Page 8 of 31
ISL6266, ISL6266A
PGND2
LGATE2
PHASE2
UGATE2
BOOT2
PGND1
LGATE1
PHASE1
UGATE1
BOOT1
VR_TT#
NTC
Functional Block Diagram
6µA
54µA
PVCC
PVCC
+
PVCC
PVCC
VDD
VIN
PVCC
1.2V
VIN
PVCC
1.24V
DRIVER
LOGIC
DRIVER
LOGIC
ULTRASONIC
TIMER
FLT
FLT
ISEN2
CURRENT
BALANCE
ISEN1
VSOFT
I_BALF
VIN
VIN
MODULATOR
MODULATOR
OC
CH1
CH2
Vw
PGOOD
MONITOR
AND LOGIC
FAULT AND
PGOOD
LOGIC
Vw
PHASE
SEQUENCER
PHASE
CONTROL
LOGIC
PGOOD
VO
E/A
VIN
FB
OC
VDIFF
+
+
1
+
-
+
+
1
0.5
RTN
VSUM
OCSET
VO
DROOP
+
10µA
DPRSTP#
DPRSLPVR
PSI#
VR_ON
VID6
VID5
-
MULTIPLIER
MODE CHANGE
REQUEST
SINGLE
PHASE
MODE
CONTROL
VID4
VID3
VID2
PMON
VO
DAC
VID1
SOFT
VSOFT
DACOUT
VID0
FB2
-
SINGLE
PHASE
SOFT
RBIAS
COMP
SINGLE
PHASE
VSEN
VO
-
DROOP
FLT
CH2
+
CH1
DFB
CLK_EN#
OC
VW
3V3
PGOOD
GND
VSOFT
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6266, ISL6266A
FN6398 Rev 4.00
August 25, 2015
Page 9 of 31
ISL6266, ISL6266A
Typical Performance Curves
1.16
100
90
1.14
70
VIN = 8.0V
60
VIN = 12.6V
VIN = 8.0V
1.12
VIN = 19.0V
VOUT (V)
EFFICIENCY (%)
80
50
40
VIN = 12.6V
1.10
VIN = 19.0V
1.08
30
20
1.06
10
0
0
5
10
15
20
25
30
35
40
45
1.04
50
0
10
20
IOUT (A)
FIGURE 2. ACTIVE MODE EFFICIENCY, 2-PHASE, CCM,
PSI# = HIGH, VID = 1.15V
40
50
FIGURE 3. ACTIVE MODE LOAD LINE, 2-PHASE, CCM,
PSI# = HIGH, VID = 1.15V
100
1.01
VIN = 8.0V
90
VIN = 12.6V
1.00
80
70
0.99
VIN = 8.0V
60
VIN = 12.6V
50
VOUT (V)
EFFICIENCY (%)
30
IOUT (A)
VIN = 19.0V
40
30
0.98
0.97
VIN = 19.0V
0.96
20
0.95
10
0
0
5
10
15
20
0.94
25
0
5
10
IOUT (A)
FIGURE 4. ACTIVE MODE EFFICIENCY, 1-PHASE, CCM,
PSI# = LOW, VID = 1.00V (ISL6266 ONLY)
25
0.765
90
0.764
80
0.763
70
60
50
40
VIN = 12.6V
VIN = 12.6V
0.762
VIN = 8.0V
VOUT (V)
EFFICIENCY (%)
20
FIGURE 5. ACTIVE MODE LOAD LINE, 1-PHASE, CCM,
PSI# = LOW, VID = 1.00V (ISL6266 ONLY)
100
VIN = 19.0V
30
0.761
0.760
0.759
VIN = 19.0V
20
0.758
10
0
15
IOUT (A)
0.1
1.0
IOUT (A)
FIGURE 6. DEEPER SLEEP MODE EFFICIENCY
FN6398 Rev 4.00
August 25, 2015
10.0
0.757
VIN = 8.0V
0
1
2
IOUT (A)
FIGURE 7. DEEPER SLEEP MODE LOAD LINE
Page 10 of 31
3
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
VR_ON
VOUT
VOUT
VSOFT
VR_ON
VSOFT
CSOFT = 15nF
FIGURE 8. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1V, ILOAD = 0A
CSOFT = 15nF
FIGURE 9. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VID = 1.4375V, ILOAD = 0A
CLK_EN#
VIN
IMVP-6_PWRGD
IIN
VOUT @ 1.15V
VOUT
FIGURE 10. SOFT-START WAVEFORM SHOWING CLK_EN#
AND IMVP-6 PGOOD
VR_ON
FIGURE 11. 8V TO 20V INPUT LINE TRANSIENT RESPONSE,
CIN = 240µF
DPRSTP#
VOUT
VID6
DPRSLPVR
IIN
VOUT
FIGURE 12. NRUSH CURRENT AT START-UP, VIN = 14.6V,
VID = 1.4375V, ILOAD = 5A
FN6398 Rev 4.00
August 25, 2015
FIGURE 13. SLOW C4 EXIT WITH DELAY OF DPRSLPVR,
FROM VID1000000 (0.7V) TO 0110000 (0.9V)
Page 11 of 31
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
VOUT
VOUT
FIGURE 14. LOAD STEP-UP RESPONSE AT THE CPU
SOCKET MPGA479, 35A LOAD STEP @
1000A/µs, 2-PHASE CCM
FIGURE 15. LOAD DUMP RESPONSE AT THE CPU SOCKET
MPGA479, 35A LOAD STEP @ 1000A/µs,
2-PHASE CCM
VID3
VID3
VOUT
VOUT
PHASE1
PHASE1
PHASE2
PHASE2
FIGURE 16. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
FIGURE 17. VID3 CHANGE OF 010X000 FROM 1.1V TO 1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
PSI#
PSI#
VOUT
VOUT
PHASE1
PHASE2
FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH
DPRSLPVR = 0, DPRSTP# = 1
FN6398 Rev 4.00
August 25, 2015
PHASE1
PHASE2
FIGURE 19. 1-CCM TO 2-CCM UPON PSI# DEASSERTION
WITH DPRSLPVR = 0, DPRSTP# = 1
Page 12 of 31
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
DPRSLPVR
DPRSLPVR/PSI
VOUT
VOUT
PHASE1
PHASE2
FIGURE 20. C4 ENTRY WITH VID CHANGE 0011X00 FROM
1.2V TO 1.15V, ILOAD = 2A, TRANSITION OF
2-CCM TO 1-DCM, PSI# TOGGLE FROM 1 TO 0
WITH DPRSLPVR FROM 0 TO 1
PHASE1
PHASE2
FIGURE 21. VID3 CHANGE OF 010X000 FROM 1V TO 1.1V
WITH DPRSLPVR = 0, DPRSTP# = 1, PSI# = 1
VOUT
DPRSLPVR
VOUT
IMVP-6_PWRGD
PHASE1
PHASE2
IOUT
FIGURE 22. C4 ENTRY WITH VID CHANGE OF 011X011 FROM
0.8625V TO 0.7625V, ILOAD = 3A, 1-CCM TO
1-DCM
FIGURE 23. OVERCURRENT PROTECTION
VID3
IMVP-6_PWRGD
VOUT
VOUT
PMON UNFILTERED
PHASE1
FIGURE 24. 1.7V OVERVOLTAGE PROTECTION SHOWS
OUTPUT VOLTAGE PULLED TO 0.9V AND PWM
TRI-STATE
FN6398 Rev 4.00
August 25, 2015
PMON FILTERED
FIGURE 25. VID TRANSITION FROM 1V TO 1.10V ILOAD = 24A,
EXTERNAL FILTER 40k AND 100pF AT PMON
Page 13 of 31
ISL6266, ISL6266A
Typical Performance Curves
(Continued)
VOUT
VOUT
PMON UNFILTERED
PMON UNFILTERED
PMON FILTERED
PMON FILTERED
FIGURE 26. VID = 1.15V, LOAD TRANSIENT OF 0A TO 36A
WITH INTEL VTT TOOL, 1kHz RATE, 50% DUTY
CYCLE, TR = 35
FIGURE 27. VID = 1.15V, LOAD APPLICATION FROM
0A TO 36A WITH INTEL VTT TOOL, 1kHz RATE,
50% DUTY CYCLE, TR = 35
VOUT
PMON UNFILTERED
PMON FILTERED
FIGURE 28. VID = 1.15V, LOAD RELEASE FROM 36A TO 0A WITH INTEL VTT TOOL, 1kHz RATE, 50% DUTY CYCLE, TR = 35
1.8
0.8
1.6
19V, 1.15V, 40A
0.6
1.2
1.0
19V, 1.15V, 30A
19V, 1.15V, 20A
PMON (V)
PMON (V)
1.4
0.8
19V, 1.15V, 10A
0.6
19V, 1.15V, 5A
0.5
0.2
0.1
1
2
3
4
5
CURRENT SOURCING (mA)
6
7
FIGURE 29. POWER MONITOR CURRENT SOURCING
CAPABILITY
FN6398 Rev 4.00
August 25, 2015
180
0.3
0.2
0
VID = 1.15V, IOUT = 10A
0.4
0.4
0.0
VID = 1.15V, IOUT = 15A
0.7
7
0.0
0.0
VID = 1.15V, IOUT = 5A
VID = 1.15V, IOUT = 2.5A
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
CURRENT SINKING (mA)
FIGURE 30. POWER MONITOR CURRENT SINKING
CAPABILITY
Page 14 of 31
ISL6266, ISL6266A
Simplified Coupled Inductor Application Circuit for DCR Current Sensing
+5V
R12
+3.3V
VIN
3V3
VDD PVCC VIN
VIN
RBIAS
NTC
R13
VR_TT#
C8
VID
ISL6266
C7
VR_TT#
UGATE1
BOOT1
SOFT
C6
VIDs
PHASE1
R8
DPRSTP#
DPRSTP#
VSUM
LGATE1
DPRSLPVR
DPRSLPVR
PSI#
PGND1
PSI#
ISEN1
ISEN1
PMON
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
IMVP-6_PWRGD
PGOOD
RL
VIN
CL VO'
C8
R10
VSEN
REMOTE
SENSE
RTN
R2
R3
PHASE2
C3
R1
LO
BOOT2
VDIFF
R7
C1
VO
UGATE2
CO
C5
R11
RL
LGATE2
FB2
FB
VO'
R9
PGND2
CL
VSUM
COMP
ISEN2
C2
RFSET
ISEN2
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 31. ISL6266 BASED TWO-PHASE COUPLED INDUCTOR DESIGN WITH DCR SENSING
FN6398 Rev 4.00
August 25, 2015
Page 15 of 31
ISL6266, ISL6266A
Simplified Application Circuit for DCR Current Sensing
+5V
VIN
+3.3V
R12
3V3
VDD PVCC VIN
VIN
RBIAS
NTC
R13
VR_TT#
C8
VID
ISL6266A
C7
VR_TT#
UGATE1
BOOT1
SOFT
LO
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
CL
RL
LGATE1
DPRSLPVR
ISEN1
DPRSLPVR
PSI#
VO'
R8
PGND2
PSI#
VO
VSUM
ISEN1
PMON
CO
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
IMVP-6_PWRGD
PGOOD
VIN
C8
VSEN
REMOTE
SENSE
UGATE2
RTN
R2
VDIFF
R3
C1
PHASE2
C3
R7
R1
LO
BOOT2
C5
R11
RL
LGATE2
FB2
FB
R9
PGND2
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 32. ISL6266A BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
FN6398 Rev 4.00
August 25, 2015
Page 16 of 31
ISL6266, ISL6266A
Simplified Application Circuit for Resistive Current Sensing
+5V
VIN
+3.3V
R11
3V3
VDD PVCC VIN
VIN
RBIAS
ISL6266A
NTC
R12
VR_TT#
C9
VID
C7
VR_TT#
UGATE1
BOOT1
SOFT
L
RS
C6
VIDs
PHASE1
R10
DPRSTP#
DPRSTP#
CL
RL
LGATE1
DPRSLPVR
ISEN2
DPRSLPVR
PSI#
VO'
R8
PGND2
PSI#
VO
VSUM
ISEN1
PMON
CO
CLK_ENABLE#
CLK_EN#
VR_ON
VR_ON
IMVP-6_PWRGD
PGOOD
VIN
C8
VSEN
REMOTE
SENSE
UGATE2
RTN
R2
VDIFF
R3
C1
PHASE2
C3
R7
L
BOOT2
RS
C5
R11
RL
LGATE2
FB2
FB
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
CHF
C4
VO'
FIGURE 33. ISL6266A BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
FN6398 Rev 4.00
August 25, 2015
Page 17 of 31
ISL6266, ISL6266A
Theory of Operation
VDD
The ISL6266A is a two-phase regulator implementing Intel®
IMVP-6 protocol and includes embedded gate drivers for
reduced system cost and board area. The regulator provides
optimum steady-state and transient performance for
microprocessor core applications up to 50A. System efficiency
is enhanced by idling one phase at low-current and
implementing automatic DCM-mode operation.
The heart of the ISL6266A is R3 Technology™, Intersil’s
Robust Ripple Regulator modulator. The R3 modulator
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their shortcomings.
The ISL6266A modulator internally synthesizes an analog of
the inductor ripple current and uses hysteretic comparators on
those signals to establish PWM pulse widths. Operating on
these large-amplitude, noise-free synthesized signals allows
the ISL6266A to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6266A has an error amplifier that allows the controller to
maintain a 0.5% voltage regulation accuracy throughout the
VID range from 0.75V to 1.5V.
The hysteresis window voltage is relative to the error amplifier
output such that load current transients results in increased
switching frequency, which gives the R3 regulator a faster
response than conventional fixed frequency PWM controllers.
Transient load current is inherently shared between active
phases due to the use of a common hysteretic window voltage.
Individual average phase voltages are monitored and
controlled to equally share the static current among the active
phases.
10mV/µs
VR_ON
2.8mV/µs
100µs
VBOOT
SOFT AND VO
VID COMMANDED
VOLTAGE
90%
13 SWITCHING CYCLES
CLK_EN#
~7ms
IMVP-6 PGOOD
FIGURE 34. SOFT-START WAVEFORMS USING A 15nF SOFT
CAPACITOR
Static Operation
After the start sequence, the output voltage will be regulated to
the value set by the VID inputs shown in Table 1. The entire
VID table is presented in the intel IMVP-6 specification. The
ISL6266A will control the no-load output voltage to an accuracy
of ±0.5% over the range of 0.75V to 1.5V.
TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6+
SPECIFICATION
VOUT
(V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0
0
0
0
0
0
0
1.5000
0
0
0
0
0
0
1
1.4875
0
0
0
0
1
0
1
1.4375
0
0
1
0
0
0
1
1.2875
Start-Up Timing
0
0
1
1
1
0
0
1.15
With the controller's VDD voltage above the POR threshold,
the start-up sequence begins when VR_ON exceeds the 3.3V
logic HIGH threshold. Approximately 100µs later, SOFT and
VOUT begin ramping to the boot voltage of 1.2V. At start-up,
the regulator always operates in a 2-phase CCM mode
regardless of control signal assertion levels. During this
interval, the SOFT capacitor is charged by 41µA current
source. If the SOFT capacitor is selected to be 20nF, the SOFT
ramp will be at 2mV/µs for a soft-start time of 600µs. Once
VOUT is within 10% of the boot voltage for 13 PWM cycles
(43µs for frequency = 300kHz), then CLK_EN# is pulled LOW
and the SOFT capacitor is charged/discharged by
approximately 200µA. Therefore, VOUT slews at 10mV/µs to
the voltage set by the VID pins. Approximately 7ms later,
PGOOD is asserted HIGH. Typical start-up timing is shown in
Figure 34.
0
1
1
0
1
0
1
0.8375
0
1
1
1
0
1
1
0.7625
1
1
0
0
0
0
0
0.3000
1
1
1
1
1
1
1
0.0000
FN6398 Rev 4.00
August 25, 2015
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the microprocessor die. The
inputs to the amplifier are the VSEN and RTN pins.
As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to
current to achieve the IMVP-6+ load line. The ISL6266A
provides options for current to be measured using either
resistors in series with the channel inductors as shown in the
application circuit of Figure 33, or using the intrinsic series
resistance of the inductors as shown in the application circuit of
Figure 32. In both cases, signals representing the inductor
currents are summed at VSUM, which is the non-inverting
input to the DROOP amplifier shown in the block diagram of
Figure 1. The voltage at the DROOP pin minus the output
voltage, VO´, is a high-bandwidth analog of the total inductor
Page 18 of 31
ISL6266, ISL6266A
current. This voltage is used as an input to a differential
amplifier to achieve the IMVP-6+ load line, and also as the
input to the overcurrent protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding thus maintaining the load-line
accuracy.
In addition to monitoring the total current (used for DROOP
and overcurrent protection), the individual channel average
currents are also monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to cause
the voltages presented at the ISEN pins to be equal.
The ISL6266A controller can be configured for two-channel
operation, with the channels operating 180° apart. The channel
PWM frequency is determined by the value of RFSET
connected to pin VW as shown in Figures 32 and 33. Input and
output ripple frequencies will be the channel PWM frequency
multiplied by the number of active channels.
High Efficiency Operation Mode
The ISL6266A has several operating modes to optimize
efficiency. The controller's operational modes are designed to
work in conjunction with the Intel IMVP-6+ control signals to
maintain the optimal system configuration for all IMVP-6+
conditions. These operating modes are established by the
IMVP-6+ control signal inputs PSI#, DPRSLPVR, and
DPRSTP# as shown in Table 2. At high current levels, the
system will operate with both phases fully active, responding
rapidly to transients and delivering maximum power to the
load. At reduced load-current levels, one of the phases may be
idled. This configuration will minimize switching losses, while
still maintaining transient response capability. At the lowest
current levels, the controller automatically configures the
system to operate in single-phase automatic-DCM mode, thus
achieving the highest possible efficiency. In this mode of
operation, the lower MOSFET will be configured to
automatically detect and prevent discharge current flowing
from the output capacitor through the inductors, and the
switching frequency will be proportionately reduced, thus
greatly reducing both conduction and switching losses.
Smooth mode transitions are facilitated by the R3
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms that maintain
voltage-regulation for all control signal input sequences and
durations.
While the ISL6266A will respond according to the logic states
shown in Table 2, it can deviate from the commanded state
during sleep state exit. If the core voltage is directed by the
CPU to make a VID change that causes excessive output
capacitor inrush current when going from 1-phase DCM to 1phase CCM, the controller will automatically add Phase 2 until
the VID transition is complete. This is beneficial for designs
that have very large COUT values.
The controller contains internal counters that prevent spurious
control signal glitches from resulting in unwanted mode
transitions. Control signals of less than two switching periods
do not result in phase-idling.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6266 AND ISL6266A
DPRSLPVR
DPRSTP#
PSI#
0
0
0
0
0
0
ISL6266
ISL6266A
VID SLEW RATE
CPU MODE
1-phase CCM
1-phase diode emulation
fast
awake
1
2-phase CCM
2-phase CCM
fast
awake
1
0
1-phase CCM
1-phase diode emulation
fast
awake
0
1
1
2-phase CCM
2-phase CCM
fast
awake
1
0
0
1-phase diode emulation
1-phase diode emulation
slow (Note 5)
sleep
1
0
1
1-phase diode emulation
1-phase diode emulation
slow (Note 5)
sleep
1
1
0
1-phase CCM
1-phase diode emulation
slow
awake
1
1
1
2-phase CCM
2-phase CCM
slow
awake
NOTE:
5. The negative VID slew rate when DPRSTP# = 0 and DPRSLPVR = 1 is limited to no faster than the slow slew rate. However, slower slew rates
can be seen. To conserve power, the ISL6266A will tri-state UGATE and LGATE and let the load gradually pull the core voltage back into
regulation.
FN6398 Rev 4.00
August 25, 2015
Page 19 of 31
ISL6266, ISL6266A
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the activephase, and detects the idling-phase zero-current condition.
During transitions into automatic-DCM or forced-CCM mode, the
timing is carefully adjusted to eliminate output voltage excursions.
When a phase is added, the current balance between phases is
quickly restored.
When commanded into 1-phase CCM operation according to
Table 2, both MOSFETs of Phase 2 will be off. The controller
will thus eliminate switching losses associated with the
unneeded channel.
VOUT AND VSOFT
Dynamic Operation
Figure 35 shows that the ISL6266A responds to changes in
VID command voltage by slewing to new voltages with a dV/dt
set by the SOFT capacitor and by the state of DPRSLPVR.
With CSOFT = 15nF and DPRSLPVR HIGH, the output voltage
will move at ±2.8mV/µs for large changes in voltage. For
DPRSLPVR LOW, the large signal dV/dt will be ±10mV/µs. As
the output voltage approaches the VID command value, the
dV/dt moderates to prevent overshoot.
10mV/µs
-2.5mV/µs
The ISL6266A can be configured to operate as a single phase
regulator using the same layout as a two phase design to
accommodate lower power CPUs. To accomplish this, the
designer must connect ISEN1 and ISEN2 to VCC_PRM
(reference AN1376 for signal names). Channel 2 components
can be removed as well as current balance circuitry. The
ISL6266A will power-up and regulate in DCM or CCM based
on the state of PSI#, as outlined in Table 2. The OCP threshold
will also change based on the state of PSI#, as outlined in
“Protection” on page 20.
2.5mV/µs
DPRSLPVR
Keeping DPRSLPVR HIGH for voltage transitions into and out
of Deeper Sleep will result in low dV/dt output voltage changes
with resulting minimized audio noise. For fastest recovery from
Deeper Sleep to Active mode, holding DPRSLPVR LOW
results in maximum dV/dt. Therefore, the ISL6266A is IMVP-6+
compliant for DPRSTP# and DPRSLPVR logic.
VID#
FIGURE 35. DEEPER SLEEP TRANSITION SHOWING
DPRSLPVR'S EFFECT ON EXIT SLEW RATE
When commanded to single-phase DCM mode, both
MOSFETs associated with Phase 2 are off, and the ISL6266A
turns off the lower MOSFET of Channel 1 whenever the
Channel 1 current decays to zero. As load is further reduced,
the Phase 1 channel switching frequency decreases to
maintain high efficiency. The operation of the inactive for 1phase DCM and 1-phase CCM described previously refers to
the ISL6266A only. See “ISL6266 Features” on page 21 for
information on the ISL6266.
Intersil's R3 Technology™ has intrinsic voltage feedforward. As
a result, high-speed input voltage steps do not result in
significant output voltage perturbations. In response to load
current step increases, the ISL6266A will transiently raise the
switching frequency so that response time is decreased and
current is shared by two channels.
Protection
The ISL6266A provides overcurrent, overvoltage, undervoltage
protection and over-temperature protection, as shown in Table
3.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6266, ISL6266A
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM1, PWM2 three-state, PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurrent fault
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