DATASHEET
ISL6277A
FN8322
Rev.3.00
Oct 9, 2019
Multiphase PWM Regulator for AMD Fusion Mobile CPUs Using SVI 2.0
The ISL6277A is fully compliant with AMD Fusion SVI 2.0 and
provides a complete solution for microprocessor and graphics
processor core power. The ISL6277A controller supports two
Voltage Regulators (VRs) with three integrated gate drivers and
two optional external drivers for maximum flexibility. The Core
VR can be configured for 3-, 2-, or 1-phase operation while the
Northbridge VR supports 2- or 1-phase configurations. The two
VRs share a serial control bus to communicate with the AMD
CPU and achieve lower cost and smaller board area compared
with two-chip solutions.
The PWM modulator is based on the Renesas Robust Ripple
Regulator R3™ Technology. Compared to traditional
modulators, the R3 modulator can automatically change
switching frequency for faster transient settling time during
load transients and improved light load efficiency.
The ISL6277A has several other key features. Both outputs
support DCR current sensing with single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs utilize remote voltage sense, adjustable
switching frequency, OC protection and power-good.
Applications
Features
• Supports AMD SVI 2.0 serial data bus interface
- Serial VID clock frequency range 100kHz to 25MHz
• Dual output controller with integrated drivers
- Two dedicated core drivers
- One programmable driver for either Core or Northbridge
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0.5V to 1.55V in 6.25mV steps
- Enhanced load line accuracy
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1-, 2- or 3-phase for the core output and 1- or
2-phase for the Northbridge output
• Adaptive body diode conduction time reduction
• Superior noise immunity and transient response
• Output current and voltage telemetry
• AMD fusion CPU/GPU core power
• Differential remote voltage sensing
• Notebook computers
• High efficiency across entire load range
Related Literature
• Programmable slew rate
• Programmable VID offset and droop on both outputs
For a full list of related documents, visit our website:
• Programmable switching frequency for both outputs
• ISL6277A device page
• Excellent dynamic current balance between phases
• Protection: OCP/WOC, OVP, PGOOD and thermal monitor
• Small footprint 48 Ld 6x6 QFN package
- Pb-free (RoHS compliant)
Core Performance
100
1.12
90
1.10
VIN = 8V
70
1.08
VIN = 12V
60
VOUT (A)
EFFICIENCY (%)
80
VIN = 19V
50
40
30
VIN = 8V
1.04
VIN = 12V
1.02
1.00
20
10
0
0
1.06
5
10
15
20
25 30 35
IOUT (A)
40
FIGURE 1. EFFICIENCY vs LOAD
FN8322 Rev.3.00
Oct 9, 2019
45
50
VIN = 19V
0.98
VOUT CORE = 1.1V
55
0.96
VOUT CORE = 1.1V
0
5
10
15 20
25 30 35
IOUT (A)
40
45
50 55
FIGURE 2. VOUT vs LOAD
Page 1 of 40
ISL6277A
Table of Contents
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Application Circuit for High Power CPU Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Application Circuit with 3 Internal Drivers Used for Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Application Circuit for Mid-Power CPUs [2+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Application Circuit for Low Power CPUs [1+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
5
6
7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiphase R3 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
16
16
17
17
18
18
20
21
21
21
Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating DriverX and PWM_Y Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VID-on-the-Fly Slew Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
22
AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pre-PWROK Metal VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SVI Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Offset Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
23
24
26
26
26
27
Telemetry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitor [NTC, NTC_NB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
27
28
28
28
29
29
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
31
31
32
32
FN8322 Rev.3.00
Oct 9, 2019
Page 2 of 40
ISL6277A
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optional FCCM_NB Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
34
34
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FN8322 Rev.3.00
Oct 9, 2019
Page 3 of 40
ISL6277A
Typical Applications
ISEN1_NB
NB_PH2
ISEN2_NB
UGATEX
LGATEX
ISUMN_NB
Cn
VNB2
VIN
BOOTX
PHASEX
Ri
VNB1
VDDP
VDD
VIN
NB_PH1
ENABLE
Simplified Application Circuit for High Power CPU Core
NTC
NB_PH1
VNB1
VNB
FCCM_NB
ISUMP_NB
VIN
PWM2_NB
ISL6208
NB_PH1
NB_PH2
NB_PH2
COMP_NB
VNB2
IMON_NB
FB_NB
*
*OPTIONAL
NTC_NB
VR_HOT_L
VSEN_NB
VNB_SENSE
IMON
PWROK
NTC
SVT
µP
VIN
SVD
SVC
VDDIO
COMP
PWM_Y
*
BOOT2
FB
*OPTIONAL
PH3
ISL6277A
FB2
*
THERMAL INDICATOR
ISL6208
*
VIN
UGATE2
VSEN
VCORE
PHASE2
VCORE_SENSE
RTN
LGATE2
PH1
ISEN1
PH2
ISEN2
PH3
ISEN3
BOOT1
VO2
VIN
PGOOD
PHASE1
LGATE1
PH1
VO1
PH3
PH1
PH2
ISUMP
PGOOD_NB
VO3
NTC
GND PAD
ISUMN
Cn
PH2
UGATE1
Ri
VO1
VO2
VO3
FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
FN8322 Rev.3.00
Oct 9, 2019
Page 4 of 40
ISL6277A
Simplified Application Circuit with 3 Internal Drivers Used for Core
NB_PH1
ISEN1_NB
NB_PH2
ISEN2_NB
Ri
VNB1
VNB2
Cn
PWM_Y
ISL6208
VDDP
ENABLE
VIN
VDD
VIN
VNB
NB_PH1
ISUMN_NB
VNB1
FCCM_NB
NTC
VIN
PWM2_NB
ISL6208
ISUMP_NB
NB_PH1
NB_PH2
NB_PH2
VNB2
COMP_NB
IMON_NB
*
FB_NB
*
*OPTIONAL
NTC_NB
VR_HOT_L
VSEN_NB
VNB_SENSE
THERMAL INDICATOR
IMON
PWROK
NTC
SVT
µP
SVD
BOOTX
SVC
VIN
UGATEX
VDDIO
PHASEX
LGATEX
COMP
PH3
V03
ISL6277A
*
FB2
FB
*
BOOT2
*OPTIONAL
VIN
VSEN
UGATE2
VCORE_SENSE
RTN
VCORE
PHASE2
PH1
ISEN1
PH2
ISEN2
PH3
ISEN3
LGATE2
BOOT1
Ri
VO1
ISUMN
NTC
VIN
PHASE1
LGATE1
PH1
VO1
PH3
PH1
PH2
ISUMP
PGOOD
VO3
VO2
UGATE1
PGOOD_NB
Cn
GND PAD
VO2
PH2
FIGURE 4. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
FN8322 Rev.3.00
Oct 9, 2019
Page 5 of 40
ISL6277A
Simplified Application Circuit for Mid-Power CPUs [2+1 Configuration]
PWM_Y
ISEN1_NB
+5V
VNB
ISL6208
10kΩ*
VDDP
ENABLE
VIN
* Resistor required or ISEN1_NB
will pull HIGH if left open and
disable Channel 1.
VDD
VIN
ISEN2_NB
Ri
NBN
ISUMN_NB
NBP
NBN
VP2
VN2
FCCM_NB
NTC
Cn
ISUMP_NB
NBP
PWM2_NB
OPEN
IMON_NB
COMP_NB
NTC_NB
*
FB_NB
*
*OPTIONAL
VSEN_NB
VNB_SENSE
PWROK
SVT
µP
BOOTX
OPEN
UGATEX
OPEN
PHASEX
OPEN
LGATEX
OPEN
SVD
SVC
VR_HOT_L
THERMAL INDICATOR
VDDIO
IMON
COMP
ISL6277A
FB2
*
*
NTC
BOOT2
FB
VIN
UGATE2
*OPTIONAL
VSEN
PHASE2
VCORE_SENSE
RTN
LGATE2
VP1
ISEN1
VP2
ISEN2
+5V
VCORE
BOOT1
ISEN3
UGATE1
NTC
LGATE1
VP1
VN1
VP1
VP2
ISUMP
PHASE1
PGOOD
Cn
GND PAD
VN2
ISUMN
PGOOD_NB
Ri
VN1
VIN
FIGURE 5. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
FN8322 Rev.3.00
Oct 9, 2019
Page 6 of 40
ISL6277A
10kΩ*
VDDP
ENABLE
VIN
* Resistor required or ISEN1_NB
will pull HIGH if left open and
disable Channel 1.
VDD
Simplified Application Circuit for Low Power CPUs [1+1 Configuration]
ISEN1_NB
UGATEX
ISEN2_NB
+5V
Ri
VNB1
VNB
PHASEX
ISUMN_NB
LGATEX
NTC
Cn
VIN
BOOTX
NB_PH1
VNB1
ISUMP_NB
NB_PH1
FCCM_NB
PWM2_NB
OPEN
COMP_NB
*
*
IMON_NB
FB_NB
*OPTIONAL
NTC_NB
VSEN_NB
VNB_SENSE
VR_HOT
NTC
PWROK
SVT
µP
THERMAL INDICATOR
IMON
SVD
SVC
VDDIO
* Resistor required or ISEN1
will pull HIGH if left open and
disable Channel 1.
10kΩ*
ISEN1
+5V
ISEN2
+5V
ISEN3
ISL6277A
PWM_Y
OPEN
BOOT2
OPEN
UGATE2
OPEN
PHASE2
OPEN
LGATE2
OPEN
COMP
OPEN
*
*
FB2
BOOT1
VIN
FB
UGATE1
*OPTIONAL
VSEN
VCORE_SENSE
VCORE
PHASE1
RTN
LGATE1
PH1
VO1
Cn
PH1
ISUMP
GND PAD
ISUMN
NTC
PGOOD
VO1
PGOOD_NB
Ri
FIGURE 6. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
FN8322 Rev.3.00
Oct 9, 2019
Page 7 of 40
ISL6277A
Block Diagram
VSEN
CORE_I
COMP_NB
NB_I
+
RTN
IMON_NB
+
+
_
FB_NB
E/A
+
ISUMN_NB
_
PWM2_NB
VR2
MODULATOR
IDROOP_NB
ISUMP_NB
IMON
CURRENT
A/D
CURRENT
SENSE
VDD
PGOOD_NB
OC FAULT
ISEN1_NB
CURRENT
BALANCING
ISEN2_NB
IBAL FAULT
OV FAULT
NB_V
NTC_NB
T_MONITOR
TEMP
MONITOR
NTC
VOLTAGE
A/D
FLOATING
DRIVER &
PWM
CONFIG
LOGIC
VR_HOT_L
OFFSET
FREQ
SLEWRATE
CONFIG
BOOTX
DRIVER
UGATEX
PHASEX
PROG
DRIVER
LGATEX
IDROOP_NB
ENABLE
A/D
IDROOP
D/A
DAC2
DAC1
PWROK
DIGITAL
INTERFACE
SVC
PWM_Y
VCCP
CORE_I
SVD
BOOT2
NB_I
TELEMETRY
SVT
CORE_V
NB_V
DRIVER
VDDIO
UGATE2
PHASE2
COMP
VSEN
+
RTN
FB
ISUMN
_
E/A
DRIVER
LGATE2
BOOT1
IDROOP
FB2
+
VR1
MODULATOR
+
_
FB2
CIRCUIT
ISUMP
+
CURRENT
SENSE
DRIVER
VOLTAGE
A/D
UGATE1
PHASE1
CORE_V
ISEN3
ISEN2
DRIVER
CURRENT
BALANCING
OC FAULT
ISEN1
LGATE1
PGOOD
IBAL FAULT
OV FAULT
GND
FIGURE 7. BLOCK DIAGRAM
FN8322 Rev.3.00
Oct 9, 2019
Page 8 of 40
ISL6277A
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
TAPE AND REEL
(Units) (Note 1)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6277AHRZ
6277A HRZ
-10 to +100
-
48 Ld 6x6 QFN
L48.6x6B
ISL6277AHRZ-T
6277A HRZ
-10 to +100
4k
48 Ld 6x6 QFN
L48.6x6B
ISL6277AIRZ
6277A IRZ
-40 to +100
-
48 Ld 6x6 QFN
L48.6x6B
ISL6277AIRZ-T
6277A IRZ
-40 to +100
4k
48 Ld 6x6 QFN
L48.6x6B
NOTES:
1. See TB347 for details about reel specifications.
2. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL6277A device page. For more information about MSL, see TB363.
Pin Configuration
UGATEX
LGATEX
PHASEX
PWM2_NB
FCCM_NB
PGOOD_NB
COMP_NB
VSEN_NB
FB_NB
ISUMP_NB
ISUMN_NB
ISEN1_NB
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
ISEN2_NB
1
36 BOOTX
NTC_NB
2
35 VIN
IMON_NB
3
34 BOOT2
SVC
4
33 UGATE2
VR_HOT_L
5
SVD
6
GND PAD
31 LGATE2
VDDIO
7
(BOTTOM)
30 VDDP
SVT
8
29 VDD
ENABLE
9
28 PWM_Y
PWROK 10
27 LGATE1
IMON 11
26 PHASE1
NTC 12
25 UGATE1
BOOT1 24
RTN 19
FB2 20
FB 21
COMP 22
PGOOD 23
ISUMP 16
ISUMN 17
VSEN 18
ISEN1 15
ISEN2 14
37
ISEN3 13
32 PHASE2
Pin Descriptions
PIN NUMBER
SYMBOL
1
ISEN2_NB
2
NTC_NB
3
IMON_NB
4
SVC
5
VR_HOT_L
6
SVD
7
VDDIO
FN8322 Rev.3.00
Oct 9, 2019
DESCRIPTION
Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2_NB is pulled to +5V, the
controller will disable Channel 2 and the Northbridge VR will run single-phase.
Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature.
Northbridge output current monitor. A current proportional to the Northbridge VR output current is
sourced from this pin.
Serial VID clock input from the CPU processor master device.
Thermal indicator signal to AMD CPU. Thermal overload open-drain output indicator active LOW.
Serial VID data bidirectional signal from the CPU processor master device to the VR.
VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller
IC for this processor I/O signal level.
Page 9 of 40
ISL6277A
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
8
SVT
Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly
complete signal provided from this pin.
9
ENABLE
Enable input. A high level logic on this pin enables both VRs.
10
PWROK
System power-good input. When this pin is high, the SVI 2 interface is active and the I2C protocol is
running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This
pin must be low prior to the ISL6277A PGOOD output going high per the AMD SVI 2.0 Controller
Guidelines.
11
IMON
12
NTC
13
ISEN3
ISEN3 is the individual current sensing for Channel 3. When ISEN3 is pulled to +5V, the controller disables
Channel 3, and the Core VR runs in two-phase mode.
14
ISEN2
Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller
disables Channel 2, and the Core VR runs in single-phase mode.
15
ISEN1
Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left
open and must be tied to GND with a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is
shut down.
16
ISUMP
Noninverting input of the transconductance amplifier for current monitor and load line of Core output.
17
ISUMN
Inverting input of the transconductance amplifier for current monitor and load line of Core output.
18
VSEN
Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.
19
RTN
Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the
microprocessor die.
20
FB2
There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase or 3-phase mode and
is off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in
1-phase mode of the Core VR to achieve optimum performance.
21
FB
Output voltage feedback to the inverting input of the Core controller error amplifier.
22
COMP
Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage.
23
PGOOD
Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull-up
externally to VDD or 3.3V through a resistor.
24
BOOT1
Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged,
through an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1
pin drops below VDDP minus the voltage dropped across the internal boot diode.
25
UGATE1
Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate
of the Phase 1 high-side MOSFET(s).
26
PHASE1
Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PHASE1 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of
Phase 1.
27
LGATE1
Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate
of the Phase 1 low-side MOSFET(s).
28
PWM_Y
Floating PWM output used for either Channel 3 of the Core VR or Channel 1 of the Northbridge VR
depending on the FCCM_NB resistor connected between FCCM_NB and GND.
29
VDD
30
VDDP
Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF
of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.
31
LGATE2
Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate
of the Phase 2 low-side MOSFET(s).
FN8322 Rev.3.00
Oct 9, 2019
Core output current monitor. A current proportional to the Core VR output current is sourced from this pin.
Thermistor input to VR_HOT_L circuit to monitor Core VR temperature.
5V bias power. A resistor [2Ω] and a decoupling capacitor should be used from the +5V supply. A high
quality, X7R dielectric MLCC capacitor is recommended.
Page 10 of 40
ISL6277A
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
32
PHASE2
Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2
pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of Phase 2.
33
UGATE2
Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate
of the Phase 2 high-side MOSFET(s).
34
BOOT2
Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through
an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops
below VDDP minus the voltage dropped across the internal boot diode.
35
VIN
36
BOOTX
Boot connection of the programmable internal driver used for either Channel 3 of the Core VR or
Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Connect an MLCC capacitor across the BOOT1X and the PHASEX pins. The boot capacitor is charged,
through an internal boot diode connected from the VDDP pin to the BOOTX pin, each time the PHASEX
pin drops below VDDP minus the voltage dropped across the internal boot diode.
37
UGATEX
High-side MOSFET gate driver portion of the programmable internal driver used for either Channel 3 of
the Core VR or Channel 1 of the Northbridge VR based on the configuration state selected by the
FCCM_NB resistor. Connect the UGATEX pin to the gate of the high-side MOSFET(s) for either Phase 3 of
the Core VR or Phase 1 of the Northbridge VR based on the configuration state selected.
38
PHASEX
Phase connection of the programmable internal driver used for either Channel 3 of the Core VR or
Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Current return path for the high-side MOSFET gate driver of the floating internal driver. Connect the
PHASEX pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the
output inductor of either Phase 3 of the Core VR or Phase 1 of the Northbridge VR based on the
configuration state selected.
39
LGATEX
Low-side MOSFET gate driver portion of floating internal driver used for either Channel 3 of the Core VR
or Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.
Connect the LGATEX pin to the gate of the low-side MOSFET(s) for either Phase 3 of the Core VR or
Phase 1 of the Northbridge VR based on the configuration state selected.
40
PWM2_NB
PWM output for Channel 2 of the Northbridge VR. Disabled when ISEN2_NB is tied to +5V.
41
FCCM_NB
Diode emulation control signal for Renesas MOSFET drivers. When FCCM_NB is LOW, diode emulation at
the driver this pin connects to is allowed. A resistor from FCCM_NB pin to GND configures the PWM_Y
and floating internal gate driver [BOOTX, UGATEX, PHASEX, LGATEX pins] to support Phase 3 of the Core
VR and Phase 1 of the Northbridge VR. The FCCM_NB resistor value also is used to set the slew rate for
the Core VR and Northbridge VR. A capacitor place holder from the FCCM_NB pin to GND is
recommended for filtering noise on this pin due to layout.
42
PGOOD_NB
Open-drain output to indicate the Northbridge portion of the IC is ready to supply regulated voltage.
Pull-up externally to VDDP or 3.3V through a resistor.
43
COMP_NB
Northbridge VR error amplifier output. A resistor from COMP_NB to GND sets the Northbridge VR offset
voltage and is used to set the switching frequency for the Core VR and Northbridge VR.
44
FB_NB
45
VSEN_NB
Output voltage sense pin for the Northbridge controller. Connect to the +sense pin of the microprocessor
die.
46
ISUMN_NB
Inverting input of the transconductance amplifier for current monitor and load line of the Northbridge VR.
47
ISUMP_NB
Noninverting input of the transconductance amplifier for current monitor and load line of the Northbridge
VR.
48
ISEN1_NB
Individual current sensing for Channel 1 of the Northbridge VR. If ISEN2_NB is tied to +5V, this pin cannot
be left open and must be tied to GND with a 10kΩ resistor. If ISEN1_NB is tied to +5V, the Northbridge
portion of the IC is shutdown.
GND (Bottom Pad)
FN8322 Rev.3.00
Oct 9, 2019
Battery supply voltage, used for feed-forward.
Output voltage feedback to the inverting input of the Northbridge controller error amplifier.
Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.
Page 11 of 40
ISL6277A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
-0.3V to +9V (20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on a
different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed
on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two
preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
CURRENT-SENSING TRACES
18
VSEN
Place the filter on these pins in close proximity to the controller for good coupling.
19
RTN
20
FB2
21
FB
22
COMP
23
PGOOD
No special consideration.
24
BOOT1
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
25
UGATE1
26
PHASE1
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing these
signals near sensitive analog signal traces or crossing over them. Routing PHASE1 to the Core VR Channel 1 high-side
MOSFET source pin instead of a general connection to PHASE1 copper is recommended for better performance.
27
LGATE1
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
28
PWM_Y
No special considerations.
29
VDD
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close
proximity to the pin with the filter resistor nearby the IC.
30
VDDP
A high quality, X7R dielectric MLCC capacitor is recommended to decouple this pin to GND. Place the capacitor in close
proximity to the pin.
31
LGATE2
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
32
PHASE2
33
UGATE2
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing these
signals near sensitive analog signal traces or crossing over them. Routing PHASE2 to the Core VR Channel 2 high-side
MOSFET source pin instead of a general connection to PHASE2 copper is recommended for better performance.
34
BOOT2
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
35
VIN
36
BOOTX
Use a wide trace width (>30mil). Avoid routing any sensitive analog signal traces close to or crossing over this trace.
37
UGATEX
38
PHASEX
These two signals should be routed together in parallel. Each trace should have sufficient width (>30mil). Avoid routing these
signals near sensitive analog signal traces or crossing over them. Routing PHASEX to the high-side MOSFET source pin
instead of a general connection to the PHASEX copper is recommended for better performance.
39
LGATEX
Use sufficient trace width (>30mil). Avoid routing this signal near any sensitive analog signal traces or crossing over them.
Place the compensation components in general proximity of the controller.
Place the decoupling capacitor in close proximity to the pin with a short connection to the internal GND plane.
40
PWM2_NB No special considerations.
41
FCCM_NB
FN8322 Rev.3.00
Oct 9, 2019
Page 36 of 40
ISL6277A
TABLE 14. LAYOUT CONSIDERATIONS FOR THE ISL6277A CONTROLLER (Continued)
PIN NUMBER
SYMBOL
LAYOUT GUIDELINES
42
PGOOD_NB No special consideration.
43
COMP_NB Place the compensation components in general proximity of the controller.
44
FB_NB
45
VSEN_NB Place the filter on this pin in close proximity to the controller for good coupling.
46
ISUMN_NB Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
ISUMP_NB
Place the NTC thermistor next to Core VR Channel 1 inductor so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces in
parallel fashion with decent width (>20mil).
47
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces on a
different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed
on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two
preferred ways of routing current sensing traces.
INDUCTOR
INDUCTOR
VIAS
CURRENT-SENSING TRACES
48
CURRENT-SENSING TRACES
ISEN1_NB
FN8322 Rev.3.00
Oct 9, 2019
Page 37 of 40
ISL6277A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
Oct 9, 2019
FN8322.3
Updated links throughout document.
Added Related Literature section
Updated the ordering information table by adding tape and reel information and updating notes.
Updated the Overcurrent Protection section on page 30.
Removed About Intersil section.
Updated disclaimer.
Dec 4, 2015
FN8322.2
On page 1 under Features, changed "SVC Frequency Range 100kHz to 20MHz" to "Serial VID clock frequency
range 100kHz to 25MHz"
Mar 27, 2015
FN8322.1
On page 1 under Features, added "SVC Frequency Range 100kHz to 20MHz" below "Supports AMD SVI 2.0
serial data bus interface”.
On page 13 in the EC Table: “LOGIC THRESHOLDS” section, added “SVC Frequency Range” with limits of
0.1MHz to 20MHz.
Dec 19, 2012
FN8322.0
Initial Release
FN8322 Rev.3.00
Oct 9, 2019
CHANGE
Page 38 of 40
ISL6277A
For the most recent package outline drawing, see L48.6x6B.
Package Outline Drawing
L48.6x6B
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/09
4X 4.4
6.00
44X 0.40
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
37
1
6.00
36
4 .40 ± 0.15
25
12
0.15
(4X)
13
24
0.10 M C A B
0.05 M C
TOP VIEW
48X 0.45 ± 0.10
4 48X 0.20
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
BASE PLANE
MAX 1.00
(
SEATING PLANE
0.08 C
( 44 X 0 . 40 )
( 5. 75 TYP )
C
SIDE VIEW
4. 40 )
C
0 . 2 REF
5
( 48X 0 . 20 )
( 48X 0 . 65 )
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN8322 Rev.3.00
Oct 9, 2019
Page 39 of 40
1RWLFH
'HVFULSWLRQVRIFLUFXLWVVRIWZDUHDQGRWKHUUHODWHGLQIRUPDWLRQLQWKLVGRFXPHQWDUHSURYLGHGRQO\WRLOOXVWUDWHWKHRSHUDWLRQRIVHPLFRQGXFWRUSURGXFWV
DQGDSSOLFDWLRQH[DPSOHV
工商网监
湘ICP备2023018690号
