ISL6308ACRZR5609

DATASHEET ISL6308A Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers The ISL6308A is a three-phase PWM control IC with integrated MOSFET drivers. It provides a precision voltage regulation system for multiple applications including, but not limited to, high current low voltage point-of-load converters, embedded applications and other general purpose low voltage medium to high current applications.The integration of power MOSFET drivers into the controller IC marks a departure from the separate PWM controller and driver configuration of previous multi-phase product families. By reducing the number of external parts, this integration allows for a cost and space saving power management solution. FN6669 Rev 0.00 September 9, 2008 Features • Integrated Multi-Phase Power Conversion - 1-, 2-, or 3-Phase Operation • Precision Output Voltage Regulation - Differential Remote Voltage Sensing - ±0.8% System Accuracy Over-Temperature (for REF=0.6V and 0.9V) - ±0.5% System Accuracy Over-Temperature (for REF=1.2V and 1.5V) - Usable for Output Voltages not Exceeding 2.3V - Adjustable Reference-Voltage Offset Output voltage can be programmed using the on-chip DAC or an external precision reference. A two bit code programs the DAC reference to one of 4 possible values (0.6V, 0.9V,1.2V and 1.5V). A unity gain, differential amplifier is provided for remote voltage sensing, compensating for any potential difference between remote and local grounds. The output voltage can also be offset through the use of single external resistor. An optional droop function is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. • Precision Channel Current Sharing - Uses Loss-Less rDS(ON) Current Sampling • Optional Load Line (Droop) Programming - Uses Loss-Less Inductor DCR Current Sampling • Variable Gate-Drive Bias - 5V to 12V • Internal or External Reference Voltage Setting - On-Chip Adjustable Fixed DAC Reference Voltage with 2-bit Logic Input Selects from Four Fixed Reference Voltages (0.6V, 0.9V, 1.2V, 1.5V) - Reference can be Changed Dynamically - Can use an External Voltage Reference A unique feature of the ISL6308A is the combined use of both DCR and rDS(ON) current sensing. Load line voltage positioning and overcurrent protection are accomplished through continuous inductor DCR current sensing, while rDS(ON) current sensing is used for accurate channel-current balance. Using both methods of current sampling utilizes the best advantages of each technique. • Overcurrent Protection • Multi-tiered Overvoltage Protection - OVP Pin to Drive Optional Crowbar Device • Selectable Operation Frequency up to 1.5MHz per Phase Protection features of this controller IC include a set of sophisticated overvoltage and overcurrent protection. Overvoltage results in the converter turning the lower MOSFETs ON to clamp the rising output voltage and protect the load. An OVP output is also provided to drive an optional crowbar device. The overcurrent protection level is set through a single external resistor. Other protection features include protection against an open circuit on the remote sensing inputs. Combined, these features provide advanced protection for the output load. • Digital Soft-Start • Capable of Start-up in a Pre-Biased Load • Pb-Free (RoHS Compliant) Applications • High Current DDR/Chipset Core Voltage Regulators • High Current, Low Voltage DC/DC Converters • High Current, Low Voltage FPGA/ASIC DC/DC Converters Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL6308ACRZ* (Note) 6308A CRZ 0 to +70 40 Ld 6x6 QFN (Pb-free) L40.6x6 ISL6308AIRZ* (Note) 6308A IRZ -40 to +85 40 Ld 6x6 QFN (Pb-free) L40.6x6 ISL6308AEVAL1Z Evaluation Platform *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6669 Rev 0.00 September 9, 2008 Page 1 of 28 ISL6308A Pinout FN6669 Rev 0.00 September 9, 2008 REF0 REF1 OVP ENLL FS PGOOD LGATE1 PVCC1 ISEN1 UGATE1 ISL6308A (40 LD 6x6 QFN) TOP VIEW 40 39 38 37 36 35 34 33 32 31 3PH 1 30 BOOT1 2PH 2 29 PHASE1 DAC 3 28 PHASE2 REF 4 27 UGATE2 OFST 5 26 BOOT2 VCC 6 25 ISEN2 COMP 7 24 PVCC2 FB 8 23 LGATE2 VDIFF 9 22 PHASE3 RGND 10 21 BOOT3 11 12 13 14 15 16 17 18 19 20 VSEN OCSET ICOMP DROOP ISUM IREF LGATE3 PVCC3 ISEN3 UGATE3 41 GND Page 2 of 28 ISL6308A Block Diagram ICOMP DROOP OCSET ISEN AMP PGOOD OVP 100µA ENLL 0.66V ISUM POWER-ON OC IREF VCC RESET PVCC1 RGND VSEN BOOT1 +1V UGATE1 SOFT-START AND x1 x1 GATE CONTROL LOGIC FAULT LOGIC SHOOTTHROUGH PROTECTION PHASE1 VDIFF LGATE1 UVP 0.2V FS OVP PVCC2 CLOCK AND SAWTOOTH GENERATOR OVP BOOT2 UGATE2 PWM1  GATE CONTROL LOGIC +150mV x 0.82  SHOOTTHROUGH PROTECTION PHASE2 PWM2 LGATE2 REF1 DAC  REF0 PWM3 2PH CHANNEL DETECT 3PH DAC PVCC3 BOOT3 REF CHANNEL CURRENT BALANCE E/A FB 1 N COMP OFST  UGATE3 GATE CONTROL LOGIC SHOOTTHROUGH PROTECTION OFFSET PHASE3 LGATE3 CHANNEL CURRENT SENSE ISEN1 FN6669 Rev 0.00 September 9, 2008 ISEN2 ISEN3 GND Page 3 of 28 ISL6308A Typical Application - ISL6308A +12V VDIFF FB COMP PVCC1 BOOT1 VSEN +5V RGND UGATE1 3PH 2PH PHASE1 ISEN1 VCC LGATE1 OFST +12V FS PVCC2 BOOT2 DAC UGATE2 ISL6308A PHASE2 REF ISEN2 LOAD LGATE2 REF1 REF0 +12V +12V OVP PGOOD PVCC3 GND BOOT3 UGATE3 PHASE3 ENLL ISEN3 IREF DROOP OCSET FN6669 Rev 0.00 September 9, 2008 LGATE3 ICOMP ISUM Page 4 of 28 ISL6308A Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V Absolute Boot Voltage, VBOOT . . . . . . . . GND - 0.3V to GND + 36V Phase Voltage, VPHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12) GND - 8V ( --------------------------------2  C  ESR Case 3: 2  F 0  V OSC  L R 2 = R 1  ----------------------------------------------0.66  V IN  ESR 0.66  V IN  ESR  C C 2 = -------------------------------------------------------------2  V OSC  R 1  F 0  L C2 In Equations 28, L is the per-channel filter inductance divided by the number of active channels; C is the sum total of all output capacitors; ESR is the equivalent series resistance of the bulk output filter capacitance; and VPP is the peak-to-peak sawtooth signal amplitude, as described in the “Electrical Specifications” table. COMP E/A + C2 R2 COMP FB C3 R3 C1 R1 VDIFF ISL6308A FIGURE 20. COMPENSATION CONFIGURATION FOR NON-LOAD-LINE REGULATED ISL6308A Figure 21 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable, with a small number of adjustments, to the multi-phase ISL6308A circuit. The output voltage (VOUT) is regulated to the reference voltage, VREF, level. The error amplifier output (COMP pin FN6669 Rev 0.00 September 9, 2008 FB R1 VREF VDIFF + RGND VSEN VOUT OSCILLATOR VIN VOSC PWM CIRCUIT L UGATE HALF-BRIDGE DRIVE Compensating the Converter Operating Without Load-Line Regulation The ISL6308A multi-phase converter operating without load line regulation behaves in a similar manner to a voltagemode controller. This section highlights the design consideration for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 20). C3 R3 C1 - Once selected, the compensation values in Equations 28 assure a stable converter with reasonable transient performance. In most cases, transient performance can be improved by making adjustments to R2. Slowly increase the value of R2 while observing the transient performance on an oscilloscope until no further improvement is noted. Normally, C1 will not need adjustment. Keep the value of C1 from Equations 28 unless some performance issue is noted. The optional capacitor C2, is sometimes needed to bypass noise away from the PWM comparator (see Figure 19). Keep a position available for C2, and be prepared to install a high frequency capacitor of between 22pF and 150pF in case any leading edge jitter problem is noted. R2 DCR PHASE C ESR LGATE ISL6308A EXTERNAL CIRCUIT FIGURE 21. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis, L and DCR represent the individual channel inductance and its DCR divided by 3 (equivalent parallel value of the three output inductors), while C and ESR represents the total output capacitance and its equivalent series resistance. 1 F LC = --------------------------2  L  C 1 F CE = --------------------------------2  C  ESR (EQ. 29) The compensation network consists of the error amplifier (internal to the ISL6308A) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase Page 22 of 28 ISL6308A margin (better than 45°). Phase margin is the difference between the closed loop phase at F0dB and 180°. The equations that follow relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 20 and 21. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Select a value for R1 (1k to 5k, typically). Calculate value for R2 for desired converter bandwidth (F0). V OSC  R 1  F 0 R 2 = --------------------------------------------d MAX  V IN  F LC (EQ. 30) If setting the output voltage to be equal to the reference set voltage as shown in Figure 21, the design procedure can be followed as presented. However, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in Figure 6), in order to compensate for the attenuation introduced by the resistor divider, the obtained R2 value needs be multiplied by a factor of (RP + RS)/RP. The remainder of the calculations remain unchanged, as long as the compensated R2 value is used. 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC). 1 C 1 = ----------------------------------------------2  R 2  0.5  F LC (EQ. 31) 3. Calculate C2 such that FP1 is placed at FCE. C1 C 2 = -------------------------------------------------------2  R 2  C 1  F CE – 1 (EQ. 32) 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the per-channel switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. R1 R 3 = ---------------------F SW ------------ – 1 F LC (EQ. 33) 1 C 3 = ------------------------------------------------2  R 3  0.7  F SW It is recommended a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): d MAX  V IN 1 + s  f   ESR  C G MOD  f  = ------------------------------  ----------------------------------------------------------------------------------------------------------2 V OSC 1 + s  f    ESR + DCR   C + s  f   L  C 1 + s  f   R2  C1 G FB  f  = ----------------------------------------------------  s  f   R1   C1 + C2  (EQ. 34) 1 + s  f    R1 + R3   C3  ------------------------------------------------------------------------------------------------------------------------  C1  C2    1 + s  f   R 3  C 3    1 + s  f   R 2   ---------------------    C 1 + C 2  G CL  f  = G MOD  f   G FB  f  where s  f  = 2  f  j COMPENSATION BREAK FREQUENCY EQUATIONS 1 F Z1 = ------------------------------2  R 2  C 1 (EQ. 38) 1 F Z2 = ------------------------------------------------2   R 1 + R 3   C 3 (EQ. 35) 1 F P1 = --------------------------------------------C1  C2 2  R 2  --------------------C1 + C2 (EQ. 36) 1 F P2 = ------------------------------2  R 3  C 3 (EQ. 37) Figure 22 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the log-log graph of Figure 22 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the per-channel switching frequency, FSW. Output Filter Design The output inductors and the output capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. The output filter also must provide the transient energy until the regulator can FN6669 Rev 0.00 September 9, 2008 Page 23 of 28 ISL6308A FP1 FP2 GAIN FZ1 FZ2 R2 20 log  --------  R1 MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN d MAX  V IN 20 log --------------------------------V OSC 0 GFB LOG GCL GMOD LOG FLC FCE F0 FREQUENCY FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN respond. Because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. The output capacitors must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. In high-speed converters, the output capacitor bank is usually the most costly (and often the largest) part of the circuit. Output filter design begins with minimizing the cost of this part of the circuit. The critical load parameters in choosing the output capacitors are the maximum size of the load step, I, the load-current slew rate, di/dt, and the maximum allowable output-voltage deviation under transient loading, VMAX. Capacitors are characterized according to their capacitance, ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the voltage drop across the ESR increases linearly until the load current reaches its final value. The capacitors selected must have sufficiently low ESL and ESR so that the total outputvoltage deviation is less than the allowable maximum. Neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount di V   ESL   ----- +  ESR   I dt (EQ. 39) The filter capacitor must have sufficiently low ESL and ESR so that V < VMAX. Most capacitor solutions rely on a mixture of high frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. Minimizing the ESL of the high-frequency capacitors allows them to support the output voltage as the current increases. Minimizing the ESR of the bulk capacitors allows them to supply the increased current with less output voltage deviation. FN6669 Rev 0.00 September 9, 2008 The ESR of the bulk capacitors also creates the majority of the output-voltage ripple. As the bulk capacitors sink and source the inductor AC ripple current (see “Interleaving” on page 9 and Equation 2), a voltage develops across the bulk capacitor ESR equal to IC,PP (ESR). Thus, once the output capacitors are selected, the maximum allowable ripple voltage, VPP(MAX), determines the lower limit on the inductance. V – N  V  OUT  V OUT  IN L   ESR   -------------------------------------------------------------------F SW  V IN  V PP MAX  (EQ. 40) Since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. The output inductors must be capable of assuming the entire load current before the output voltage decreases more than VMAX. This places an upper limit on inductance. Equation 41 gives the upper limit on L for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. Equation 42 addresses the leading edge. Normally, the trailing edge dictates the selection of L because duty cycles are usually less than 50%. Nevertheless, both inequalities should be evaluated, and L should be selected based on the lower of the two results. In each equation, L is the per-channel inductance, C is the total output capacitance, and N is the number of active channels. 2  N  C  VO L  ---------------------------------  V MAX –  I  ESR   I  2 (EQ. 41)  1.25   N  C L  ----------------------------------  V MAX –  I  ESR    V IN – V O    I  2 (EQ. 42) Switching Frequency There are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper MOSFET loss calculation. These effects are outlined in “MOSFETs” on page 18, and they establish the upper limit for the switching frequency. The lower limit is established by the requirement for fast transient response and small outputvoltage ripple as outlined in “Output Filter Design” on page 23. Choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. Switching frequency is determined by the selection of the frequency-setting resistor, RFS. Figure 23 and Equation 43 are provided to assist in selecting the correct value for RFS: R FS = 10 10.61 – 1.035  log  F SW  (EQ. 43) Page 24 of 28 ISL6308A INPUT-CAPACITOR CURRENT (IRMS/IO) 0.3 RFS VALUE (k) 200 100 50 20 10 100k 1M 500k 200k SWITCHING FREQUENCY (Hz) 2M 0.2 0.1 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 FIGURE 23. RFS vs SWITCHING FREQUENCY The input capacitors are responsible for sourcing the AC component of the input current flowing into the upper MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. INPUT-CAPACITOR CURRENT (IRMS/IO) IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.25 IO IL,PP = 0.75 IO 0.6 0.8 1.0 0.2 0.1 FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 2-PHASE CONVERTER 0.6 INPUT-CAPACITOR CURRENT (IRMS/IO) Input Capacitor Selection 0.3 0.4 DUTY CYCLE (VIN/VO) 0.4 0.2 IL,PP = 0 IL,PP = 0.5 IO IL,PP = 0.75 IO 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VIN/VO) FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR SINGLE-PHASE CONVERTER 0 0 0.2 0.4 0.6 0.8 1.0 DUTY CYCLE (VIN/VO) FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS CURRENT FOR 3-PHASE CONVERTER For a three-phase design, use Figure 24 to determine the input-capacitor RMS current requirement set by the duty cycle, maximum sustained output current (IO), and the ratio of the peak-to-peak inductor current (IL,PP) to IO. Select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the RMS current calculated. The voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. Figures 25 and 26 provide the same input RMS current information for two-phase and single-phase designs respectively. Use the same approach for selecting the bulk capacitor type and number. FN6669 Rev 0.00 September 9, 2008 Low ESL, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Place them as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression. Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff Page 25 of 28 ISL6308A transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. There are two sets of critical components in a DC/DC converter using a ISL6308A controller. The power components are the most critical because they switch large amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. It is important to have a symmetrical layout, preferably with the controller equidistantly located from the three power trains it controls. Equally important are the gate drive lines (UGATE, LGATE, PHASE): since they drive the power train MOSFETs using short, high current pulses, it is important to size them as large and as short as possible to reduce their overall impedance and inductance. Extra care should be given to the LGATE traces in particular since keeping the impedance and inductance of these traces helps to significantly reduce the possibility of shoot-through. Equidistant placement of the controller to the three power trains also helps to keep these traces equally short (equal impedances, resulting in similar driving of both sets of MOSFETs). The power components should be placed first. Locate the input capacitors close to the power switches. Minimize the length of the connections between the input capacitors, CIN, and the power switches. Locate the output inductors and output capacitors between the MOSFETs and the load. Locate the high-frequency decoupling capacitors (ceramic) as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND immediately next, or even onto the capacitor solder pad. The critical small components include the bypass capacitors for VCC and PVCC. Locate the bypass capacitors, CBP, close to the device. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a highimpedance circuit loop, sensitive to EMI pick-up. It is also important to place current sense components close to their respective pins on the ISL6308A, including the RISEN resistors, RS, RCOMP, CCOMP. For proper current sharing route three separate symmetrical as possible traces from the corresponding phase node for each RISEN. A multi-layer printed circuit board is recommended. Figure 27 shows the connections of the critical components for the converter. Note that capacitors CxxIN and CxxOUT could each represent numerous physical capacitors. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to inductor LOUT short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the IC to the MOSFETs’ gates and sources should be sized to carry at least one ampere of current (0.02” to 0.05”). © Copyright Intersil Americas LLC 2008. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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For information regarding Intersil Corporation and its products, see www.intersil.com FN6669 Rev 0.00 September 9, 2008 Page 26 of 28 ISL6308A R1 C1 VDIFF LOCATE CLOSE TO IC (MINIMIZE CONNECTION PATH) C2 HEAVY TRACE ON CIRCUIT PLANE LAYER ISLAND ON POWER PLANE LAYER +12V R2 FB KEY ISLAND ON CIRCUIT PLANE LAYER CHF01 COMP VIA CONNECTION TO GROUND PLANE PVCC1 CBIN1 CHF1 BOOT1 +5V LOCATE NEAR SWITCHING TRANSISTORS; (MINIMIZE CONNECTION PATH) CBOOT1 VSEN RGND UGATE1 3PH 2PH PHASE1 LOUT1 ISEN1 VCC RISEN1 CHF0 LGATE1 ROFST OFST +12V CHF02 FS PVCC2 CHF2 RFS CBIN2 BOOT2 CBOOT2 DAC ISL6308A RREF UGATE2 PHASE2 REF CREF LOUT2 ISEN2 CBOUT (CHFOUT) RISEN2 LGATE2 LOAD REF1 REF0 +12V OVP PGOOD CHF03 CBIN3 PVCC3 LOCATE NEAR LOAD; (MINIMIZE CONNECTION PATH) CHF3 +12V BOOT3 GND CBOOT3 UGATE3 PHASE3 ENLL LOUT3 ISEN3 IREF RISEN3 DROOP OCSET ICOMP ISUM LGATE3 RS RCOMP RS RS ROCSET CCOMP CSUM FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS FN6669 Rev 0.00 September 9, 2008 Page 27 of 28 ISL6308A Package Outline Drawing L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 4X 4.5 6.00 36X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 40 31 30 1 6.00 4 . 10 ± 0 . 15 21 10 0.15 (4X) 11 20 TOP VIEW 0.10 M C A B 40X 0 . 4 ± 0 . 1 4 0 . 23 +0 . 07 / -0 . 05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 ( C BASE PLANE ( 5 . 8 TYP ) SEATING PLANE 0.08 C SIDE VIEW 4 . 10 ) ( 36X 0 . 5 ) C 0 . 2 REF 5 ( 40X 0 . 23 ) 0 . 00 MIN. 0 . 05 MAX. ( 40X 0 . 6 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. FN6669 Rev 0.00 September 9, 2008 Page 28 of 28