ISL6536AIB

ISL6536A ® Data Sheet May 2004 Four Channel Supervisory IC Features The ISL6536A is a four channel supervisory IC designed to monitor voltages >, = 0.7V. This IC bias range is from 2.7V to 5V but can supervise any positive voltage using an external resistor divider to translate to a lower voltage for comparison to the internal 0.63V reference. • 1% VMON Threshold accuracy Once properly biased and enabled when all four voltage monitor (VMON) inputs are satisfied the PGOOD output will be immediately released to go high to signal that voltage is valid on all four rails. Subsequently when the monitored voltage on any rail drops below its user defined threshold point, the PGOOD output is pulled low. Each rail’s VMON point is independently adjustable with a resistor divider. The PGOOD output is guaranteed to be valid with IC bias lower than 1V. The VMON inputs will ignore 30µs transients on the monitored supplies. The PGOOD output is an open-drain to allow ORing of multiple signals and interfacing to a range of logic levels. The ENABLE input provides for a reset of the PGOOD output when it is pulled down below 0.5V. With an internal 10uA pull-up to VDD it can be signalled with common logic or pulled to ground with a push button switch. • VMON Glitch Immunity FN9136.1 • Adjustable undervoltage lockout for each supply • Active high PGOOD Output • Guaranteed PGOOD Valid to Falling VDD < 1V • Pb-free Available as an Option Applications • Graphics Cards • Multi voltage DSPs and Processors • µP Voltage Monitoring • Embedded Control Systems • Intelligent Instruments • Medical Equipment • Network Routers • Portable Battery-Powered Equipment ISL6536A *OPT V1 IN V2 IN • Set-Top Boxes V3 IN V4 IN Typical Application Schematic • Telecommunications Systems Ordering Information PART NUMBER TEMP. RANGE (°C) PKG. DWG. # 1 VDD VMON1 8 2 PGD VMON2 7 ISL6536AIB -40 to +85 8 Lead SOIC M8.15 3 EN VMON3 6 ISL6536AIBZ (See Note) -40 to +85 8 Lead SOIC (Pb-free) M8.15 4 GND VMON4 5 PACKAGE ISL6536AIB-T 8 Lead SOIC Tape and Reel ISL6536AIBZ-T (See Note) 8 Lead SOIC Tape and Reel (Pb-free) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL6536A Pin Descriptions ISL6536A PIN NAME FUNCTION DESCRIPTION 1 VDD 2 PGOOD PGOOD is the boolean AND function of all the UV inputs being satisfied. This is an open drain output and can be pulled high to the appropriate level with an external resistor. Additionally a 20kΩ pull up to VDD is provided internally. 3 ENABLE Enabling input for supervisory function. Has a 10µA pull-up to VDD 4 GND 5-8 VMON1 VMON2 VMON3 VMON4 Bias IC from nominal 2.7V to 5V IC ground These inputs provide for a programmable monitored voltage threshold referenced to an internal 0.633V reference with 1% accuracy. These inputs have a 30µs glitch filter to prevent transient upsets from being recognized by PGOOD. VDD EN 10µA VMON1 20K VMON2 FALLING EDGE GLITCH FILTER VMON3 VMON4 + ISL6536A 633mV - 2 PGOOD ISL6536A Absolute Maximum Ratings Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V VMON, PGOOD, ENABLE. . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (HBM) Thermal Resistance (Typical, Note 1) θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C Operating Conditions VDD Supply Voltage Range. . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details. 2. 2. All voltages are relative to GND, unless otherwise specified. Nominal VDD = 3.3V, TA = TJ = -40oC - 85°C, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VMON > VMON_L2H - 165 1000 µA BIAS IC Supply Current IVDD VDD Power On VDD_L2H VDD low to high - 2.6 - V VDD Power On Reset VDD_POR VDD high to low - 2.4 - V Pull-Down Current PGpd VPGOOD = 0.5V - 2 - mA Pull-Up Resistance PGpu - 20 - kΩ Output Low VPGl VDD= 1V - 0.05 0.1 V Last valid input = Vth to PG release - 2 - µs PGOOD Delay from VMON Rising TPGdelVMON Delay from EN Rising TPGdelENR EN high to PG release - 0.05 - µs Delay from EN Falling TPGdelENF EN low to PG pulling low - 0.015 - µs 0.4VDD 0.5VDD 0.6VDD V - 0.065 - V - 10 - µA 0.627 0.633 0.639 V ENABLE Rising Threshold VEN Threshold Hysteresis ENABLE Low to High Threshold VEN_HYS Pull-up Current IENpu VEN = 0.5V VMON INPUT Falling Threshold 3.3VMON_H2L Falling Threshold Temp Coefficient 3.3VMON_TC - 33 - µV/°C Hysteresis VVMON_HYS - 10 - mV Range VMON_RNG - 1 - mV - 30 - µs Glitch Filter Duration TFIL 3 Tj=+25c VMON glitch to PGOOD low Filter ISL6536A ISL6536A Description and Operation The ISL6536A is a four channel supervisory IC with industry leading 1% tolerance and 1mV range between channels. This IC is designed to monitor multiple voltages greater than 0.7V and is suitable for both microprocessors or industrial system applications. Upon VDD bias power up the PGOOD output is held low with VDD as low as 0V. Once biased to 2.7V and enabled the IC continuously monitors from one to four voltages independently through external resistor dividers comparing each VMON pin voltage to an internal 0.63V reference. Once all VMON input voltages rise above 0.63V the PGOOD (power good) output signal is released and is pulled high via an external pull resistor to indicate that the power conditions have been met. The PGOOD output is an open-drain to allow ORing of the signals and interfacing to a wide range of logic levels. Once any VMON input falls below 0.63V the PGOOD output is pulled low, the VMON inputs are designed to reject fast transients (30µs). If less than four voltages are being monitored, connect the unused VMON pins to VDD. The PGOOD pin has an internal 20kΩ pull-up to VDD making an external pull-up resistor unnecessary. Figure 1 illustrates the operational timing diagram. 4/5 EN/VMON INPUTS HIGH VTH LAST EN/VMON INPUT