DATASHEET
ISL6566
FN9178
Rev 4.00
Mar 9, 2006
Three-Phase Buck PWM Controller with Integrated MOSFET Drivers for VRM9,
VRM10, and AMD Hammer Applications
The ISL6566 three-phase PWM control IC provides a
precision voltage regulation system for advanced
microprocessors. The integration of power MOSFET drivers
into the controller IC marks a departure from the separate
PWM controller and driver configuration of previous multiphase product families. By reducing the number of external
parts, this integration is optimized for a cost and space
saving power management solution.
Features
Outstanding features of this controller IC include
programmable VID codes compatible with Intel VRM9,
VRM10, as well as AMD Hammer microprocessors. A unity
gain, differential amplifier is provided for remote voltage
sensing, compensating for any potential difference between
remote and local grounds. The output voltage can also be
positively or negatively offset through the use of a single
external resistor.
• Precision Channel Current Sharing
- Uses Loss-Less rDS(ON) Current Sampling
• Accurate Load Line Programming
- Uses Loss-Less Inductor DCR Current Sampling
• Variable Gate Drive Bias: 5V to 12V
• Microprocessor Voltage Identification Inputs
- Up to a 6-Bit DAC
- Selectable between Intel’s VRM9, VRM10, or AMD
Hammer DAC Codes
- Dynamic VID Technology
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
• Digital Soft-Start
• Selectable Operation Frequency up to 1.5MHz Per Phase
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
VID4
ENLL
FS
PGOOD
LGATE1
PVCC1
ISEN1
UGATE1
ISL6566 (QFN)
TOP VIEW
VID3
Protection features of this controller IC include a set of
sophisticated overvoltage, undervoltage, and overcurrent
protection. Overvoltage results in the converter turning the
lower MOSFETs ON to clamp the rising output voltage and
protect the microprocessor. The overcurrent protection level
is set through a single external resistor. Furthermore, the
ISL6566 includes protection against an open circuit on the
remote sensing inputs. Combined, these features provide
advanced protection for the microprocessor and power
system.
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- 0.5% System Accuracy Over Temperature
- Adjustable Reference-Voltage Offset
VID2
A unique feature of the ISL6566 is the combined use of both
DCR and rDS(ON) current sensing. Load line voltage
positioning (droop) and overcurrent protection are
accomplished through continuous inductor DCR current
sensing, while rDS(ON) current sensing is used for accurate
channel-current balance. Using both methods of current
sampling utilizes the best advantages of each technique.
• Integrated Multi-Phase Power Conversion
- 1, 2, or 3-Phase Operation
40
39
38
37
36
35
34
33
32
31
VID1
1
30 BOOT1
VID0
2
29 PHASE1
VID12.5
3
28 PHASE2
VRM10
4
27 UGATE2
REF
5
OFS
6
VCC
7
24 PVCC2
COMP
8
23 LGATE2
FB
9
22 PHASE3
26 BOOT2
41
GND
25 ISEN2
VDIFF 10
FN9178 Rev 4.00
Mar 9, 2006
13
14
15
16
17
18
VSEN
OCSET
ICOMP
ISUM
IREF
LGATE3
PVCC3
19
20
UGATE3
12
ISEN3
11
RGND
21 BOOT3
Page 1 of 30
ISL6566
Ordering Information
PART NUMBER
PART
MARKING
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
ISL6566CRR5184
ISL6566CR
0 to 70
40 Ld 6x6 QFN
L40.6x6
ISL6566CR-TR5184
ISL6566CR
0 to 70
40 Ld 6x6 QFN Tape and Reel
L40.6x6
ISL6566CRZR5184 (Note)
ISL6566CRZ
0 to 70
40 Ld 6x6 QFN (Pb-free)
L40.6x6
ISL6566CRZ-TR5184 (Note)
ISL6566CRZ
0 to 70
40 Ld 6x6 QFN (Pb-free) Tape and Reel
L40.6x6
ISL6566CRZAR5184 (Note)
ISL6566CRZ
0 to 70
40 Ld 6x6 QFN (Pb-free)
L40.6x6
ISL6566CRZA-TR5184 (Note)
ISL6566CRZ
0 to 70
40 Ld 6x6 QFN (Pb-free) Tape and Reel
L40.6x6
ISL6566IR
ISL6566IR
-40 to 85
40 Ld 6x6 QFN
L40.6x6
ISL6566IR-T
ISL6566IR
-40 to 85
40 Ld 6x6 QFN Tape and Reel
L40.6x6
ISL6566IRZ (Note)
ISL6566IRZ
-40 to 85
40 Ld 6x6 QFN (Pb-free)
L40.6x6
ISL6566IRZ-T (Note)
ISL6566IRZ
-40 to 85
40 Ld 6x6 QFN (Pb-free) Tape and Reel
L40.6x6
ISL6566IRZA (Note)
ISL6566IRZ
-40 to 85
40 Ld 6x6 QFN (Pb-free)
L40.6x6
ISL6566IRZA-T (Note)
ISL6566IRZ
-40 to 85
40 Ld 6x6 QFN (Pb-free)
L40.6x6
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9178 Rev 4.00
Mar 9, 2006
Page 2 of 30
ISL6566
Block Diagram
ICOMP
ENLL
PGOOD
OCSET
100A
ISEN AMP
0.66V
ISUM
POWER-ON
RESET
OC
IREF
VCC
PVCC1
RGND
VSEN
BOOT1
+1V
UGATE1
SOFT-START
AND
x1
x1
GATE
CONTROL
LOGIC
FAULT LOGIC
SHOOTTHROUGH
PROTECTION
PHASE1
VDIFF
LGATE1
UVP
0.2V
FS
OVP
PVCC2
CLOCK AND
SAWTOOTH
GENERATOR
OVP
VOVP
BOOT2
UGATE2
PWM1
GATE
CONTROL
LOGIC
+150mV
x 0.82
SHOOTTHROUGH
PROTECTION
PHASE2
PWM2
LGATE2
VID4
VID3
VID2
VID1
VID0
DYNAMIC
VID
D/A
PWM3
CHANNEL
DETECT
PVCC3
VID12.5
VRM10
BOOT3
REF
CHANNEL
CURRENT
BALANCE
E/A
FB
1
N
COMP
OFS
UGATE3
GATE
CONTROL
LOGIC
SHOOTTHROUGH
PROTECTION
OFFSET
PHASE3
LGATE3
CHANNEL
CURRENT
SENSE
ISEN1
FN9178 Rev 4.00
Mar 9, 2006
ISEN2
ISEN3
GND
Page 3 of 30
ISL6566
Typical Application - ISL6566
+12V
VDIFF
FB
COMP
VSEN
PVCC1
BOOT1
RGND
UGATE1
+5V
PHASE1
VCC
ISEN1
LGATE1
OFS
+12V
FS
PVCC2
REF
VID4
ISL6566
BOOT2
UGATE2
VID3
PHASE2
VID2
ISEN2
VID1
LOAD
LGATE2
VID0
VID12.5
VRM10
+12V
PGOOD
+12V
PVCC3
GND
BOOT3
UGATE3
PHASE3
ENLL
ISEN3
IREF
OCSET
ICOMP
FN9178 Rev 4.00
Mar 9, 2006
ISUM
LGATE3
Page 4 of 30
ISL6566
Typical Application - ISL6566 with NTC Thermal Compensation
+12V
VDIFF
FB
COMP
VSEN
PVCC1
BOOT1
RGND
UGATE1
+5V
PHASE1
VCC
ISEN1
LGATE1
OFS
+12V
FS
PVCC2
REF
VID4
ISL6566
BOOT2
UGATE2
VID3
PHASE2
VID2
ISEN2
VID1
LOAD
LGATE2
VID0
VID12.5
VRM10
PGOOD
+12V
+12V
PVCC3
GND
BOOT3
PLACE IN CLOSE
PROXIMITY
UGATE3
ENLL
IREF
OCSET
ICOMP
FN9178 Rev 4.00
Mar 9, 2006
PHASE3
ISEN3
NTC
LGATE3
ISUM
Page 5 of 30
ISL6566
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Supply Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +15V
Absolute Boot Voltage, VBOOT . . . . . . . . GND - 0.3V to GND + 36V
Phase Voltage, VPHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V ( -----------------------------2C ESR
2 f 0 V pp L
R C = R FB ----------------------------------------0.66 V IN ESR
0.66V IN ESR C
C C = -----------------------------------------------2V PP R FB f 0 L
In Equations 29, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent series resistance of
the bulk output filter capacitance; and VPP is the peak-to-peak
sawtooth signal amplitude as described in the Electrical
Specifications.
Once selected, the compensation values in Equations 29
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to RC. Slowly increase the
value of RC while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from
Equations 29 unless some performance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep a
position available for C2, and be prepared to install a high-
FN9178 Rev 4.00
Mar 9, 2006
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. Because it
has a low bandwidth compared to the switching frequency, the
output filter limits the system transient response. The output
capacitors must supply or sink load current while the current in
the output inductors increases or decreases to meet the
demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit. Output
filter design begins with minimizing the cost of this part of the
circuit. The critical load parameters in choosing the output
capacitors are the maximum size of the load step, I, the loadcurrent slew rate, di/dt, and the maximum allowable outputvoltage deviation under transient loading, VMAX. Capacitors
are characterized according to their capacitance, ESR, and
ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will initially
deviate by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL
and ESR so that the total output-voltage deviation is less than
the allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount
di
V ESL ----- + ESR I
dt
(EQ. 30)
The filter capacitor must have sufficiently low ESL and ESR so
that V < VMAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited highfrequency performance. Minimizing the ESL of the highfrequency capacitors allows them to support the output voltage
as the current increases. Minimizing the ESR of the bulk
capacitors allows them to supply the increased current with less
output voltage deviation.
The ESR of the bulk capacitors also creates the majority of the
output-voltage ripple. As the bulk capacitors sink and source
the inductor ac ripple current (see Interleaving and Equation 2),
a voltage develops across the bulk capacitor ESR equal to
IC,PP(ESR). Thus, once the output capacitors are selected, the
maximum allowable ripple voltage, VPP(MAX), determines the
lower limit on the inductance.
V – N V
OUT V OUT
IN
L ESR -----------------------------------------------------------f S V IN V PP MAX
(EQ. 31)
Page 24 of 30
ISL6566
Equation 32 gives the upper limit on L for the cases when the
trailing edge of the current transient causes a greater outputvoltage deviation than the leading edge. Equation 33
addresses the leading edge. Normally, the trailing edge dictates
the selection of L because duty cycles are usually less than
50%. Nevertheless, both inequalities should be evaluated, and
L should be selected based on the lower of the two results. In
each equation, L is the per-channel inductance, C is the total
output capacitance, and N is the number of active channels.
2 N C VO
L --------------------------------- V MAX – I ESR
I 2
(EQ. 32)
1.25 N C
L ---------------------------------- V MAX – I ESR V IN – V O
I 2
(EQ. 33)
Input Capacitor Selection
The input capacitors are responsible for sourcing the ac
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
Since the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
before the output voltage decreases more than VMAX. This
places an upper limit on inductance.
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.25 IO
IL,PP = 0.75 IO
0.2
0.1
0
0
0.2
Switching Frequency
There are a number of variables to consider when choosing the
switching frequency, as there are considerable effects on the
upper MOSFET loss calculation. These effects are outlined in
MOSFETs, and they establish the upper limit for the switching
frequency. The lower limit is established by the requirement for
fast transient response and small output-voltage ripple as
outlined in Output Filter Design. Choose the lowest switching
frequency that allows the regulator to meet the transientresponse requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RT. Figure 21 and Equation 34 are
provided to assist in selecting the correct value for RT.
R T = 10
0.6
0.8
1.0
(EQ. 34)
10.61 – 1.035 log f S
FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 3-PHASE CONVERTER
For a three-phase design, use Figure 22 to determine the inputcapacitor RMS current requirement set by the duty cycle,
maximum sustained output current (IO), and the ratio of the
peak-to-peak inductor current (IL,PP) to IO. Select a bulk
capacitor with a ripple current rating which will minimize the
total number of input capacitors required to support the RMS
current calculated. The voltage rating of the capacitors should
also be at least 1.25 times greater than the maximum input
voltage. Figures 23 and 24 provide the same input RMS current
information for two-phase and single-phase designs
respectively. Use the same approach for selecting the bulk
capacitor type and number.
1000
0.3
INPUT-CAPACITOR CURRENT (IRMS/IO)
RT (k)
0.4
DUTY CYCLE (VIN/VO)
100
10
10
100
1000
10000
SWITCHING FREQUENCY (kHz)
0.2
0.1
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
0
0
0.2
0.4
0.6
0.8
DUTY CYCLE (VIN/VO)
FIGURE 21. RT vs SWITCHING FREQUENCY
FN9178 Rev 4.00
Mar 9, 2006
FIGURE 23. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
Page 25 of 30
1.0
ISL6566
all three power trains. Equidistant placement of the controller to
the three power trains also helps keep the gate drive traces
equally short, resulting in equal trace impedances and similar
drive capability of all sets of MOSFETs.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.6
0.4
0.2
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
0
0
0.2
0.4
0.6
0.8
1.0
DUTY CYCLE (VIN/VO)
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR SINGLE-PHASE CONVERTER
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the input bulk capacitors to suppress
leading and falling edge voltage spikes. The spikes result from
the high current slew rate produced by the upper MOSFET turn
on and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitics and maximize suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. These voltage spikes can
degrade efficiency, radiate noise into the circuit and lead to
device overvoltage stress. Careful component selection,
layout, and placement minimizes these voltage spikes.
Consider, as an example, the turnoff transition of the upper
PWM MOSFET. Prior to turnoff, the upper MOSFET was
carrying channel current. During the turnoff, current stops
flowing in the upper MOSFET and is picked up by the lower
MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes.
There are two sets of critical components in a DC-DC
converter using a ISL6566 controller. The power components
are the most critical because they switch large amounts of
energy. Next are small signal components that connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first, which include the
MOSFETs, input and output capacitors, and the inductors. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each.
Symmetrical layout allows heat to be dissipated equally across
FN9178 Rev 4.00
Mar 9, 2006
When placing the MOSFETs try to keep the source of the upper
FETs and the drain of the lower FETs as close as thermally
possible. Input Bulk capacitors should be placed close to the
drain of the upper FETs and the source of the lower FETs. Locate
the output inductors and output capacitors between the
MOSFETs and the load. The high-frequency input and output
decoupling capacitors (ceramic) should be placed as close as
practicable to the decoupling target, making use of the shortest
connection paths to any internal planes, such as vias to GND next
or on the capacitor solder pad.
The critical small components include the bypass capacitors
for VCC and PVCC, and many of the components surrounding
the controller including the feedback network and current
sense components. Locate the VCC/PVCC bypass capacitors
as close to the ISL6566 as possible. It is especially important
to locate the components associated with the feedback circuit
close to their respective controller pins, since they belong to a
high-impedance circuit loop, sensitive to EMI pick-up. It is also
important to place the current sense components close to their
respective pins on the ISL6566, including RISEN, RS, RCOMP,
and CCOMP.
A multi-layer printed circuit board is recommended. Figure 25
shows the connections of the critical components for the
converter. Note that capacitors CxxIN and CxxOUT could each
represent numerous physical capacitors. Dedicate one solid layer,
usually the one underneath the component side of the board, for a
ground plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a power
plane and break this plane into smaller islands of common voltage
levels. Keep the metal runs from the PHASE terminal to output
inductors short. The power plane should support the input power
and output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring.
Routing UGATE, LGATE, and PHASE traces
Great attention should be paid to routing the UGATE, LGATE,
and PHASE traces since they drive the power train MOSFETs
using short, high current pulses. It is important to size them as
large and as short as possible to reduce their overall impedance
and inductance. They should be sized to carry at least one
ampere of current (0.02” to 0.05”). Going between layers with
vias should also be avoided, but if so, use two vias for
interconnection when possible.
Extra care should be given to the LGATE traces in particular
since keeping their impedance and inductance low helps to
significantly reduce the possibility of shoot-through. It is also
important to route each channels UGATE and PHASE traces in
as close proximity as possible to reduce their inductances.
Page 26 of 30
ISL6566
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal GND
pad of the ISL6566 to the ground plane with multiple vias is
recommended. This heat spreading allows the part to achieve
its full thermal potential. It is also recommended that the
controller be placed in a direct path of airflow if possible to help
thermally manage the part.
Suppressing MOSFET Gate Leakage
With VCC at ground potential, UGATE is high impedance. In
this state, any stray leakage has the potential to deliver charge
to the gate of the upper MOSFET. If UGATE receives sufficient
charge to bias the device on, a low impedance path will be
connected between the upper MOSFET drain and PHASE. If
this occurs and the input power supply is present and active,
the system could see potentially damaging current. Worst-case
leakage currents are on the order of pico-amps; therefore, a
10k resistor, connected from UGATE to PHASE, is more than
sufficient to bleed off any stray leakage current. This resistor
will not affect the normal performance of the driver or reduce its
efficiency.
FN9178 Rev 4.00
Mar 9, 2006
Page 27 of 30
ISL6566
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
C2
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
RFB
ISLAND ON POWER PLANE LAYER
+12V
C1
VDIFF
ISLAND ON CIRCUIT PLANE LAYER
R1
FB
VIA CONNECTION TO GROUND PLANE
COMP
PVCC1
(CF2)
CBIN1
BOOT1
LOCATE NEAR SWITCHING TRANSISTORS;
(MINIMIZE CONNECTION PATH)
CBOOT1
VSEN
UGATE1
RGND
+5V
PHASE1
VCC
(CF1)
ISEN1
RISEN1
LGATE1
ROFS
OFS
+12V
FS
RT
PVCC2
REF
(CF2)
CREF
CBIN2
BOOT2
CBOOT2
VID4
ISL6566
UGATE2
VID3
PHASE2
VID2
ISEN2
CBOUT
(CHFOUT)
RISEN2
VID1
LOAD
LGATE2
VID0
VID12.5
+12V
VRM10
PGOOD
CBIN3
PVCC3
(CF2)
+12V
BOOT3
GND
LOCATE NEAR LOAD;
(MINIMIZE CONNECTION PATH)
CBOOT3
UGATE3
PHASE3
ENLL
ISEN3
IREF
RISEN3
OCSET
ICOMP
ISUM
RCOMP
LGATE3
RS
RS
ROCSET
RS
CCOMP
FIGURE 25. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN9178 Rev 4.00
Mar 9, 2006
Page 28 of 30
ISL6566
© Copyright Intersil Americas LLC 2004-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9178 Rev 4.00
Mar 9, 2006
Page 29 of 30
ISL6566
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
2X
9
MILLIMETERS
D/2
D1
D1/2
2X
N
6
INDEX
AREA
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJD-2 ISSUE C)
0.15 C A
D
A
L40.6x6
0.15 C B
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
1
2
3
E1/2
E/2
E1
b
D2
0.15 C B
0.15 C A
4X
B
TOP VIEW
0
A
C
0.08 C
SEATING PLANE
A1
A3
SIDE VIEW
9
5
NX b
0.10 M C A B
4X P
D2
(DATUM B)
8
7
NX k
D2
2 N
4X P
4.10
(Ne-1)Xe
REF.
E2
N e
8
6.00 BSC
-
5.75 BSC
9
3.95
4.10
k
0.25
-
-
-
L
0.30
0.40
0.50
8
L1
-
-
0.15
10
N
40
2
Nd
10
3
Ne
10
3
P
-
-
0.60
9
-
-
12
9
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
SECTION "C-C"
L1
10
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
C
L
L
e
L1
10
L
e
C C
TERMINAL TIP
FN9178 Rev 4.00
Mar 9, 2006
-
3. Nd and Ne refer to the number of terminals on each D and E.
A1
FOR ODD TERMINAL/SIDE
7, 8
2. N is the number of terminals.
8
BOTTOM VIEW
C
L
4.25
0.50 BSC
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
9
CORNER
OPTION 4X
(Nd-1)Xe
REF.
7, 8
NOTES:
7
E2/2
NX L
9
4.25
Rev. 1 10/02
2
3
6
INDEX
AREA
-
E
1
(DATUM A)
5, 8
5.75 BSC
3.95
e
/ / 0.10 C
0.30
E1
E2
A2
0.23
9
6.00 BSC
D1
9
2X
2X
0.18
D
E
9
0.20 REF
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FOR EVEN TERMINAL/SIDE
Page 30 of 30
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