X28HC64_09

® X28HC64 64k, 8k x 8-Bit Data Sheet August 28, 2009 FN8109.2 5 Volt, Byte Alterable EEPROM The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil’s proprietary, high performance, floating gate CMOS technology. Like all Intersil programmable nonvolatile memories, the X28HC64 is a 5V only device. It features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs. The X28HC64 supports a 64-byte page write operation, effectively providing a 32µs/byte write cycle, and enabling the entire memory to be typically written in 0.25 seconds. The X28HC64 also features DATA Polling and Toggle Bit Polling, two methods providing early end of write detection. In addition, the X28HC64 includes a user-optional software data protection mode that further enhances Intersil’s hardware write protect capability. Intersil EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. Features • 70ns access time • Simple byte and page write - Single 5V supply - No external high voltages or VPP control circuits - Self-timed - No erase before write - No complex programming algorithms - No overerase problem • Low power CMOS - 40mA active current max. • 200µA standby current max. • Fast write cycle times - 64-byte page write operation - Byte or page write cycle: 2ms typical - Complete memory rewrite: 0.25 sec. typical - Effective byte write cycle time: 32µs typical • Software data protection • End of write detection - DATA polling - Toggle bit • High reliability - Endurance: 100000 cycles - Data retention: 100 years • JEDEC approved byte-wide pin out • Pb-free available (RoHS compliant) Pinouts X28HC64 (28 LD PDIP, SOIC) TOP VIEW NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 8 9 10 11 12 13 14 28 27 26 25 24 23 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 A7 X28HC64 (32 LD PLCC) TOP VIEW A12 VCC WE NC NC NC 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 A8 A9 A11 NC OE A10 CE I/O7 I/O6 7 X28HC64 22 X28HC64 (Top View) 13 21 14 15 16 17 18 19 20 I/O1 I/O2 I/O3 I/O4 VSS I/O5 NC 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X28HC64 Ordering Information PART NUMBER X28HC64J-70* X28HC64JIZ-70* (Note 1) X28HC64JZ-70* (Note 1) X28HC64SIZ-70 X28HC64SZ-70 (Note 1) X28HC64J-90* X28HC64JI-90** X28HC64JIZ-90* (Note 1) X28HC64P-90 X28HC64PI-90 PART MARKING X28HC64J-70 RR X28HC64JI-70 ZRR X28HC64J-70 ZRR X28HC64SI-70 RR X28HC64S-70 RRZ X28HC64J-90 RR X28HC64JI-90 RR X28HC64JI-90 ZRR X28HC64P-90 RR X28HC64PI-90 RR TEMPERATURE RANGE (°C) 0 to +70 -40 to +85 0 to +70 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 120 90 ACCESS TIME (ns) 70 PACKAGE 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC (Pb-free) 28 Ld SOIC (300 mil) 28 Ld SOIC (300 mil) (Pb-free) 32 Ld PLCC 32 Ld PLCC 32 Ld PLCC (Pb-free) 28 Ld PDIP 28 Ld PDIP 28 Ld PDIP (Pb-free) 28 Ld PDIP (Pb-free) 32 Ld PLCC 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC (Pb-free) 28 Ld PDIP 28 Ld PDIP 28 Ld PDIP (Pb-free) 28 Ld PDIP (Pb-free) 28 Ld SOIC (300 mil) 28 Ld SOIC (300 mil) 28 Ld SOIC (300 mil) (Pb-free) 28 Ld SOIC (300 mil) (Pb-free) PKG. DWG. # N32.45x55 N32.45x55 N32.45x55 M28.3 M28.3 N32.45x55 N32.45x55 N32.45x55 E28.6 E28.6 E28.6 E28.6 N32.45x55 N32.45x55 N32.45x55 N32.45x55 E28.6 E28.6 E28.6 E28.6 M28.3 M28.3 M28.3 M28.3 X28HC64PIZ-90 (Notes 1, 2) X28HC64PI-90 RRZ X28HC64PZ-90 (Notes 1, 2) X28HC64P-90 RRZ X28HC64J-12* X28HC64JI-12* X28HC64JIZ-12* (Note 1) X28HC64JZ-12* (Note 1) X28HC64P-12 X28HC64PI-12 X28HC64J-12 RR X28HC64JI-12 RR X28HC64JI-12 Z RR X28HC64J-12 RRZ X28HC64P-12 RR X28HC64PI-12 RR X28HC64PIZ-12 (Notes 1, 2) X28HC64PI-12 RRZ X28HC64PZ-12 (Notes 1, 2) X28HC64P-12 RRZ X28HC64S-12*, X28HC64SI-12* X28HC64SIZ-12* (Note 1) X28HC64SZ-12 (Note 1) ** X28HC64S-12 RR X28HC64SI-12 RR X28HC64SI-12 RRZ X28HC64S-12 RRZ *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. ***Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 2 FN8109.2 August 28, 2009 X28HC64 Pin Descriptions Addresses (A0-A12) The Address inputs select an 8-bit memory location during a read or write operation. Device Operation Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC64 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 2ms. Data In/Data Out (I/O0-I/O7) Data is written to or read from the X28HC64 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28HC64. TABLE 1. PIN NAMES SYMBOL A0-A12 I/O0-I/O7 WE CE OE VCC VSS NC DESCRIPTION Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect Page Write Operation The page write feature of the X28HC64 allows the entire memory to be written in 0.25 seconds. Page write allows two to sixty-four bytes of data to be consecutively written to the X28HC64 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A6 through A12) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Block Diagram 65,536-BIT X BUFFERS LATCHES AND DECODER A0–A12 ADDRESS INPUTS Y BUFFERS LATCHES AND DECODER I/O BUFFERS AND LATCHES EEPROM ARRAY Write Operation Status Bits The X28HC64 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. I/O DP TB 5 4 3 2 1 0 CE OE WE VCC VSS CONTROL LOGIC AND TIMING I/O0–I/O7 DATA INPUTS/OUTPUTS RESERVED TOGGLE BIT DATA POLLING FIGURE 1. STATUS BIT ASSIGNMENT 3 FN8109.2 August 28, 2009 X28HC64 DATA Polling (I/O7) The X28HC64 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC64, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28HC64 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. DATA Polling I/O7 WE Last Write CE OE VIH I/O7 HIGH Z VOL A0–A12 VOH X28HC64 Ready An An An An An An An FIGURE 2. DATA POLLING BUS SEQUENCE WRITE DATA DATA Polling can effectively reduce the time for writing to the X28HC64. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine. NO WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS READ LAST ADDRESS IO7 COMPARE? YES NO READY FIGURE 3. DATA POLLING SOFTWARE FLOW 4 FN8109.2 August 28, 2009 X28HC64 The Toggle Bit I/O6 WE LAST WRITE CE OE I/O6 VOH * VOL HIGH Z * X28HC64 READY * BEGINNING AND ENDING STATE OF I/O6 WILL VARY. FIGURE 4. TOGGLE BIT BUS SEQUENCE Hardware Data Protection LAST WRITE The X28HC64 provides two hardware features that protect nonvolatile data from inadvertent writes. • Default VCC Sense—All write functions are inhibited when VCC is 3V typically. • Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity. YES LOAD ACCUM FROM ADDR N Software Data Protection COMPARE ACCUM WITH ADDR N COMPARE OK? YES NO The X28HC64 offers a software controlled data protection feature. The X28HC64 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/-down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC64 can be automatically protected during powerup and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device, unless the reset command is issued. Once the software protection is enabled, the X28HC64 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. READY FIGURE 5. TOGGLE BIT SOFTWARE FLOW The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC64 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit. Software Algorithm Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window, enabling the host to write from one to sixty-four bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. FN8109.2 August 28, 2009 5 X28HC64 Software Data Protection VCC 0V DATA ADDR CE ≤tBLC MAX WE BYTE OR PAGE AAA 1555 55 0AAA A0 1555 WRITES OK (VCC) tWC WRITE PROTECTED FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE WRITE DATA AA TO ADDRESS 1555 WRITE DATA 55 TO ADDRESS 0AAA Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used, the X28HC64 will automatically disable further writes unless another command is issued to deactivate it. If no further commands are issued the X28HC64 will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA A0 TO ADDRESS 1555 BYTE/PAGE LOAD ENABLED WRITE DATA XX TO ANY ADDRESS OPTIONAL BYTE/PAGE LOAD OPERATION WRITE LAST BYTE TO LAST ADDRESS AFTER TWC RE-ENTERS DATA PROTECTED STATE FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA PROTECTION 6 FN8109.2 August 28, 2009 X28HC64 Resetting Software Data Protection VCC DATA ADDR CE AAA 1555 55 0AAA 80 1555 AA 1555 55 0AAA 20 1555 ≥tWC STANDARD OPERATING MODE WE FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE WRITE DATA AA TO ADDRESS 1555 In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC64 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA 55 TO ADDRESS 0AAA WRITE DATA 80 TO ADDRESS 1555 WRITE DATA AA ADDRESS 1555 WRITE DATA 55 TO ADDRESS 0AAA WRITE DATA 20 TO ADDRESS 1555 FIGURE 9. SOFTWARE SEQUENCE TO DEACTIVATE SOFTWARE 7 FN8109.2 August 28, 2009 X28HC64 System Considerations Because the X28HC64 is frequently used in large memory arrays, it is provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus, and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. Because the X28HC64 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. 1.4 1.2 NORMALIZED (mA) + 25°C + 125°C ICCRD 1.0 0.8 0.6 0.4 0.2 5.5VCC 1.4 1.2 NORMALIZED (mA) 1.0 0.8 0.6 0.4 0.2 5.5VCC - 55°C 5.0VCC 4.5VCC ICCRD 0M 10M FREQUENCY (Hz) 20M 0M 10M FREQUENCY (Hz) 20M FIGURE 10. NORMALIZED ICC(RD) BY TEMPERATURE OVER FREQUENCY DATA PROTECTION FIGURE 11. NORMALIZED ICC(RD) @ 25% OVER THE VCC RANGE AND FREQUENCY 8 FN8109.2 August 28, 2009 X28HC64 Absolute Maximum Ratings Temperature Under Bias X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C X28HC64I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on any Pin with Respect to Vss . . . . . . . . . . . . . . -1V to +7V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Thermal Information Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Recommended Operating Conditions Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage Range X28HC64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. DC Electrical Specifications Over recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER VCC Current (active) (TTL Inputs) VCC Current (Standby) (TTL Inputs) VCC Current (Standby) (CMOS Inputs) Input Leakage Current Output Leakage Current Input LOW Voltage (Note 4) Input HIGH Voltage (Note 4) Output LOW Voltage Output HIGH Voltage NOTES: SYMBOL ICC ISB1 ISB2 ILI ILO VlL VIH VOL VOH IOL = 5mA IOH = -5mA TEST CONDITIONS CE = OE = VIL, WE = VIH, All I/O’s = open, address inputs = TTL levels @ f = 10 MHz CE = VIH, OE = VIL All I/O’s = open, other inputs = VIH CE = VCC - 0.3V, OE = GND, All I/O’s = open, other inputs = VCC - 0.3V VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH TYP MIN (Note 3) 15 1 100 MAX 40 2 200 ±10 ±10 UNIT mA mA µA µA µA V V V V -1 2 0.8 VCC + 1 0.4 2.4 3. Typical values are for TA = +25°C and nominal supply voltage 4. VIL min. and VIH max. are for reference only and are not tested. Endurance and Data Retention PARAMETER Minimum Endurance Data Retention Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. MIN 100,000 100 MAX UNIT Cycles Years 9 FN8109.2 August 28, 2009 X28HC64 Power-up Timing Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER Power-up to Read Operation (Note 5) Power-up to Write Operation (Note 5) SYMBOL tPUR tPUW TYP (Note 3) 100 5 UNIT µs ms Capacitance TA = +25°C, f = 1MHz, VCC = 5V PARAMETER SYMBOL CI/O CIN TEST CONDITIONS VI/O = 0V VIN = 0V MAX 10 6 UNIT pF pF Input/output Capacitance (Note 5) Input Capacitance (Note 5) NOTE: 5. This parameter is periodically sampled and not 100% tested. Symbol Table TABLE 2. AC CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 5ns 1.5V WAVEFORM INPUTS Must be steady Ma y change from LO W to HIGH OUTPUTS Will be steady Will change from LO W to HIGH Will change from HIGH to LO W Changing: State Not Known Center Line is High Impedance TABLE 3. MODE SELECTION CE L L H X X OE L H X L X WE H L X X H MODE Read Write Standby and write inhibit Write inhibit Write inhibit I/O DOUT DIN High Z — — POWER Active Active Standby — — Ma y change from HIGH to LO W Don’t Care: Changes Allowed N/A Equivalent AC Load Circuits 5V 1.92kΩ OUTPUT 1.37kΩ 30pF 10 FN8109.2 August 28, 2009 X28HC64 AC Electrical Specifications Read Cycle Limits Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. X28HC64-70 -55°C TO +125°C PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output (Note 6) OE LOW to Active Output (Note 6) CE HIGH to High Z Output (Note 6) OE HIGH to High Z Output (Note 6) Output Hold from Address Change NOTE: 6. tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. SYMBOL tRC tCE tAA tOE tLZ tOLZ tHZ tOHZ tOH 0 0 0 30 30 0 MIN 70 70 70 35 0 0 30 30 0 MAX X28HC64-90 -55°C TO +125°C MIN 90 90 90 40 0 0 30 30 MAX X28HC64-12 -55°C TO +125°C MIN 120 120 120 50 MAX UNIT ns ns ns ns ns ns ns ns ns Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tLZ DATA I/O HIGH Z DATA VALID tAA tOLZ tOH tHZ DATA VALID tOHZ 11 FN8109.2 August 28, 2009 X28HC64 Write Cycle Limits Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER Write Cycle Time (Note 7) Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE High Setup Time OE High Hold Time WE Pulse Width WE HIGH Recovery (Note 8) Data Valid (Note 8) Data Setup Data Hold Delay to Next Write (Note 8) Byte Load Cycle NOTES: 7. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 8. tWPH and tDW are periodically sampled and not 100% tested. SYMBOL tWC tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC 50 0 10 0.15 100 0 50 0 0 50 0 0 50 50 1 MIN TYP (Note 3) 2 MAX 5 UNIT ms ns ns ns ns ns ns ns ns ns µs ns ns µs µs WE Controlled Write Cycle tWC ADDRESS tAS tCS CE tAH tCH OE tOES tWP WE tDV DATA IN tDS DATA OUT HIGH Z DATA VALID tDH tOEH 12 FN8109.2 August 28, 2009 X28HC64 CE Controlled Write Cycle tWC ADDRESS tAS CE tOES OE tOEH tCS WE tDV DATA IN tDS DATA OUT HIGH Z DATA VALID tDH tCH tAH tCW Page Write Cycle OE (NOTE 9) CE tWP WE tWPH tBLC Address (NOTE 10) I/O Byte 0 Byte 1 Byte 2 Byte n Byte n+1 Last Byte Byte n+2 tWC *For each successive write within the page write operation, A6–A12 should be the same or writes to an unknown address could occur. NOTES: 9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 13 FN8109.2 August 28, 2009 X28HC64 DATA Polling Timing Diagram (Note 11) ADDRESS An An An CE WE tOEH tOES OE tDW I/O7 DIN = X DOUT = X tWC DOUT = X Toggle Bit Timing Diagram (Note 11) CE WE tOEH OE tDW I/O*6 HIGH Z * tWC * I/O6 beginning and ending state will vary, depending upon actual tWC. * tOES NOTE: 11. Polling operations are by definition read cycles and are therefore subject to read cycle timings. 14 FN8109.2 August 28, 2009 X28HC64 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP ND N32.45x55 (JEDEC MS-016AE ISSUE A) 0.004 (0.10) C 32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.125 0.060 0.485 0.447 0.188 0.585 0.547 0.238 28 7 9 MAX 0.140 0.095 0.495 0.453 0.223 0.595 0.553 0.273 MILLIMETERS MIN 3.18 1.53 12.32 11.36 4.78 14.86 13.90 6.05 28 7 9 MAX 3.55 2.41 12.57 11.50 5.66 15.11 14.04 6.93 NOTES 3 4, 5 3 4, 5 6 7 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 7. ND denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. NE denotes the number of leads on the two long sides of the package. 0.025 (0.64) R 0.045 (1.14) D2/E2 C L D2/E2 VIEW “A” D D1 D2 E E1 E2 N ND NE E1 E NE D1 D 0.020 (0.51) MAX 3 PLCS 0.050 (1.27) MIN A1 A 0.015 (0.38) MIN SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.025 (0.64) MIN 0.013 (0.33) 0.021 (0.53) (0.12) M A S -B S D S 0.005 VIEW “A” TYP. 15 FN8109.2 August 28, 2009 X28HC64 Small Outline Plastic Packages (SOIC) N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 10.00 0.25 0.40 28 0o MAX 2.65 0.30 0.51 0.32 18.10 7.60 10.65 0.75 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93 MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914 0.394 0.01 0.016 28 0o MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992 0.419 0.029 0.050 8o A1 B C D E e H C α A1 0.10(0.004) 0.05 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 16 FN8109.2 August 28, 2009 X28HC64 Dual-In-Line Plastic Packages (PDIP) N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E E28.6 (JEDEC MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00 eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.600 BSC 0.115 28 0.700 0.200 - 2.54 BSC 15.24 BSC 17.78 5.08 28 2.93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN8109.2 August 28, 2009