X5169

® X5168, X5169 (Replaces X25268, X25169) Data Sheet June 15, 2006 FN8130.2 CPU Supervisor with 16Kbit SPI EEPROM These devices combine three popular functions, Power-on Reset Control, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions by holding RESET/RESET active when VCC falls below a minimum VCC trip point. RESET/RESET remains asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applications requiring higher precision. Features • Low VCC Detection and Reset Assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V • Long Battery Life with Low Power Consumption - 3.3V, IOH = -1.0mA 2V < VCC ≤ 3.3V, IOH = -0.4mA VCC ≤ 2V, IOH = -0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4 V Capacitance SYMBOL COUT (NOTE 2) TA = +25°C, f = 1MHz, VCC = 5V. TEST CONDITIONS VOUT = 0V VIN = 0V MAX. 8 6 UNIT pF pF Output capacitance (SO, RESET/RESET) CIN (NOTE 2) Input capacitance (SCK, SI, CS, WP) NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. 12 FN8130.2 June 15, 2006 X5168, X5169 Equivalent A.C. Load Circuit at 5V VCC 5V 5V A.C. Test Conditions Input pulse levels Input rise and fall times VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 2.06kΩ 4.6kΩ Input and output timing level Output 3.03kΩ 100pF RESET/RESET 30pF AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified.) 2.7-5.5V SYMBOL SERIAL INPUT TIMING fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time PARAMETER MIN MAX UNIT 0 500 250 250 200 200 50 50 2 MHz ns ns ns ns ns ns ns 100 100 500 10 ns ns ns ms 13 FN8130.2 June 15, 2006 X5168, X5169 Serial Input Timing tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG SO High Impedance Serial Output Timing 2.7-5.5V SYMBOL fSCK tDIS tV tHO tRO(3) tFO(3) Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time 0 100 100 PARAMETER MIN 0 MAX 2 250 200 UNIT MHz ns ns ns ns ns Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Serial Output Timing CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG SI ADDR LSB IN 14 FN8130.2 June 15, 2006 X5168, X5169 Power-Up and Power-Down Timing VTRIP 0 Volts tR RESET (X5168) tPURST tPURST tF tRPD VTRIP VCC RESET (X5169) RESET Output Timing SYMBOL VTRIP PARAMETER Reset trip point voltage, X5168-4.5A, X5168-4.5A Reset trip point voltage, X5168, X5169 Reset trip point voltage, X5168-2.7A, X5169-2.7A Reset trip point voltage, X5168-2.7, X5169-2.7 VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC 100 100 1 100 MIN 4.5 4.25 2.85 2.55 TYP 4.63 4.38 2.93 2.63 20 200 280 500 MAX 4.75 4.5 3.0 2.7 UNIT V VTH tPURST tRPD tF (5) mV ms ns µs µs V (5) (5) tR VRVALID Note: (5) This parameter is periodically sampled and not 100% tested. VTRIP Set Conditions tTHD VCC VTRIP tTSU tVPS tP tVPH tRP CS VP SCK VP SI tVPS tVPH tVPO tVPO 15 FN8130.2 June 15, 2006 X5168, X5169 VTRIP Reset Conditions VCC* tVPS tP tVP1 tRP CS tVPS tVPH tVPO SCK VCC VP tVPO SI *VCC > Programmed VTRIP VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C PARAMETER tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv SCK VTRIP program voltage setup time SCK VTRIP program voltage hold time VTRIP program pulse width VTRIP level setup time VTRIP level hold (stable) time VTRIP write cycle time VTRIP program cycle recovery period (between successive programming cycles) SCK VTRIP program voltage off time before next cycle Programming voltage VTRIP programmed voltage range Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C) Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C) VTRIP program voltage repeatability (successive program operations) (programmed at 25°C) VTRIP Program variation after programming (0-75°C). (programmed at 25°C) 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25 DESCRIPTION MIN 1 1 1 10 10 10 MAX UNIT µs µs µs µs ms ms ms ms V V V mV mV mV VTRIP programming parameters are periodically sampled and are not 100% tested. 16 FN8130.2 June 15, 2006 X5168, X5169 Typical Performance VCC Supply Current vs. Temperature (ISB) 18 16 14 10 8 6 4 2 0 -40C Watchdog Timer Off (VCC = 3V, 5V) 25C Temp (°C) 90C Watchdog Timer On (VCC = 5V) Time (ms) 12 Isb (µA) tPURST vs. Temperature 205 Watchdog Timer On (VCC = 5V) 200 195 190 185 180 175 170 165 160 -40 25 Degrees °C 90 VTRIP vs. Temperature (programmed at 25°C) 5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 85 VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V 17 FN8130.2 June 15, 2006 X5168, X5169 Small Outline Package Family (SO) A D N (N/2)+1 h X 45° A E E1 PIN #1 I.D. MARK c SEE DETAIL “X” 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4° ±4° 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150”) 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300”) (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01 18 FN8130.2 June 15, 2006 X5168, X5169 Plastic Dual-In-Line Packages (PDIP) D E N PIN #1 INDEX SEATING PLANE L e b A2 A c E1 A1 NOTE 5 eA eB 1 2 b2 N/2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN ±0.005 ±0.002 +0.010/-0.015 +0.004/-0.002 ±0.010 +0.015/-0.010 ±0.005 Basic Basic ±0.025 ±0.010 Reference Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 2 1 NOTES 19 FN8130.2 June 15, 2006 X5168, X5169 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8130.2 June 15, 2006