X5325S8T1

DATASHEET X5323, X5325 (Replaces X25323, X25325) FN8131 Rev 3.00 December 9, 2015 CPU Supervisor with 32kBit SPI EEPROM These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. Features • Selectable watchdog timer • Low VCC detection and reset assertion - Five standard reset threshold voltages - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V • Determine watchdog or low voltage reset with a volatile flag bit • Long battery life with low power consumption - PROGRAMMED VTRIP VTRIP Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C. PARAMETER DESCRIPTION MIN MAX UNIT tVPS SCK VTRIP Program Voltage Set-up Time 1 µs tVPH SCK VTRIP Program Voltage Hold Time 1 µs VTRIP Program Pulse Width 1 µs tTSU VTRIP Level Set-up Time 10 µs tTHD VTRIP Level Hold (Stable) Time 10 ms tP FN8131 Rev 3.00 December 9, 2015 Page 14 of 19 X5323, X5325 (Replaces X25323, X25325) VTRIP Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C. (Continued) PARAMETER DESCRIPTION MIN MAX UNIT 10 ms tWC VTRIP Write Cycle Time tRP VTRIP Program Cycle Recovery Period (Between Successive Programming Cycles) 10 ms tVPO SCK VTRIP Program Voltage Off-Time Before Next Cycle 0 ms Programming Voltage 15 18 V VTRIP Programed Voltage Range 1.7 5.0 V Vta1 Initial VTRIP Program Voltage Accuracy (VCC Applied-VTRIP) (Programmed at +25°C) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage Accuracy [(VCC Applied-Vta1)-VTRIP] (Programmed at +25°C) -25 +25 mV Vtr VTRIP Program Voltage Repeatability (Successive Program Operations; Programmed at +25°C) -25 +25 mV Vtv VTRIP Program Variation After Programming (0°C to +75°C; Programmed at +25°C) -25 +25 mV 4.5 5.2 VP VTRAN NOTE: 6. VTRIP programming parameters are periodically sampled and are not 100% tested. Typical Performance Curves 18 16 1.8 14 1.7 12 1.6 WATCHDOG TIMER ON (VCC = 5V) 10 RESET (s) ISB (µA) 1.9 WATCHDOG TIMER ON (VCC = 5V) 8 6 -40°C +25°C 1.5 +90°C 1.4 1.3 1.2 4 2 1.1 WATCHDOG TIMER OFF (VCC = 3V, 5V) 0 -40 1.0 25 90 1.7 2.4 TEMPERATURE (°C) FIGURE 11. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1) 0.80 5.025 5.000 3.500 VTRIP = 3.5V 2.475 +25°C 0.65 +90°C 0.60 0.55 2.525 2.500 -40°C 0.70 RESET (s) VOLTAGE (V) 0.75 VTRIP = 5V 3.525 3.475 3.8 VOLTAGE (V) FIGURE 10. VCC SUPPLY CURRENT vs TEMPERATURE (ISB) 4.975 3.1 0.50 VTRIP = 2.5V 0.45 0 25 85 TEMPERATURE (°C) FIGURE 12. VTRIP vs TEMPERATURE (PROGRAMMED AT +25°C) FN8131 Rev 3.00 December 9, 2015 1.7 2.4 3.1 3.8 4.5 5.2 VOLTAGE (V) FIGURE 13. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0) Page 15 of 19 X5323, X5325 (Replaces X25323, X25325) 205 205 200 200 195 195 190 190 RESET (s) TIME (ms) Typical Performance Curves 185 180 175 185 -40°C +25°C +90°C 180 175 170 170 165 165 160 160 -40 25 90 1.7 2.4 FIGURE 14. TPURST vs TEMPERATURE 3.1 3.8 4.5 5.2 VOLTAGE (V) TEMPERATURE (°C) FIGURE 15. TWDO vs VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1) Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION December 9, 2015 FN8131.3 CHANGE Updated Ordering Information Table on page 2. Added Revision History and About Intersil sections. Replaced POD MDP0027 with M8.15E About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN8131 Rev 3.00 December 9, 2015 Page 16 of 19 X5323, X5325 (Replaces X25323, X25325) Plastic Dual-In-Line Packages (PDIP) E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. C 2/07 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. FN8131 Rev 3.00 December 9, 2015 Page 17 of 19 X5323, X5325 (Replaces X25323, X25325) Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN8131 Rev 3.00 December 9, 2015 Page 18 of 19 X5323, X5325 (Replaces X25323, X25325) Thin Shrink Small Outline Plastic Packages (TSSOP) M14.173 N INDEX AREA E 0.25(0.010) M E1 2 SYMBOL 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M L A D -C- e  A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE c 0.10(0.004) C A M B S MIN 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.041 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.195 0.199 4.95 5.05 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N NOTES: MAX  14 0o 14 7 8o Rev. 2 4/06 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8131 Rev 3.00 December 9, 2015 Page 19 of 19