X9251TS24Z

® X9251 Single Supply/Low Power/256-Tap/SPI Bus Data Sheet April 13, 2007 FN8166.5 Quad Digitally-Controlled (XDCP™) Potentiometer The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are imple-mented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Four potentiometers in one package • 256 resistor taps–0.4% resolution • SPI Serial Interface for write, read, and transfer operations of the potentiometer • Wiper resistance: 100Ω typical @ VCC = 5V • 4 Non-volatile data registers for each potentiometer • Non-volatile storage of multiple wiper positions • Standby current VH, VL, and VW. 5. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254. 12 FN8166.5 April 13, 2007 X9251 DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.) LIMITS SYMBOL ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH PARAMETER VCC supply current (active) VCC supply current (non-volatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage IOL = 3mA IOH = -1mA, VCC ≥ +3V IOH = -0.4mA, VCC ≤ +3V VCC - 0.8 VCC - 0.4 TEST CONDITIONS fSCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V VIN = VSS to VCC VOUT = VSS to VCC VCC x 0.7 VCC x 0.3 0.4 1 MIN. TYP MAX 400 5 3 10 10 UNITS μA mA μA μA μA V V V V V Endurance and Data Retention PARAMETER Minimum endurance Data retention MIN 100,000 100 UNITS Data changes per bit per register years Capacitance SYMBOL CIN/OUT (Note 6) Input/Output capacitance (SI) COUT (Note 6) CIN (Note 6) Output capacitance (SO) Input capacitance (A0, A1, CS, WP, HOLD, and SCK) TEST TEST CONDITIONS VOUT = 0V VOUT = 0V VIN = 0V TYP 8 8 6 UNITS pF pF pF Power-Up Timing SYMBOL tr VCC (Note 6) tPUR (Note 7) tPUW (Note 7) VCC Power-up rate Power-up to initiation of read operation Power-up to initiation of write operation PARAMETER MIN 0.2 1 50 MAX UNITS V/ms ms ms A.C. Test Conditions Input Pulse Levels Input rise and fall times Input and output timing level NOTES: 6. This parameter is not 100% tested 7. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 13 FN8166.5 April 13, 2007 X9251 Equivalent A.C. Load Circuit VCC 2kΩ RH SO pin 2kΩ 10pF 10pF RW CL CW 25pF CL 10pF SPICE Macromodel RTOTAL RL AC TIMING SYMBOL fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO (Note 6) tFO (Note 6) tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SPI clock frequency SPI clock cycle rime SPI clock high rime SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 setup time WP, A0 hold time 2 0 0 400 100 100 100 100 10 0 100 100 0 500 200 200 250 250 50 50 2 2 250 200 PARAMETER MIN MAX 2 UNITS MHz ns ns ns ns ns ns ns μs μs ns ns ns ns ns ns ns ns ns ns ns μs ns ns High-Voltage Write Cycle Timing SYMBOL tWR PARAMETER High-voltage write cycle time (store instructions) TYP 5 MAX 10 UNITS ms XDCP Timing SYMBOL tWRPO (Note 6) tWRL (Note 6) PARAMETER Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) MIN 5 5 MAX 10 10 UNITS μs μs 14 FN8166.5 April 13, 2007 X9251 Symbol Table WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance Timing Diagrams Input Timing tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG tFI LSB tRI SO HIGH IMPEDANCE Output Timing CS SCK tV SO MSB tHO ... tDIS ... LSB SI ADDR 15 FN8166.5 April 13, 2007 X9251 Hold Timing CS tHSU SCK tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH ... XDCP Timing (for All Load Instructions) CS SCK ... tWRL ... LSB SI MSB VWx SO HIGH IMPEDANCE Write Protect and Device Address Pins Timing CS tWPASU WP A0 A1 (ANY INSTRUCTION) tWPAH 16 FN8166.5 April 13, 2007 X9251 Applications information Basic Configurations of Electronic Potentiometers VR +VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits NON INVERTING AMPLIFIER VS + – VO VIN 317 R1 R2 R1 Iadj R2 VO (REG) VOLTAGE REGULATOR VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 OFFSET VOLTAGE ADJUSTMENT R1 VS 100kΩ – + TL072 10kΩ 10kΩ +12V 10kΩ -12V VO R2 COMPARATOR WITH HYSTERESIS VS – + VO VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) } R1 } R2 17 FN8166.5 April 13, 2007 X9251 Application Circuits (continued) ATTENUATOR C R1 VS R3 R4 R1 = R2 = R3 = R4 = 10kΩ R1 R2 – + VO VS R R2 + – VO FILTER VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) INVERTING AMPLIFIER R1 R2 EQUIVALENT L-R CIRCUIT } VS } – + C1 VO VS R2 + – VO = G VS G = - R2/R1 ZIN R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FUNCTION GENERATOR C – + R2 R1 – + } RA } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 18 FN8166.5 April 13, 2007 X9251 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8° Rev. 1 4/06 MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914 MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992 A1 B C D E α A1 0.10(0.004) C e H h L N 0.05 BSC 0.394 0.010 0.016 24 0° 8° 0.419 0.029 0.050 1.27 BSC 10.00 0.25 0.40 24 0° 10.65 0.75 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 19 FN8166.5 April 13, 2007 X9251 Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D N (N/2)+1 A MDP0044 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. A A1 A2 b c D E E1 e H 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00 1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00 Max ±0.05 ±0.05 +0.05/-0.06 +0.05/-0.06 ±0.10 Basic ±0.10 Basic ±0.15 Reference Rev. F 2/07 E E1 1 B TOP VIEW (N/2) 0.20 C B A 2X N/2 LEAD TIPS C SEATING PLANE e 0.05 L L1 NOTES: b 0.10 C N LEADS SIDE VIEW 0.10 M C A B 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL “X” c END VIEW L1 A A2 GAUGE PLANE 0.25 A1 DETAIL X L 0° - 8° All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8166.5 April 13, 2007