X9258

® X9258 Low Noise/Low Power/2-Wire Bus/256 Taps Data Sheet May 6, 2005 FN8168.1 Quad Digital Controlled Potentiometers (XDCP™) FEATURES • • • • • • • • Four potentiometers in one package 256 resistor taps/pot–0.4% resolution 2-wire serial interface Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V Four nonvolatile data registers for each pot Nonvolatile storage of wiper position Standby current < 5µA max (total package) Power supplies —VCC = 2.7V to 5.5V —V+ = 2.7V to 5.5V —V- = -2.7V to -5.5V 100kΩ, 50kΩ total pot resistance High reliability —Endurance – 100,000 data changes per bit per register —Register data retention – 100 years 24-lead SOIC, 24-lead TSSOP Dual supply version of X9259 DESCRIPTION The X9258 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • • • • BLOCK DIAGRAM VCC VSS V+ VWP SCL SDA A0 A1 A2 A3 R2 R3 R0 R1 Wiper Counter Register (WCR) Pot 0 VH0/RH0 R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 2 VH2/RH2 VL0/RL0 VW0/RW0 R2 R3 VL2/RL2 VW2/RW2 Interface and Control Circuitry 8 Data R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 1 VW1/RW1 VH1/RH1 R0 R1 Wiper Counter Register (WCR) VW3/RW3 Resistor Array Pot 3 VH3/RH3 R2 R3 VL1/RL1 R2 R3 VL3/RL3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9258 PIN DESCRIPTIONS Host Interface Pins SERIAL CLOCK (SCL) The SCL input is used to clock data into and out of the X9258. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVICE ADDRESS (A0 - A3) The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9258. A maximum of 16 devices may occupy the 2-wire serial bus. Potentiometer Pins VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 VL3/RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0 - VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. PIN NAMES Symbol SCL SDA A0-A3 VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 VW0/RW0 - VW3/RW3 WP V+,VVCC VSS NC NC A0 VW3/RW3 VH3/RH3 VL3/RL3 V+ VCC VL0/RL0 VH0/RH0 VW0/RW0 A2 WP PIN CONFIGURATION SOIC/TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 X9258 24 23 22 21 20 19 18 17 16 15 14 13 A3 SCL VL2/RL2 VH2/RH2 VW2/RW2 V– VSS VW1/RW1 VH1/RH1 VL1/RL1 A1 SDA Description Serial Clock Serial Data Device Address Potentiometer Pins (terminal equivalent) Potentiometers Pins (wiper equivalent) Hardware Write Protection Analog Supplies System Supply Voltage System Ground No Connection (Allowed) PRINCIPLES OF OPERATION Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for the DCP analog section. The X9258 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the DCP potentiometers. Serial Interface—2-Wire The X9258 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers 2 FN8168.1 May 6, 2005 X9258 and provide the clock for both transmit and receive operations. Therefore, the X9258 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9258 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9258 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9258 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9258 will respond with a final acknowledge. Array Description The X9258 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 8 bits of the WCR are decoded to select, and enable, one of 256 switches. Device Address The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9258 this is fixed as 0101[B]. Figure 1. Slave Address Device Type Identifier 0 1 0 1 A3 A2 A1 A0 The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0 - A3 inputs. The X9258 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9258 to respond with an acknowledge. The A0 - A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9258 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9258 is still busy with the write operation no ACK will be returned. If the X9258 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. 3 FN8168.1 May 6, 2005 X9258 ACK Polling Sequence Nonvolatile Write Command Completed EnterACK Polling Issue START Issue Slave Address Issue STOP ACK Returned? Yes Further Operation? No Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9258; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected data register). The sequence of operations is shown in Figure 4. No Yes Issue Instruction Issue STOP Proceed Proceed Instruction Structure The next byte sent to the X9258 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the two pots and when applicable they point to one of four associated registers. The format is shown below in Figure 2. Figure 2. Instruction Byte Format Register Select I3 I2 I1 I0 R1 R0 P1 P0 Instructions Wiper Counter Register Select The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select which one of the four potentiometers is to be affected by the instruction. 4 FN8168.1 May 6, 2005 X9258 Figure 3. Two-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K S T O P The Increment/Decrement command is different from the other commands. Once the command is issued and the X9258 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH terminal. Table 1. Instruction Set Instruction Set Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register Note: Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. I3 1 1 1 1 1 I2 0 0 0 1 1 I1 0 1 1 0 0 I0 1 0 1 0 1 R1 0 0 1/0 1/0 1/0 R0 0 0 1/0 1/0 1/0 P1 1/0 1/0 1/0 1/0 1/0 P0 1/0 1/0 1/0 1/0 1/0 Operation Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read the contents of the Data Register pointed to by P1 - P0 and R1 - R0 Write new value to the Data Register pointed to by P1 - P0 and R1 - R0 Transfer the contents of the Data Register pointed to by P1 - P0 and R1 - R0 to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Data Register pointed to by R1 - R0 Transfer the contents of the Data Registers pointed to by R1 - R0 of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by R1 - R0 of all four pots Enable Increment/decrement of the Control Latch pointed to by P1 - P0 1 1 1 0 1/0 1/0 1/0 1/0 0 0 0 1 1/0 1/0 0 0 1 0 0 0 1/0 1/0 0 0 0 0 1 0 0 0 1/0 1/0 (1) 1/0 = data is one or zero 5 FN8168.1 May 6, 2005 X9258 Figure 4. Three-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K D7 D6 D5 D4 D3 D2 D1 D0 A C K S T O P Figure 5. Increment/Decrement Instruction Sequence F SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P Figure 6. Increment/Decrement Timing Limits INC/DEC CMD Issued SCL tWRID SDA VW/RW Voltage Out 6 FN8168.1 May 6, 2005 X9258 Figure 7. Acknowledge Response from Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver START Acknowledge Figure 8. Detailed Potentiometer Block Diagram Detailed Operation Serial Data Path From Interface Circuitry Register 0 8 Register 1 8 Serial BUS Input C o u n t e r D e c o d e VH/RH Parallel BUS Input Wiper Counter Register (WCR) Register 2 Register 3 If WCR = 00[H] then VW/RW = VL/RL If WCR = FF[H] then VW/RW = VH/RH INC/DEC Logic UP/DN Modified SCL UP/DN CLK VL/RL VW/RW All DCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9258 contains four Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select 7 one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. FN8168.1 May 6, 2005 X9258 The WCR is a volatile register; that is, its contents are lost when the X9258 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Instruction Format Notes: (1) (2) (3) (4) (5) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. “A3 ~ A0”: stands for the device addresses sent by the master. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. “I”: stands for the increment operation, SDA held high during active SCL phase (high). “D”: stands for the decrement operation, SDA held low during active SCL phase (high). REGISTER DESCRIPTIONS Data Registers, (8-Bit), Nonvolatile WP7 NV (MSB) WP6 WP5 WP4 WP3 WP2 WP1 NV NV NV NV NV NV WP0 NV (LSB) Four 8-bit Data Registers for each DCP. (sixteen 8-bit registers in total). – {D7~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the wiper counter register on power-up. Wiper Counter Register, (8-Bit), Volatile WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 Read Wiper Counter Register (WCR) S device type device T identifier addresses A R0101AAAA 3210 T instruction WCR S opcode addresses A C PP K10010010 wiper position S (sent by slave on SDA) A CWWWWWWWW KPPPPPPPP 76543210 M A C K S T O P Write Wiper Counter Register (WCR) S device type device T identifier addresses A R0101AAAA 3210 T instruction WCR S opcode addresses A C PP K10100010 Data Byte S (sent by master on SDA) A CWWWWWWWW KPPPPPPPP 76543210 S A C K S T O P Read Data Register (DR) S device type device T identifier addresses A R0101AAAA 3210 T instruction DR and WCR S opcode addresses A C RRPP K10111010 Data Byte S (sent by slave on SDA) A CWWWWWWWW KPPPPPPPP 76543210 M A C K S T O P 8 FN8168.1 May 6, 2005 X9258 Write Data Register (WR) S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C RRPP R0101AAAA 1100 3210K 1010 T Data Byte S (sent by master on SDA) A C WWWWWWWW PPPPPPPP K 76543210 S A C K S T HIGH-VOLTAGE O WRITE CYCLE P XFR Data Register (DR) to Wiper Counter Register (WCR) S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C RRPP R0101AAAA 1101 3210K 1010 T S A C K S T O P XFR Wiper Counter Register (WCR) to Data Register (DR) S device type device T identifier addresses A R0101AAAA 3210 T instruction DR and WCR S opcode addresses A C RRPP 1110 K 1010 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Increment/Decrement Wiper Counter Register (WCR) S device type device T identifier addresses A R0101AAAA 3210 T instruction S opcode A C K0010 WCR addresses 0 0 P 1 increment/decrement S (sent by master on SDA) A P C I/ I/ I/ I/ .... 0KDD DD S T O P Global XFR Data Register (DR) to Wiper Counter Register (WCR) S device type device T identifier addresses A R0101AAAA 3210 T instruction DR S opcode addresses A C RR K00011000 S A C K S T O P Global XFR Wiper Counter Register (WCR) to Data Register (DR) S device type device T identifier addresses A R0101AAAA 3210 T instruction DR S opcode addresses A C RR 1000 00 K 10 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 9 FN8168.1 May 6, 2005 X9258 SYMBOL TABLE Guidelines for Calculating Typical Values of Bus Pull-Up Resistors INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance 120 100 Resistance (K) 80 60 40 20 0 0 Min. Resistance 20 40 60 80 100 120 RMIN = VCC MAX =1.8kΩ IOL MIN tR CBUS WAVEFORM RMAX = Max. Resistance Bus Capacitance (pF) 10 FN8168.1 May 6, 2005 X9258 ABSOLUTE MAXIMUM RATINGS Temperature under bias..................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on SDA, SCL or any address input with respect to VSS ................................. -1V to +7V Voltage on V+ (referenced to VSS) ........................ 10V Voltage on V- (referenced to VSS) ........................-10V (V+) - (V-)............................................................... 12V Any VH/RH...............................................................V+ Any VL/RL................................................................. VLead temperature (soldering, 10 seconds)........ 300°C IW (10 seconds)................................................±15mA COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0°C -40°C Max. +70°C +85°C Device X9258 X9258-2.7 Supply Voltage (VCC) Limits 5V ± 10% 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter End to end resistance tolerance Power rating IW RW RW V+ VVTERM Wiper current Wiper resistance Wiper resistance Voltage on V+ Pin Voltage on V- Pin X9258 X9258-2.7 X9258 X9258 -2.7 Voltage on any VH/RH or VL/RL pin Noise Resolution (4) Absolute linearity (1) Relative linearity (2) Temperature coefficient of RTOTAL Ratiometric Temperature Coefficient CH/CL/CW Potentiometer Capacitance 10/10/25 ±300 ±20 +4.5 +2.7 -5.5 -5.5 V-120 0.6 ±1 ±0.6 150 40 Min. Typ. Max. ±20 50 ±7.5 250 100 +5.5 +5.5 -4.5 -2.7 V+ Unit % mW mA Ω Ω V V V dBV % MI(3) MI(3) ppm/°C ppm/°C pF Test Conditions 25°C, each pot Wiper current = ± 1mA IW = ± 1mA @ V+ = 3V, V- = -3V IW = ± 1mA @ V+ = 5V, V- = -5V Ref: 1kHz Vw(n)(actual) - Vw(n)(expected) Vw(n + 1) - [Vw(n) + MI] See Circuit #3 11 FN8168.1 May 6, 2005 X9258 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol ICC1 ICC2 ISB ILI ILO VIH VIL VOL Parameter VCC supply current (Nonvolatile Write) VCC supply current (move wiper, write, read) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Min. Typ. 1 Max. Unit mA Test Conditions fSCL = 400kHz, SDA = Open, Other Inputs = VSS fSCL = 400kHz, SDA = Open, Other Inputs = VSS SCL = SDA = VCC, Addr. = VSS VIN = VSS to VCC VOUT = VSS to VCC 100 5 10 10 VCC x 0.7 -0.5 VCC + 0.1 VCC x 0.3 0.4 µA µA µA µA V V V IOL = 3mA Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/255 or (VH/RH—VL/RL)/255, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions. ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention Min. 100,000 100 Unit Data changes per bit per register years CAPACITANCE Symbol CI/O (5) Test Input/output capacitance (SDA) Input capacitance (A0, A1, A2, A3, and SCL) Max. 8 6 Unit pF pF Test Conditions VI/O = 0V VIN = 0V CIN(5) POWER-UP TIMING Symbol tPUR (6) (6) Parameter Power-up to initiation of read operation Power-up to initiation of write operation VCC Power up ramp Min. Max. 1 5 Unit ms ms V/msec tPUW tR VCC(7) 0.2 50 POWER UP AND DOWN REQUIREMENT The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The VCC ramp rate spec is always in effect. Notes: (5) This parameter is periodically sampled and not 100% tested. (6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (7) Sample tested only. 12 FN8168.1 May 6, 2005 X9258 A.C. TEST CONDITIONS Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 RH CH 2.7V 1533Ω SDA Output 100pF 100pF CW 25pF RW Test Circuit #3 SPICE Macro Model Macro Model RTOTAL CL 10pF RL EQUIVALENT A.C. LOAD CIRCUIT 5V 10pF AC TIMING (Over recommended operating condition) Symbol fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF tAA tDH TI tBUF tSU:WPA tHD:WPA Clock frequency Clock cycle time Clock high time Clock low time Start setup time Start hold time Stop setup time SDA data input setup time SDA data input hold time SCL and SDA rise time SCL and SDA fall time SCL low to SDA data output valid time SDA data output hold time Noise suppression time constant at SCL and SDA inputs Bus free rime (prior to any transmission) WP, A0, A1, A2 and A3 setup time WP, A0, A1, A2 and A3 hold time 50 50 1300 0 0 2500 600 1300 600 600 600 100 30 300 300 900 Parameter Min. Max. 400 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns HIGH-VOLTAGE WRITE CYCLE TIMING Symbol tWR Parameter High-voltage write cycle time (store instructions) Typ. 5 Max. 10 Unit ms 13 FN8168.1 May 6, 2005 X9258 DCP TIMING Symbol tWRPO tWRL tWRID Note: Parameter Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) Wiper response time from an active SCL/SCK edge (increment/decrement instruction) Min. Max. 10 10 10 Unit µs µs µs (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. TIMING DIAGRAMS 2-WIRE INTERFACE START and STOP Timing (START) tR SCL tSU:STA tHD:STA tR SDA tF tSU:STO tF (STOP) Input Timing tCYC SCL tHIGH tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA tDH 14 FN8168.1 May 6, 2005 X9258 DCP Timing (for All Load Instructions) (STOP) SCL SDA LSB tWRL VWx DCP Timing (for Increment/Decrement Instruction) SCL SDA Wiper Register Address Inc/Dec tWRID Inc/Dec VWx Write Protect and Device Address Pins Timing (START) SCL (STOP) ... (Any Instruction) ... SDA tSU:WPA WP A0, A1 A2, A3 ... tHD:WPA 15 FN8168.1 May 6, 2005 X9258 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers VR +VR VW/RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS + – VO VIN 317 R1 R2 R1 VO (REG) Voltage Regulator Iadj R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment Comparator with Hysteresis R1 VS 100kΩ – + R2 VS – + VO VO } } TL072 10kΩ 10kΩ +12V 10kΩ -12V R1 R2 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 16 FN8168.1 May 6, 2005 X9258 Application Circuits (continued) Attenuator C VS R1 – VS R3 R4 All RS = 10kΩ + VO R2 R Filter + – VO R2 R1 VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) Inverting Amplifier R1 R2 Equivalent L-R Circuit } VS } – + VO C1 VS R2 + – VO = G VS G = - R2/R1 ZIN R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C – + R2 R1 – + } RA } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 17 FN8168.1 May 6, 2005 X9258 PACKAGING INFORMATION 24-Lead Plastic, TSSOP, Package Code V24 .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.06) .005 (.15) .010 (.25) Gage Plane 0° - 8° .020 (.50) .030 (.75) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) See Detail “A” ALL MEASUREMENTS ARE TYPICAL Seating Plane (1.78) (4.16) (7.72) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 18 FN8168.1 May 6, 2005 X9258 PACKAGING INFORMATION 24-Lead Plastic Small Outline Gull Wing Package Type S 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0.009 (0.22) 0.013 (0.33) 0.015 (0.40) 0.050 (1.27) 0.420" 0° - 8° FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 19 FN8168.1 May 6, 2005 X9258 Ordering Information X9258 Device Y P T V VCC Limits Blank = 5V ±10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package S24 = 24-Lead SOIC V24 = 24-Lead TSSOP Potentiometer Organization T = 100KΩ U= 50kΩ S & V Package Marking Line #1 Line #2 Line #3 Line #4 (Blank) (Part Number) (Date Code) (*) (Blank) = F 2.7V 0 to 70°C G 2.7V -40 to +85°C I 5V -40 to +85°C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN8168.1 May 6, 2005