X9269TV24-2.7

® X9269 Single Supply/Low Power/256-Tap/2-Wire Bus Data Sheet March 28, 2005 FN8173.1 Dual Digitally-Controlled (XDCP™) Potentiometers FEATURES • Dual–Two separate potentiometers • 256 resistor taps/pot–0.4% resolution • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer single supply device • Wiper Resistance, 100Ω typical VCC = 5V • 4 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on Power-up. • Standby Current < 5µA Max • 50kΩ, 100kΩ versions of End to End Pot Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 24-Lead SOIC, 24-Lead TSSOP • Low Power CMOS • Power Supply VCC = 2.7V to 5.5V DESCRIPTION The X9269 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-Wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default Data Register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM VCC RH0 RH1 2-Wire Bus Interface Address Data Status Write Read Transfer Inc/Dec Bus Interface and Control Control Power-on Recall Wiper Counter Registers (WCR) Data Registers (DR0–DR3) VSS RW0 RL0 RW1 RL1 50kΩ or 100kΩ versions 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9269 DETAILED FUNCTIONAL DIAGRAM RH0 RL0 RW0 VCC Power-on Recall R0 R1 Wiper Counter Register (WCR) Pot 0 SCL SDA A3 A2 A1 A0 WP INTERFACE AND CONTROL CIRCUITRY R2 R3 50kΩ and 100kΩ 256-taps 8 Data Power-on Recall R0 R1 Wiper Counter Register (WCR) Resistor Array Pot 1 R2 R3 VSS RL1 RH1 RW1 CIRCUIT LEVEL APPLICATIONS • Vary the gain of a voltage amplifier • Provide programmable dc reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the dc biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems 2 FN8173.1 March 28, 2005 X9269 PIN CONFIGURATION SOIC/TSSOP NC A0 NC NC NC NC VCC RL0 RH0 RW0 A2 WP 1 2 3 4 5 6 7 8 9 10 11 12 X9269 24 23 22 21 20 19 18 17 16 15 14 13 A3 SCL NC NC NC NC VSS RW1 RH1 RL1 A1 SDA PIN ASSIGNMENTS Pin (SOIC/TSSOP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol NC A0 NC NC NC NC VCC RL0 RH0 RW0 A2 WP SDA A1 RL1 RH1 RW1 VSS NC NC NC NC SCL A3 No Connect Device Address for 2-Wire bus. No Connect No Connect No Connect No Connect System Supply Voltage Low Terminal for Potentiometer 0. High Terminal for Potentiometer 0. Wiper Terminal for Potentiometer 0. Device Address for 2-Wire bus. Hardware Write Protect Function Serial Data Input/Output for 2-Wire bus. Device Address for 2-Wire bus. Low Terminal for Potentiometer 1. High Terminal for Potentiometer 1. Wiper Terminal for Potentiometer 1. System Ground No Connect No Connect No Connect No Connect Serial Clock for 2-Wire bus. Device Address for 2-Wire bus. 3 FN8173.1 March 28, 2005 X9269 PIN DESCRIPTIONS Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9269. DEVICE ADDRESS (A3 - A0) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9269. A maximum of 16 devices may occupy the 2-Wire serial bus. NO CONNECT No connect pins should be left open. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RH and RL such that RH0 and RL0 are the terminals of POT 0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 2 sets of RW such that RW0 is the terminal of POT 0 and so on. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins 4 FN8173.1 March 28, 2005 X9269 PRINCIPLES OF OPERATION The X9269 is a integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: – Resistor Array Description – Serial Interface Description – Instruction and Register Description. Array Description The X9269 is comprised of a resistor array (See Figure 1). Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (See Table 1). The WCR may be written directly. These Data Registers can the WCR can be read and written by the host system. Power-up and Down Requirements. There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate specification is always in effect. Figure 1. Detailed Potentiometer Block Diagram One of Two Potentiometers SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) 8 REGISTER 1 (DR1) 8 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) INC/DEC LOGIC UP/DN MODIFIED SCL UP/DN CLK RL SERIAL BUS INPUT C O U N T E R D E C O D E RH REGISTER 2 (DR2) REGISTER 3 (DR3) IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH RW 5 FN8173.1 March 28, 2005 X9269 SERIAL INTERFACE DESCRIPTION Serial Interface The X9269 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9269 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 2. Start Condition All commands to the X9269 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9269 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. See Figure 2. Figure 2. Acknowledge Response from Receiver Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 2. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9269 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9269 will respond with a final acknowledge. See Figure 2. SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 6 FN8173.1 March 28, 2005 X9269 Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9269 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9269 is still busy with the write operation no ACK will be returned. If the X9269 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. FLOW 1: ACK Polling Sequence Nonvolatile Write Command Completed EnterACK Polling INSTRUCTION AND REGISTER DESCRIPTION Instructions DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A) The first byte sent to the X9269 from the host is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9269; this is fixed as 0101[B] (refer to Table 1). The A[3:0] bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A3-A0 input pins. The slave address is externally specified by the user. The X9269 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9269 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I) Issue START Issue Slave Address Issue STOP ACK Returned? Yes No The next byte sent to the X9269 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode I [3:0]. The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least significant bit points to one of two Wiper Counter Registers or Pots. The format is shown in Table 2. Further Operation? Yes Issue Instruction No Register Selection Register Selected Issue STOP RB 0 0 1 1 RA 0 1 0 1 DR0 DR1 DR2 Proceed Proceed DR3 7 FN8173.1 March 28, 2005 X9269 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 0 (MSB) ID2 1 ID1 0 ID0 1 A3 A2 A1 A0 (LSB) Table 2. Instruction Byte Format Instruction Opcode Register Selection Pot Selection (WCR Selection) I3 (MSB) I2 I1 I0 RB RA 0 P0 (LSB) Table 3. Instruction Set Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Global XFR Data Registers to Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register Increment/Decrement Wiper Counter Register I3 1 1 1 1 1 I2 0 0 0 1 1 Instruction Set I1 I0 RB RA 0 1 0 0 1 1 0 0 0 1 0 1 0 1/0 1/0 1/0 0 1/0 1/0 1/0 0 0 0 0 0 0 P0 1/0 1/0 1/0 1/0 1/0 Operation Read the contents of the Wiper Counter Register pointed to by P0 Write new value to the Wiper Counter Register pointed to by P0 Read the contents of the Data Register pointed to by P0 and RB - RA Write new value to the Data Register pointed to by P0 and RB - RA Transfer the contents of the Data Register pointed to by P0 and RB - RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P0 to the Data Register pointed to by RB - RA Transfer the contents of the Data Registers pointed to by RB - RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB - RA of all four pots Enable Increment/decrement of the Control Latch pointed to by P0 1 1 1 0 1/0 1/0 0 1/0 0 0 0 1 1/0 1/0 0 0 1 0 0 0 1/0 1/0 0 0 0 0 1 0 0 0 0 1/0 Note: 1/0 = data is one or zero 8 FN8173.1 March 28, 2005 X9269 DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9269 contains two Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (See Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9269 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR (See Design Considerations Section). Data Registers (DR) Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit [7:0] are used to store one of the 256 wiper positions (0~255). Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). WCR7 V (MSB) WCR6 V WCR5 V WCR4 V WCR3 V WCR2 V WCR1 V WCR0 V (LSB) Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 NV MSB NV NV NV NV NV NV Bit 0 NV LSB 9 FN8173.1 March 28, 2005 X9269 DEVICE DESCRIPTION Instructions Four of the nine instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the selected potentiometer, – Write Wiper Counter Register – change current wiper position of the selected potentiometer, – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. The basic sequence of the three byte instructions is illustrated in Figure 4. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9269; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register – This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 6). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9269 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instruction format for more details. 10 FN8173.1 March 28, 2005 X9269 Figure 3. Two-Byte Instruction Sequence SCL SDA 0 1 0 1 A I3 C K I2 I1 I0 RB RA 0 Register Address A C K Pot/WCR Address P0 S T O P S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A External R Device ID Address T Instruction Opcode Figure 4. Three-Byte Instruction Sequence SCL SDA 0 1 0 1 A2 A0 A I3 C K External Address A1 I2 I1 I0 0 RB RA 0 P0 A C K Register Pot/WCR Address Address D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] A C K S T O P S ID3 ID2 ID1 ID0 A3 T A Device ID R T Instruction Opcode Figure 5. Increment/Decrement Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 External Address A C K I3 I2 I1 I0 0 A C Register Pot/WCR K Address Address RB RA 0 P0 I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P ID3 ID2 ID1 ID0 Device ID Instruction Opcode Figure 6. Increment/Decrement Timing Limits INC/DEC CMD Issued SCL tWRID SDA RW Voltage Out 11 FN8173.1 March 28, 2005 X9269 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 0 1 0 0 0 P0 S A C K Wiper Position (Sent by X9269 on SDA) M WWWWWWWWA CCCCCCCCC RRRRRRRRK 76543210 S T O P Write Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 0 0 0 0 P0 S A C K Wiper Position (Sent by Master on SDA) S WWWWWWWWA CCCCCCCCC RRRRRRRRK 76543210 S T O P Read Data Register (DR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 1 RB RA 0 P0 S A C K Wiper Position (Sent by X9269 on SDA) M WWWWWWWWA CCCCCCCCC RRRRRRRRK 76543210 S T O P Write Data Register (DR) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE FN8173.1 March 28, 2005 Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 1 0 0 RB RA 0 P0 K Wiper Position (Sent by Master on SDA) S WWWWWWWWA CCCCCCCCC RRRRRRRRK 76543210 Global XFR Data Register (DR) to Wiper Counter Register (WCR) S T A R T Device Type Identifier 0 1 0 Instruction DR/WCR S Opcode Addresses A C 1 A3 A2 A1 A0 K 0 0 0 1 RB RA 0 0 Device Addresses S A C K S T O P 12 X9269 Global XFR Wiper Counter Register (WCR) to Data Register (DR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 0 0 0 RB RA 0 0 K S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Wiper Counter Register (WCR) to Data Register (DR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 1 1 0 RB RA 0 P0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 1 0 1 RB RA 0 P0 S A C K S T O P Increment/Decrement Wiper Counter Register (WCR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C P0 K001000 0 Increment/Decrement S (Sent by Master on SDA) A C K I/D I/D . . . . I/D I/D S T O P Notes: (1) (2) (3) (4) (5) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. “A3 ~ A0”: stands for the device addresses sent by the master. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. “I”: stands for the increment operation, SDA held high during active SCL phase (high). “D”: stands for the decrement operation, SDA held low during active SCL phase (high). 13 FN8173.1 March 28, 2005 X9269 ABSOLUTE MAXIMUM RATINGS Temperature under bias..................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on SCL, SDA any address input with respect to VSS ................................. -1V to +7V ∆V = | (VH - VL) | ................................................... 5.5V Lead temperature (soldering, 10 seconds)........ 300°C IW (10 seconds) .................................................±6mA COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0°C -40°C Max. +70°C +85°C Device X9261 X9261-2.7 Supply Voltage (VCC)(4) Limits 5V ± 10% 2.7V to 5.5V POTENTIOMETER CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.) Limits Symbol RTOTAL RTOTAL Parameter End to End Resistance End to End Resistance End to End Resistance Tolerance Power Rating Min. Typ. 100 50 Max. Units kΩ kΩ Test Conditions T version U version ±20 50 ±3 300 150 VSS -120 0.4 ±1 ±0.6 ±300 20 10/10/25 0.1 10.0 VCC % mW mA Ω Ω V dBV % MI(3) MI(3) ppm/°C ppm/°C pF µA See Macro model Device in stand by. Vin = VSS to VCC Rw(n)(actual) - Rw(n)(expected)(5) Rw(n + 1) - [Rw(n) + MI](5) IW = ± 3mA @ VCC = 3V IW = ± 3mA @ VCC = 5V VSS = 0V Ref: 1V 25°C, each pot IW RW RW VTERM Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity (1) Relative Linearity (2) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW Ial Potentiometer Capacitances RW, RH, RL Leakage Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power-up VCC > VH, VL, and VW. (5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254. 14 FN8173.1 March 28, 2005 X9269 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol ICC1 Parameter VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage curInput HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Min. Typ. Max. 400 Units µA Test Conditions fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) fSCL = 400kHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) VCC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) VIN = VSS to VCC VOUT = VSS to VCC ICC2 1 5 mA ISB ILI ILO VIH VIL VOL VOH VOH 5 10 10 VCC x 0.7 -1 VCC - 0.8 VCC - 0.4 VCC + 1 VCC x 0.3 0.4 µA µA µA V V V V V IOL = 3mA IOH = -1mA, VCC ≥ +3V IOH = -0.4mA, VCC ≤ +3V ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention Min. 100,000 100 Units Data changes per bit per register years CAPACITANCE Symbol CIN/OUT CIN(6) (6) Test Input / Output capacitance (SDA) Input capacitance (SCL, WP, A3, A2, A1 and A0) Max. 8 6 Units pF pF Test Conditions VOUT = 0V VIN = 0V POWER-UP TIMING Symbol tr VCC tPUR (6) (7) Parameter VCC Power-up rate Power-up to initiation of read operation Min. 0.2 Max. 50 1 Units V/ms ms POWER-UP AND DOWN REQUIREMENTS The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC power-up timing spec is always in effect. A.C. TEST CONDITIONS Input Pulse Levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. 15 FN8173.1 March 28, 2005 X9269 EQUIVALENT A.C. LOAD CIRCUIT 5V 1533 Ω SDA pin 100pF SDA pin CL 100pF 10pF RW 3V 867Ω RH CW 25pF CL 10pF SPICE Macromodel RTOTAL RL AC TIMING Symbol fSCL tCYC tHIGH tLOW tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tF tAA tDH TI tBUF tSU:WPA tHD:WPA Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Start Setup Time Start Hold Time Stop Setup Time SDA Data Input Setup Time SDA Data Input Hold Time SCL and SDA Rise Time SCL and SDA Fall Time SCL Low to SDA Data Output Valid Time SDA Data Output Hold Time Noise Suppression Time Constant at SCL and SDA inputs Bus Free Time (Prior to Any Transmission) A0, A1, A2, A3 Setup Time A0, A1, A2, A3 Hold Time 0 50 1200 0 0 2500 600 1300 600 600 600 100 30 300 300 0.9 Parameter Min. Max. 400 Units kHz ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns 16 FN8173.1 March 28, 2005 X9269 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol tWR Parameter High-voltage write cycle time (store instructions) Typ. 5 Max. 10 Units ms XDCP TIMING Symbol tWRPO tWRL Parameter Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) Min. 5 5 Max. Units 10 10 µs µs SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance 17 FN8173.1 March 28, 2005 X9269 TIMING DIAGRAMS Start and Stop Timing (START) tR SCL tSU:STA tHD:STA tR SDA tF tSU:STO tF (STOP) Input Timing tCYC SCL tLOW SDA tSU:DAT tHD:DAT tBUF tHIGH Output Timing SCL SDA tAA tDH 18 FN8173.1 March 28, 2005 X9269 XDCP Timing (for All Load Instructions) (STOP) SCL SDA LSB tWRL VWx Write Protect and Device Address Pins Timing (START) SCL ... (Any Instruction) ... SDA tSU:WPA WP A0, A1 ... tHD:WPA (STOP) 19 FN8173.1 March 28, 2005 X9269 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers VR +VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS + – VO VIN 317 R1 R2 R1 VO (REG) Voltage Regulator Iadj R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 VS 100kΩ – + 10kΩ 10kΩ +12V 10kΩ -12V TL072 10kΩ VCC 10kΩ VO R2 Comparator with Hysterisis VS – + VO VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) } R1 } R2 20 FN8173.1 March 28, 2005 X9269 Application Circuits (continued) Attenuator C VS R1 – VS R3 R4 R1 = R2 = R3 = R4 = 10kΩ R1 + VO R2 R + – VO Filter R2 VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) Inverting Amplifier R1 R2 Equivalent L-R Circuit } VS } – + VO C1 VS R2 + – VO = G VS G = - R2/R1 ZIN R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C – + R2 R1 – + } RA } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 21 FN8173.1 March 28, 2005 X9269 PACKAGING INFORMATION 24-Lead Plastic, TSSOP, Package Code V24 .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .041 (1.05) .0075 (.19) .0118 (.30) 0.002 (0.05) 0.005 (0.15) .010 (.25) Gage Plane 0° - 8° .020 (.50) .030 (.75) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) See Detail “A” ALL MEASUREMENTS ARE TYPICAL Seating Plane (1.78) (4.16) (7.72) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 FN8173.1 March 28, 2005 X9269 PACKAGING INFORMATION 24-Lead Plastic Small Outline Gull Wing Package Type S 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0.009 (0.22) 0.013 (0.33) 0.015 (0.40) 0.050 (1.27) 0.420" 0° - 8° FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 23 FN8173.1 March 28, 2005 X9269 ORDERING INFORMATION X9269 Device Y P T V VCC Limits Blank = 5V ± 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package S24 = 24-Lead SOIC V24 = 24-Lead TSSOP Potentiometer Organization Pot U= 50kΩ T= 100kΩ All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 FN8173.1 March 28, 2005