X9271UVI

® X9271 Single Supply/Low Power/256-Tap/SPI Bus Data Sheet March 31, 2005 FN8174.1 Single Digitally-Controlled (XDCP™) Potentiometer FEATURES • 256 Resistor Taps • SPI Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ VCC = 5V • 16 Nonvolatile Data Registers • Nonvolatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on Power-up. • Standby Current < 3µA Max • VCC: 2.7V to 5.5V Operation • 50kΩ, 100kΩ versions of End to End Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 14-Lead TSSOP • Low Power CMOS DESCRIPTION The X9271 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM VCC RH SPI Bus Interface Address Data Status Write Read Transfer Inc/Dec Bus Interface and Control Control Power-on Recall Wiper Counter Register (WCR) Data Registers 16 Bytes 50kΩ and 100kΩ 256-taps POT VSS RW RL 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9271 DETAILED FUNCTIONAL DIAGRAM VCC Bank 0 Power-on Recall R0 R1 HOLD CS SCK SO SI A0 A1 WP WIPER COUNTER REGISTER (WCR) 50kΩ and 100kΩ 256-taps RH INTERFACE AND CONTROL CIRCUITRY DATA R2 R3 RL RW Bank 1 R0 R1 Bank 2 R0 R1 Bank 3 R0 R1 Control R2 R3 R2 R3 R2 R3 12 additional nonvolatile registers 3 Banks of 4 registers x 8-bits VSS CIRCUIT LEVEL APPLICATIONS • Vary the gain of a voltage amplifier • Provide programmable dc reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the dc biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits SYSTEM LEVEL APPLICATIONS • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems 2 FN8174.1 March 31, 2005 X9271 PIN CONFIGURATION TSSOP S0 A0 NC CS SCK SI VSS 1 2 3 4 5 6 7 X9271 14 13 12 11 10 9 8 VCC RL RH RW HOLD A1 WP PIN ASSIGNMENTS TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol SO A0 NC CS SCK SI VSS WP A1 HOLD RW RH RL VCC Serial Data Output. Device Address. No Connect. Chip Select. Serial Clock. Serial Data Input. System Ground. Hardware Write Protect. Device Address. Function Device select. Pause the serial bus. Wiper Terminal of the Potentiometer. High Terminal of the Potentiometer. Low Terminal of the Potentiometer. System Supply Voltage. 3 FN8174.1 March 31, 2005 X9271 PIN DESCRIPTIONS Bus Interface Pins SERIAL OUTPUT (SO) SO is a serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9271. HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. CMOS level input. DEVICE ADDRESS (A1 - A0) The address inputs are used to set the the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9271. CHIP SELECT (CS) When CS is HIGH, the X9271 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9271, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. NO CONNECT. No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. 4 FN8174.1 March 31, 2005 X9271 PRINCIPLES OF OPERATION Device Description SERIAL INTERFACE The X9271 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. ARRAY DESCRIPTION The X9271 is comprised of a resistor array (See Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (See Table 1). POWER-UP AND DOWN RECOMMENDATIONS. There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate specification is always in effect. Figure 1. Detailed Potentiometer Block Diagram SERIAL DATA PATH FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) 8 BANK_0 Only SERIAL BUS INPUT REGISTER 1 (DR1) 8 PARALLEL BUS INPUT C O U N T E R D E C O D E RH REGISTER 2 (DR2) REGISTER 3 (DR3) WIPER COUNTER REGISTER (WCR) INC/DEC LOGIC IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH UP/DN MODIFIED SCK UP/DN CLK RL RW 5 FN8174.1 March 31, 2005 X9271 DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9271 contains a Wiper Counter Register for the DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/ Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9271 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the R0 value into the WCR. The DR0 value of Bank 0 is the default value. Data Registers (DR3–DR0) The potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bits [7:0] are used to store one of the 256 wiper positions or data (0 ~255). Status Register (SR) This 1-bit Status Register is used to store the system status. WIP: Write In Progress status bit, read only. – When WIP=1, indicates that high-voltage write cycle is in progress. – When WIP=0, indicates that no high-voltage write cycle is in progress Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). WCR7 V (MSB) WCR6 V WCR5 V WCR4 V WCR3 V WCR2 V WCR1 V WCR0 V (LSB) Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wiper positions or data (Nonvolatile, NV). Bit 7 NV MSB Bit 6 NV Bit 5 NV Bit 4 NV Bit 3 NV Bit 2 NV Bit 1 NV Bit 0 NV LSB Table 3. Status Register, SR (WIP is 1-bit) WIP (LSB) 6 FN8174.1 March 31, 2005 X9271 DEVICE DESCRIPTION Instructions IDENTIFICATION BYTE (ID AND A) The first byte sent to the X9271 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9271; this is fixed as 0101[B] (refer to Table 4). The A1 - A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A1 - A0 input pins. The slave address is externally specified by the user. The X9271 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9271 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1 - A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I[3:0]) The next byte sent to the X9271 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[3:0]). The RB and RA bits point to one of the four Data Registers. P0 is the POT selection; since the X9271 is single POT, the P0=0. The format is shown in Table 5. REGISTER BANK SELECTION (R1, R0, P1, P0) There are 16 registers organized into four banks. Bank 0 is the default bank of registers. Only Bank 0 registers can be used for data register to Wiper Counter Register operations. Table 4. Identification Byte Format Device Type Identifier Set to 0 for proper operation Internal Slave Address Banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for SPI write and read operations. The data registers in Banks 1, 2, and 3 cannot be used for direct read/write operations between the Wiper Counter Register. Register Selection (DR0 to DR3) Table Register RB 0 RA Selection Operations 0 0 Data Register Read and Write; Wiper Counter Register Operations 1 1 Data Register Read and Write; Wiper Counter Register Operations 0 2 Data Register Read and Write; Wiper Counter Register Operations 1 3 Data Register Read and Write; Wiper Counter Register Operations 0 1 1 Register Bank Selection (Bank 0 to Bank 3) Table Bank P1 0 P0 Selection Operations 0 0 Data Register Read and Write; Wiper Counter Register Operations 1 1 Data Register Read and Write Only 0 2 Data Register Read and Write Only 1 3 Data Register Read and Write Only 0 1 1 ID3 0 (MSB) ID2 1 ID1 0 ID0 1 0 0 A1 A0 (LSB) 7 FN8174.1 March 31, 2005 X9271 Table 5. Instruction Byte Format P1 and P0 are used also for register Bank Selection for SPI Register Write and Read operations Pot Selection (WCR Selection) Set to P0=0 for potentiometer operations Instruction Opcode Register Selection I3 (MSB) I2 I1 P0 RB RA P1 P0 (LSB) DEVICE DESCRIPTION Instructions Five of the eight instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the potentiometer; – Write Wiper Counter Register – change current wiper position of the potentiometer; – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. – Read Status - This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The basic sequence of the three byte instructions is illustrated in Figure 3. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. The Read Status Register instruction is the only unique format (See Figure 4). Two instructions require a two-byte sequence to complete (Figure 2). These instructions transfer data between the host and the X9271; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. The final command is Increment/Decrement (Figure 5 and 6). It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instruction format for more details. Write in Process (WIP bit) The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. 8 FN8174.1 March 31, 2005 X9271 Figure 2. Two-Byte Instruction Sequence CS SCK SI 0 1 0 1 0 0 0 0 A1 A0 I3 I2 I1 I0 0 0 ID3 ID2 ID1 ID0 Device ID RB RA P1 P0 Register Address Pot/Bank Address Internal Address Instruction Opcode These commands only valid when P1 = P0 = 0 Figure 3. Three-Byte Instruction Sequence (Write) CS SCL SI 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register Address D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 ID3 ID2 ID1 ID0 Device ID Instruction Opcode Pot/BankWCR[7:0] valid only when P1 = P0 = 0; Address or Data Register Bit [7:0] for all values of P1 and P0 Figure 4. Three-Byte Instruction Sequence (Read) CS SCL SI 0 0 0 0 A1 A0 Internal Address I3 I2 I1 I0 RB RA P1 P0 Register Address Pot/Bank Address 0 1 0 1 X X X X X X X X ID3 ID2 ID1 ID0 Device ID Don’t Care Instruction Opcode S0 D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] valid only when P1 = P0 = 0; or Data Register Bit [7:0] for all values of P1 and P0 9 FN8174.1 March 31, 2005 X9271 Figure 5. Increment/Decrement Instruction Sequence CS SCL SI 0 A1 A0 Internal Address I3 I2 I1 I0 0 I N C 1 I N C 2 I N C n D E C 1 D E C n 0 1 0 1 0 0 0 0 ID3 ID2 ID1 ID0 Device ID RA RB P1 P0 Register Address Pot/Bank Address Instruction Opcode Figure 6. Increment/Decrement Timing Limits tWRID SCK SI V W VOLTAGE OUT INC/DEC CMD ISSUED Table 6. Instruction Set Instruction Read Wiper Counter Register Write Wiper Counter Register Read Data Register Write Data Register XFR Data Register to Wiper Counter Register XFR Wiper Counter Register to Data Register Increment/Decrement Wiper Counter Register Read Status (WIP bit) Note: 1/0 = data is one or zero I3 1 1 1 1 1 I2 0 0 0 1 1 I1 0 1 1 0 0 Instruction Set I0 RB RA 1 0 0 0 1 0 1 0 1/0 1/0 1/0 0 1/0 1/0 1/0 P1 0 0 1/0 1/0 0 P0 1/0 1/0 1/0 1/0 0 Operation Read the contents of the Wiper Counter Register Write new value to the Wiper Counter Register Read the contents of the Data Register pointed to by P1 - P0 and RB - RA Write new value to the Data Register pointed to by P1 - P0 and RB - RA Transfer the contents of the Data Register pointed to by RB - RA (Bank 0 only) to the Wiper Counter Register Transfer the contents of the Wiper Counter Register to the Register pointed to by RB-RA (Bank 0 only) Enable Increment/decrement of the Wiper Counter Register Read the status of the internal write cycle, by checking the WIP bit. 1 1 1 0 1/0 1/0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 10 FN8174.1 March 31, 2005 X9271 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 0 1 DR/Bank Addresses 0 0 0 Wiper Position (Sent by X9271 on SO) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS Falling Edge 0 0 0 A1 A0 1 W C 0 R 7 CS W Rising C Edge R 0 Write Wiper Counter Register (WCR) Device Type Identifier 1 0 1 Device Addresses Instruction Opcode 0 1 0 DR/Bank Addresses 0 0 0 W C 0 R 7 Data Byte (Sent by Host on SI) W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 CS Falling Edge 0 0 0 A1 A0 1 CS W Rising C Edge R 0 Read Data Register (DR) Device Type Device Instruction DR/Bank Data Byte CS CS Identifier Addresses Opcode Addresses (Sent by X9271 on SO) Falling Rising Edge 0 1 0 1 0 0 A1 A0 1 0 1 1 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge Write Data Register (DR) Device Type Identifier Device Addresses Instruction Opcode DR/Bank Addresses Data Byte (Sent by Host on SI) HIGH-VOLTAGE WRITE CYCLE FN8174.1 March 31, 2005 CS Falling Edge 0 CS Rising 1 0 1 0 0 A1 A0 1 1 0 0 RB RA P1 P0 D7 D 6 D5 D4 D3 D2 D1 D0 Edge Transfer Wiper Counter Register (WCR) to Data Register (DR) CS Falling Edge Device Type Identifier 0 1 0 1 Device Addresses Instruction Opcode DR/Bank Addresses RB RA 0 0 CS Rising Edge HIGH-VOLTAGE WRITE CYCLE 0 0 A1 A0 1 1 1 0 11 X9271 Transfer Data Register (DR) to Wiper Counter Register (WCR) Device Type Device CS Identifier Addresses Falling Edge 0 1 0 1 0 0 A1 A0 Instruction Opcode DR/Bank Addresses 0 0 CS Rising Edge 1 1 0 1 RB RA Increment/Decrement Wiper Counter Register (WCR) Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses 00 A1 A0 Instruction Opcode DR/Bank Addresses Increment/Decrement (Sent by Master on SDA) . . . . CS Rising I/D I/D Edge 0 0 1 0 X X 0 0 I/D I/D Read Status Register (SR) Device Type CS Identifier Falling Edge 0 1 0 1 Device Addresses 00 A1 A0 Instruction Opcode DR/Bank Addresses Data Byte (Sent by X9271 on SO) WIP CS Rising Edge 010100010000000 Notes: (1) (2) (2) (3) (4) “A1 ~ A0”: stands for the device addresses sent by the master. WCRx refers to wiper position data in the Wiper Counter Register “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). “X:”: Don’t Care. 12 FN8174.1 March 31, 2005 X9271 ABSOLUTE MAXIMUM RATINGS Temperature under bias..................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on SCK any address input with respect to VSS ................................. -1V to +7V ∆V = |(VH - VL)|..................................................... 5.5V Lead temperature (soldering, 10 seconds)........ 300°C IW (10 seconds)..................................................±6mA COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Commercial Industrial Min. 0°C -40°C Max. +70°C +85°C Device X9271 X9271-2.7 Supply Voltage (VCC)(4) Limits 5V ± 10% 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.) Limits Symbol RTOTAL RTOTAL Parameter End to End Resistance End to End Resistance End to End Resistance Tolerance Power Rating Min. Typ. 100 50 Max. Units kΩ kΩ Test Conditions T version U version ±20 50 ±3 300 150 VSS -120 0.4 ±1 ±0.2 ±300 20 10/10/25 VCC % mW mA Ω Ω V dBV/√Hz % MI(3) MI(3) ppm/°C ppm/°C pF See Macro model Rw(n)(actual) - Rw(n)(expected)(5) Rw(n + 1) - [Rw(n) + MI](5) IW = ± 3mA @ VCC = 3V IW = ± 3mA @ VCC = 5V VSS = 0V Ref: 1V 25°C, each pot IW RW RW VTERM Wiper Current Wiper Resistance Wiper Resistance Voltage on any RH or RL Pin Noise Resolution Absolute Linearity(1) Relative Linearity(2) Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW Potentiometer Capacitancies Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH - RL) / 255, single pot (4) During power-up VCC > VH, VL, and VW. (5) n = 0, 1, 2, …,255; m =0, 1, 2, …., 254. 13 FN8174.1 March 31, 2005 X9271 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol ICC1 ICC2 ISB ILI ILO VIH VIL VOL VOH VOH Parameter VCC supply current (active) VCC supply current (nonvolatile write) VCC current (standby) Input leakage current Output leakage current Input HIGH voltage Input LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Min. Typ. Max. 400 Units µA mA µA µA µA V V V V V IOL = 3mA Test Conditions fSCK = 2.5 MHz, SO = Open, VCC = 6V Other Inputs = VSS fSCK = 2.5MHz, SO = Open, VCC = 6V Other Inputs = VSS SCK = SI = VSS, Addr. = VSS, CS = VCC = 6V VIN = VSS to VCC VOUT = VSS to VCC 1 5 3 10 10 VCC x 0.7 -1 VCC - 0.8 VCC - 0.4 VCC + 1 VCC x 0.3 0.4 IOH = -1mA, VCC ≥ +3V IOH = -0.4mA, VCC ≤ +3V ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention Min. 100,000 100 Units Data changes per bit per register years CAPACITANCE Symbol CIN/OUT COUT (6) (6) Test Input / Output capacitance (SI) Output capacitance (SO) Input capacitance (A0, CS, WP, HOLD, and SCK) Max. 8 8 6 Units pF pF pF Test Conditions VOUT = 0V VOUT = 0V VIN = 0V CIN(6) POWER-UP TIMING Symbol tr VCC (6) Parameter VCC Power-up rate Power-up to initiation of read operation Power-up to initiation of write operation Min. 0.2 Max. 50 1 50 Units V/ms ms ms tPUR(7) tPUW(7) A.C. TEST CONDITIONS Input Pulse Levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. 14 FN8174.1 March 31, 2005 X9271 EQUIVALENT A.C. LOAD CIRCUIT 5V 1462 Ω SO pin 2714 Ω 100pF SO pin 1217 Ω 100pF 10pF RW 3V 1382 Ω RH CL CW 25pF CL 10pF SPICE Macromodel RTOTAL RL AC TIMING Symbol fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI tCS tWPASU tWPAH SSI/SPI clock frequency SSI/SPI clock cycle time SSI/SPI clock high time SSI/SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs CS deselect time WP, A0 setup time WP, A0 hold time 2 0 0 400 100 100 100 100 10 0 100 100 0 500 200 200 250 250 50 50 2 2 250 200 Parameter Min. Max. 2.5 Units MHz ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns µs ns ns 15 FN8174.1 March 31, 2005 X9271 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol tWR Parameter High-voltage write cycle time (store instructions) Typ. 5 Max. 10 Units ms XDCP TIMING Symbol tWRPO tWRL Parameter Wiper response time after the third (last) power supply is stable Wiper response time after instruction issued (all load instructions) Min. 5 5 Max. 10 10 Units µs µs SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance 16 FN8174.1 March 31, 2005 X9271 TIMING DIAGRAMS Input Timing tCS CS tLEAD SCK tSU SI MSB tH tWL tCYC ... tWH ... tLAG tFI LSB tRI SO High Impedance Output Timing CS SCK tV SO MSB tHO ... tDIS ... LSB SI ADDR Hold Timing CS tHSU SCK ... tRO SO tHZ SI tHOLD HOLD tLZ tFO tHH 17 FN8174.1 March 31, 2005 X9271 XDCP Timing (for All Load Instructions) CS SCK ... tWRL MSB ... LSB SI VWx SO High Impedance Write Protect and Device Address Pins Timing CS tWPASU WP A0 A1 (Any Instruction) tWPAH 18 FN8174.1 March 31, 2005 X9271 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers VR +VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS + – VO VIN 317 R1 R2 R1 VO (REG) Voltage Regulator Iadj R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 VS 100kΩ – + TL072 10kΩ 10kΩ +12V 10kΩ -12V VO R2 Comparator with Hysterisis VS – + VO VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) } R1 } R2 19 FN8174.1 March 31, 2005 X9271 Application Circuits (continued) Attenuator C VS R1 – VS R3 R4 R1 = R2 = R3 = R4 = 10kΩ R1 + VO R2 R + – VO Filter R2 VO = G VS -1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1 fc = 1/(2πRC) Inverting Amplifier R1 R2 Equivalent L-R Circuit } VS } – + VO C1 VS R2 + – VO = G VS G = - R2/R1 ZIN R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C – + R2 R1 – + } RA } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB 20 FN8174.1 March 31, 2005 X9271 PACKAGING INFORMATION 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8 ° .019 (.50) .029 (.75) Detail A (20X) Seating Plane .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 21 FN8174.1 March 31, 2005 X9271 ORDERING INFORMATION X9271 Device Y V T V VCC Limits Blank = 5V ± 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package V = 14-Lead TSSOP Potentiometer Organization Pot U= 50kΩ T= 100kΩ All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 FN8174.1 March 31, 2005