X9312

IGNS W DES F OR N E E ME N T DED OMMEN DED REPLAC nter at OT R E C N Ce N COMME Datal Sheetort om/tsc upp NO RE hnica S .intersil.c c w t our Te contac TERSIL or ww 88-IN 1-8 ® X9312 Terminal Voltage 0V to +15V, 100 Taps March 15, 2005 FN8176.0 Digitally Controlled Potentiometer (XDCP™) FEATURES • • • • Solid-state potentiometer 3-wire serial interface Terminal voltage, 0 to +15V 100 wiper tap points —Wiper position stored in nonvolatile memory and recalled on power-up 99 resistive elements —Temperature compensated —End to end resistance range ± 20% Low power CMOS —VCC = 5V —Active current, 3mA max. —Standby current, 1mA max. High reliability —Endurance, 100,000 data changes per bit —Register data retention, 100 years RTOTAL values = 10kΩ, 50kΩ, and 100kΩ Packages —8-lead SOIC and DIP DESCRIPTION The Intersil X9312 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a 3-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: – control – parameter adjustments – signal processing • • • • • BLOCK DIAGRAM U/D INC CS 7-Bit Up/Down Counter 99 98 97 7-Bit Nonvolatile Memory 96 One of One Hundred Decoder 2 VSS (Ground) General VCC VSS Store and Recall Control Circuitry 1 0 RL/VL RW/VW Detailed RH/VH VCC (Supply Voltage) Up/Down (U/D) Increment (INC) Device Select (CS) Control and Memory RH/VH RW/VW Transfer Gates Resistor Array RL/VL 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X9312 PIN DESCRIPTIONS RH/VH and RL/VL The high (RH/VH) and low (RL/VL) terminals of the X9312 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is 0V and the maximum is +15V. The terminology of RL/VL and RH/VH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW/VW Rw/Vw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40Ω. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incriminated or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9312 will be placed in the low power standby mode until the device is selected once again. PIN CONFIGURATION DIP/SOIC INC U/D RH/VH VSS 1 2 3 4 X9312 8 7 6 5 VCC CS RL/VL RW/VW PIN NAMES Symbol RH/VH RW/VW RL/VL VSS VCC U/D INC CS Description High terminal Wiper terminal Low terminal Ground Supply voltage Up/Down control input Increment control input Chip select control input PRINCIPLES OF OPERATION There are three sections of the X9312: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. 2 FN8176.0 March 15, 2005 X9312 INSTRUCTIONS AND PROGRAMMING The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven bit counter. The output of this counter is decoded to select one of one hundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9312, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a powerup/down cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc... The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. MODE SELECTION CS L L H H X L INC U/D H L X X X Wiper up Mode Wiper down Store wiper position Standby current No store, return to standby SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from Low to High May change from High to Low Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from Low to High Will change from High to Low Changing: State Not Known Center Line is High Impedance 3 FN8176.0 March 15, 2005 X9312 ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on CS, INC, U/D and VCC with respect to VSS ................................. -1V to +7V ∆V = |VH - VL| ........................................................ 15V Lead temperature (soldering 10 seconds) ......... 300°C IW (10 seconds) ...............................................±8.8mA COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0°C -40°C Max. +70°C +85°C Supply Voltage (VCC) X9312 Limits 5V ±10% POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol VVH VVL Parameter End to end resistance tolerance VH terminal voltage VL terminal voltage Power rating Power rating Min. VSS VSS Typ. Max. ±20 15 15 25 225 Unit % V V mW mW Ω mA dBV % Test Conditions/Notes VSS = 0V VSS = 0V RTOTAL ≥ 10kΩ RTOTAL = 1kΩ IW = 1mA, VCC = 5V Ref: 1kHz Rw(n)(actual) - Rw(n)(expected) Rw(n+1) - [Rw(n) + MI] RW IW Wiper resistance Wiper current Noise Resolution Absolute linearity(1) Relative linearity(2) RTOTAL temperature coefficient Ratiometric temperature coefficient 40 -120 1 100 ±4.4 ±1 ±0.2 ±300 ±20 10/10/25 MI(3) MI(3) ppm/°C ppm/°C pF CH/CL/CW Potentiometer capacitances See circuit #3 Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected)) = ±1 Ml Maximum. (2) Relative linearity is a measure of the error in step size between taps = RW(n+1 - [Rw(n) + Ml] = ±0.2 Ml. (3) 1 Ml = Minimum Increment = RTOT/99. 4 FN8176.0 March 15, 2005 X9312 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol ICC ISB ILI VIH VIL CIN(5) Parameter VCC active current (Increment) Standby supply current CS, INC, U/D input leakage current CS, INC, U/D input HIGH voltage CS, INC, U/D input LOW voltage CS, INC, U/D input capacitance Min. Typ.(4) 1 500 Max. 3 1000 ±10 Unit mA µA µA V V pF Test Conditions CS = VIL, U/D = VIL or VIH and INC = 0.4V/2.4V @ max. tCYC CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VIN = VSS to VCC 2 -1 VCC + 1 0.8 10 VCC = 5V, VIN = VSS, TA = 25°C, f = 1MHz ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention Min. 100,000 100 Unit Data changes per bit Years Notes: (4) Typical values are for TA = 25°C and nominal supply voltage. (5) This parameter is periodically sampled and not 100% tested. Test Circuit #1 VH/RH Test Circuit #2 VH/RH Test Point Test Point VW/RW VL/RL VL /RL L Circuit #3 SPICE Macro Model RTOTAL RH CH 10pF RW CW 25pF CL 10pF RL VS VW VW/RW Force Current A.C. CONDITIONS OF TEST Input pulse levels Input rise and fall times Input reference levels 0V to 3V 10ns 1.5V 5 FN8176.0 March 15, 2005 X9312 A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Limits Symbol tCl tlD tDI tlL tlH tlC tCPH tCPH tIW tCYC t R , t F7 tPU 7 7 Parameter CS to INC setup INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period INC inactive to CS inactive CS deselect time (STORE) CS deselect time (NO STORE) INC to Vw change INC cycle time INC input rise and fall time Power-up to wiper stable VCC power-up rate Min. 100 100 1 1 1 1 20 100 Typ.6 Max. Unit ns ns µs µs µs µs ms ns 100 4 500 500 500 µs µs µs µs V/ms tR VCC 0.2 50 POWER-UP AND DOWN REQUIREMENTS There are no restrictions on the sequencing of VCC and the voltages applied to the potentiometer pins during powerup or power-down conditions. During power-up, the data sheet parameters for the DCP do not fully apply until 1 millisecond after VCC reaches is final value. The VCC ramp spec is always in effect. A.C. TIMING CS tCYC tCI INC tID tDI tF tIL tIH tIC tCPH 90% 90% 10% tR U/D tIW VW MI (8) Notes: (6) Typical values are for TA = 25°C and nominal supply voltage. (7) This parameter is sample tested. (8) MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position. 6 FN8176.0 March 15, 2005 X9312 APPLICATIONS INFORMATION Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers VR VH VW/RW VL I Three terminal potentiometer; variable voltage divider Two terminal variable resistor; variable current VR Basic Circuits Buffered Reference Voltage R1 +V +5V VREF VW + – -5V VOUT = VW/RW (a) (b) OP-07 VOUT +V R1 VW/RW VO = (1+R2/R1)VS VW/RW X Cascading Techniques +V +V VS + – –5V R2 Noninverting Amplifier +5V LM308A VO Voltage Regulator Offset Voltage Adjustment Comparator with Hysteresis VIN 317 R1 VO (REG) R1 VS 100kΩ – + R2 VS LT311A – + VO VO TL072 Iadj R2 10kΩ 10kΩ VO (REG) = 1.25V (1+R2/R1)+Iadj R2 +12V -12V 10kΩ VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) (for additional circuits see AN115) } R1 } R2 7 FN8176.0 March 15, 2005 X9312 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050"Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250" 0.050" Typical FOOTPRINT 0.030" Typical 8 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8 FN8176.0 March 15, 2005 X9312 ORDERING INFORMATION X9312X X X Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC End to End Resistance W= 10kΩ Physical Characteristics Marking Includes Manufacturer’s Trademark Resistance Value or Code Date Code All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN8176.0 March 15, 2005