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ZL6105ALAFTR5546

ZL6105ALAFTR5546

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    VFQFN36_EP

  • 描述:

    IC REG CTRLR BUCK PMBUS 36QFN

  • 数据手册
  • 价格&库存
ZL6105ALAFTR5546 数据手册
DATASHEET ZL6105 FN6906 Rev 6.0 Jun 22, 2021 Digital DC/DC Controller with Drivers and Auto Compensation The ZL6105 is a digital power controller with integrated MOSFET drivers. Auto compensation eliminates the need for manual compensation design work. Adaptive performance optimization algorithms improve power conversion efficiency. Zilker Labs Digital-DC™ technology enables a blend of power conversion performance and power management features. Features The ZL6105 is designed to be a flexible building block for DC power and can be easily adapted to designs ranging from a single-phase power supply operating from a 3.3V to a multiphase current sharing supply operating from a 12V input. The ZL6105 eliminates the need for complicated power supply managers as well as numerous external discrete components. • Adaptive Light Load Efficiency Optimization The ZL6105 uses the I2C/SMBus™ with PMBus™ protocol for communication with a host controller and the Digital-DC bus for communication between Zilker Labs devices. • Fast Load Transient Response The ZL6105 is pin for pin compatible with the ZL2008. The POLA VOUT table and compensation table have been removed. A new single resistor VOUT table and the Auto Compensation feature have been added. Power Conversion • Efficient Synchronous Buck Controller • Auto Compensating PID Filter • 3V to 14V Input Range • 0.54V to 5.5V Output Range (with margin) • ±1% Output Voltage Accuracy • Internal 3A MOSFET Drivers • Current Sharing and Phase Interleaving • Snapshot™ Parameter Capture • Pb-Free (RoHs Compliant) Power Management • Digital Soft-start/stop Applications • Power-Good/Enable • Servers/Storage Equipment • Voltage Tracking, Sequencing and Margining • Telecom/Datacom Equipment • Voltage, Current and Temperature Monitoring • Power Supply Modules • I2C/SMBus Interface, PMBus Compatible • Output Voltage and Current Protection • Internal Non-volatile Memory (NVM) EN PG PH_EN FC ILIM CFG UVLO V25 100 VR VDD VOUT = 3.3V VOUT = 1.5V 95 LDO POWER MANAGEMENT DDC DRIVER NONVOLATILE MEMORY SCL SDA SALRT I2 C PWM CONTROLLER MONITOR ADC CURRENT SENSE TEMP SENSOR BST GH SW GL VSEN+ VSENISENA ISENB Efficiency (%) 90 V SS VTRK MGN SYNC 85 80 75 70 65 60 50 SA XTEMP PGND SGND DGND FIGURE 1. BLOCK DIAGRAM FN6906 Rev 6.0 Jun 22, 2021 VIN = 12V fSW = 400kHz Circuit of Figure 3 4 55 0 2 4 6 8 10 12 14 16 18 20 Load Current (A) FIGURE 2. EFFICIENCY vs LOAD CURRENT Page 1 of 35 © 2011 Renesas Electronics ZL6105 Table of Contents Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ZL6105 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-DC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Conversion Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multi-mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 11 11 Power Conversion Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Bias Regulators and Input Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-side Driver Boost Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Resistor Output Voltage Setting Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limit Threshold Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-linear Response (NLR) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency Optimized Driver Dead-time Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adaptive Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 13 13 13 14 15 15 16 19 20 22 22 22 Power Management Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Pre-Bias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C/SMBus Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C/SMBus Device Address Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Adding/Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring via I2C/SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Volatile Memory and Device Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 23 24 24 24 25 25 26 26 27 28 28 28 28 31 31 31 32 License Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FN6906 Rev 6.0 Jun 22, 2021 Page 2 of 35 ZL6105 Typical Application Circuit The following application circuit represents a typical implementation of the ZL6105. For enable using the PMBus, it is recommended to tie the enable pin (EN) to SGND. VIN 12V F.B.1 ENABLE CIN 3 x 10 µF 25 V 4.7 µF 25 V PHASE ENABLE DDC Bus 3 POWER GOOD OUTPUT CV25 10 µF 4V CB BST 26 3 SA0 GH 25 4 SA1 SW 24 ZL6105 5 ILIM 18 VSEN- EPAD SGND 17 VSEN+ ISENB 19 16 VRTK 9 SALRT 15 SS ISENA 20 14 UVLO 8 SDA 13 V1 VR 21 12 V0 7 SCL 11 FC1 GL 22 VOUT LOUT 2.2 µH PGND 23 6 CFG0 10 FC0 1 µF 16 V VDD 27 2 SYNC I2C/SMBus 2 DB BAT54 V25 28 DDC 30 XTEMP 29 MGN 31 EN 33 CFG1 32 PH_EN 34 PG 36 1 DGND V25 CFG2 35 QH COUT 2 x 47 µF 6.3 V QL 470 µF 2.5 V POS-CAP CVR 4.7 µF 2*220 µF 6.3 V 100 m RTN 6.3 V Ground unification Notes: 1. Ferrite bead is optional for input noise suppression 2. The I2C/SMBus requires pull-up resistors. Please refer to the I2C/SMBus specifications for more details. 3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices connected). The 10 kΩ default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise time. Please refer to the DDC Bus section for more details. FIGURE 3. 12V TO 1.8V/16A APPLICATION CIRCUIT FN6906 Rev 6.0 Jun 22, 2021 Page 3 of 35 ZL6105 Input Voltage Bus > PG EN MGN CFG(0,1,2) ILIM SS V(0,1) FC(0,1) VDD VR VTRK Power Management SYNC GEN BST NVM MOSFET Drivers Digital Compensator D-PWM SW VOUT NLR PLL SYNC  ADC - VSEN + REFCN ISENB ISENA ADC DAC VDD DDC I2C SALRT SDA SCL SA(0,1) Voltage Sensor MUX ADC VSEN+ VSENXTEMP Communication TEMP Sensor FIGURE 4. ZL6105 BLOCK DIAGRAM Pin Configuration 28 V25 29 XTEMP 30 DDC 31 MGN 32 CFG1 33 EN 34 PH_EN 35 CFG2 36 PG ZL6105 (36 LD QFN) TOP VIEW DGND 1 27 VDD SYNC 2 26 BST SA0 3 25 GH SA1 4 24 SW EXPOSED PADDLE* ILIM 5 23 PGND VSEN- 18 VSEN+ 17 19 ISENB VTRK 16 SALRT 9 SS 15 20 ISENA UVLO 14 SDA 8 V1 13 21 VR V0 12 SCL 7 FC1 11 22 GL FC0 10 CFG0 6 *CONNECT TO SGND FN6906 Rev 6.0 Jun 22, 2021 Page 4 of 35 ZL6105 Pin Descriptions PIN LABEL TYPE (Note 1) DESCRIPTION 1 DGND PWR 2 SYNC I/O,M (Note 2) 3 SA0 I, M Serial address select pins. Used to assign unique SMBus address to each IC or to enable certain management features. Current limit select. Sets the overcurrent threshold voltage for ISENA and ISENB. Digital ground. Common return for digital signals. Connect to low impedance ground plane. Clock synchronization input. Used to set switching frequency of internal clock or for synchronization to external frequency reference. 4 SA1 5 ILIM I, M 6 CFG0 I, M Configuration pin. Used to setup current sharing and non-linear response. 7 SCL I/O Serial clock. Connect to external host and/or to other ZL devices. 8 SDA I/O Serial data. Connect to external host and/or to other ZL devices. 9 SALRT O Serial alert. Connect to external host if desired. 10 FC0 I Loop compensation configuration pins. 11 FC1 I Output voltage selection pins. Used to set VOUT set-point and VOUT max. 12 V0 13 V1 14 UVLO I, M Undervoltage lockout selection. Sets the minimum value for VDD voltage to enable VOUT. 15 SS I, M Soft start pin. Sets the output voltage ramp time during turn-on and turn-off. Sets the delay from when EN is asserted until the output voltage starts to ramp. 16 VTRK I 17 VSEN+ I Output voltage feedback. Connect to output regulation point. 18 VSEN- I Output voltage feedback. Connect to load return or ground regulation point. 19 ISENB I Differential voltage input for current limit. 20 ISENA I Differential voltage input for current limit. High voltage tolerant. 21 VR PWR 22 GL O 23 PGND PWR Power ground. Connect to low impedance ground plane. 24 SW PWR Drive train switch node. Tracking sense input. Used to track an external voltage source. Internal 5V reference used to power internal drivers. Low side FET gate drive. 25 GH O 26 BST PWR 27 VDD (Note 3) PWR Supply voltage. 28 V25 PWR Internal 2.5V reference used to power internal circuitry. 29 XTEMP I 30 DDC I/O 31 MGN I 32 CFG1 I, M High-side FET gate drive. High-side drive boost voltage. External temperature sensor input. Connect to external 2N3904 diode connected transistor. Digital-DC Bus. (Open Drain) Interoperability between Zilker Labs devices. Signal that enables margining of output voltage. Configuration pin. Used to setup clock synchronization and sequencing. 33 EN I Enable input (active high). Pull-up to enable PWM switching and pull-down to disable PWM switching. 34 PH_EN I Phase enable input (active high). Pull-up to enable phase and pull-down to disable phase for current sharing. 35 CFG2 I, M 36 PG O ePad SGND PWR Configuration pin. Sets the phase offset (single-phase) or current sharing group position (multi-phase). Power-good output. Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low impedance ground plane. NOTES: 1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pin dependents. (Refer to “Multi-mode Pins” on page 11). 2. The SYNC pin can be used as a logic pin, a clock input or a clock output. 3. VDD is measured internally and the value is used to modify the PWM loop gain. FN6906 Rev 6.0 Jun 22, 2021 Page 5 of 35 ZL6105 Ordering Information PART NUMBER (Notes 5, 6) ZL6105ALAF PART MARKING PACKAGE DESCRIPTION (RoHS Compliant) PKG. DWG. # 6105 36 Ld QFN L36.6x6A ZL6105ALAFT ZL6105ALAFTK CARRIER TYPE (Note 4) TEMP. RANGE Tube -40 to +85°C Reel, 100 Reel, 1k NOTES: 4. See TB347 for details about reel specifications. 5. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 6. For Moisture Sensitivity Level (MSL), see the ZL6105 device information page. For more information on MSL, see TB363. FN6906 Rev 6.0 Jun 22, 2021 Page 6 of 35 ZL6105 Absolute Maximum Ratings (Note 7) Thermal Information DC Supply Voltage for VDD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 17V MOSFET Drive Reference for VR Pin @ 120mA . . . . . . . . . . . -0.3V to 6.5V 2.5V Logic Reference for V25 Pin @ 120mA . . . . . . . . . . . . . . . -0.3V to 3V Logic I/O Voltage for CFG(0,1,2), DDC, EN, FC(0, 1), ILIM, MGN, PG, PH_EN, SA(0, 1), SALRT, SCL, SDA, SS, SYNC, UVLO, V(0,1) Pins . . . . . . . . . . . . . . . . -0.3V to 6.5V Analog Input Voltages for ISENB, VSEN, VTRK, XTEMP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Analog Input Voltages for ISENA Pin . . . . . . . . . . . . . . . . . . . . . -1.5V to 30V High Side Supply Voltage for BST Pin . . . . . . . . . . . . . . . . . . . . -0.3V to 30V Boost to Switch Voltage for BST - SW Pins . . . . . . . . . . . . . . . . . -0.3V to 8V High Side Drive Voltage for GH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(VSW - 0.3V) to (VBST + 0.3V) Low Side Drive Voltage for GL Pin . . . . . . . . . . (PGND - 0.3V) to VR + 0.3V Switch Node for SW Pin Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(PGND - 0.3V) to 30V Transient ( 6V, IVR < 20mA 4.5 5.2 5.5 V V25 Reference Output Voltage VR > 3V, IV25 < 20mA 2.25 2.5 2.75 V 0.6 – 5.0 V Output Characteristics Output Voltage Adjustment Range (Note 12) VIN > VOUT Output Voltage Set-point Resolution Set using resistors – 10 – mV Set using I2C/SMBus – ±0.025 – % FS (Note 13) Includes line, load, temp -1 – 1 % Output Voltage Accuracy (Note 14) Vsen Input Bias Current VSEN = 5.5V – 110 200 µA Current Sense Differential Input Voltage (Ground Referenced) VISENA -VISENB -100 – 100 mV Current Sense Differential Input Voltage (Vout Referenced, Vout < 4.0V) VISENA -VISENB -50 – 50 mV Current Sense Input Bias Current Ground referenced -100 – 100 µA FN6906 Rev 6.0 Jun 22, 2021 Page 7 of 35 ZL6105 Electrical Specifications VDD = 12V, TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER CONDITIONS MIN (Note 19) TYP MAX (Note 19) UNIT – 1 µA Current Sense Input Bias Current (Vout Referenced, Vout < 4.0V) ISENA -1 ISENB -100 – 100 µA Soft-start Delay Duration Range Set using SS pin or resistor (Note 15) 5 – 30 ms Set using I2C/SMBus (Note 15) Soft-start Delay Duration Accuracy Soft-start Ramp Duration Range 0.005 – 500 s Turn-on delay (Note 15) - -0.25/+4 - ms Turn-off delay (Note 15) - -0.25/+4 - ms Set using SS pin or resistor 2 – 20 ms Set using I2C 0 – 200 ms – 100 – µs -250 – 250 nA – – 0.8 V – 1.4 – V Soft-start Ramp Duration Accuracy Logic Input/Output Characteristics Logic Input Leakage Current EN, SCL, SDA pins Logic Input Low, VIL Logic Input OPEN (N/C) Multi-mode logic pins 2.0 – – V Logic Output Low, VOL IOL  4mA (Note 20) – – 0.4 V Logic Output High, VOH IOH  -2mA (Note 20) 2.25 – – V 200 – 1400 kHz Logic Input High, VIH Oscillator and Switching Characteristics Switching Frequency Range Switching Frequency Set-point Accuracy Predefined settings (See Table 11) -5 – 5 % Maximum Pwm Duty Cycle Factory default 95 – – % 150 – – ns -13 – 13 % Minimum Sync Pulse Width Input Clock Frequency Drift Tolerance External clock source Gate Drivers – 4.5 – V High-side Driver Peak Gate Drive Current (Pull-down) High-side driver voltage (VBST -VSW) (VBST -VSW) = 4.5V 2 3 – A High-side Driver Pull-up Resistance (VBST -VSW) = 4.5V, (VBST -VGH) = 50mV – 0.8 2  High-side Driver Pull-down Resistance (VBST -VSW) = 4.5V, (VGH -VSW) = 50mV – 0.5 2  Low-side Driver Peak Gate Drive Current (Pull-up) VR = 5V – 2.5 – A Low-side Driver Peak Gate Drive Current (Pull-down) VR = 5V – 1.8 – A Low-side Driver Pull-up Resistance VR = 5V, (VR -VGL) = 50mV – 1.2 2  Low-side Driver Pull-down Resistance VR = 5V, (VGL -PGND) = 50mV – 0.5 2  Gh Rise and Fall Time (VBST -VSW) = 4.5V, CLOAD = 2.2nF – 5 20 ns Gl Rise and Fall Time VR = 5V, CLOAD = 2.2nF – 5 20 ns Switching Timing Tracking VTRK Input Bias Current VTRK = 5.5V VTRK Tracking Ramp Accuracy 100% Tracking, VOUT -VTRK, no prebias – 110 200 µA -100 – + 100 mV VTRK Regulation Accuracy 100% Tracking, VOUT -VTRK -1 – 1 % Configurable via I2C/SMBus 2.85 – 16 V -150 – 150 mV – 3 – % 0 – 100 % Fault Protection Characteristics UVLO Threshold Range UVLO Set-point Accuracy UVLO Hysteresis Factory default Configurable via FN6906 Rev 6.0 Jun 22, 2021 I2C/SMBus Page 8 of 35 ZL6105 Electrical Specifications VDD = 12V, TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER CONDITIONS UVLO Delay MIN (Note 19) TYP MAX (Note 19) UNIT – 2.5 - µs Power Good VOUT Threshold Factory default – 90 – % VOUT Power Good VOUT Hysteresis Factory default – 5 – % Power Good Delay Using pin-strap or resistor (Note 16) 0 – 200 ms Configurable via I2C/SMBus 0 – 500 s Factory default – 85 – % VOUT Configurable via I2C/SMBus 0 – 110 % VOUT Factory default – 115 – % VOUT 0 – 115 % VOUT – 5 – % VOUT – 16 – µs VSEN Undervoltage Threshold VSEN Overvoltage Threshold Configurable via I2C/SMBus VSEN Undervoltage Hysteresis VSEN Undervoltage/Overvoltage Fault Response Time Factory default I2C/SMBus 5 – 60 µs Current Limit Set-point Accuracy (VOUT Referenced) – ±10 – % FS (Note 17) Current Limit Set-point Accuracy (Ground Referenced) – ±10 – % FS (Note 17) Factory default – 10 – tSW (Note 18) Configurable via I2C/SMBus 1 – 32 tSW (Note 18) Current Limit Protection Delay Configurable via Temperature Compensation of Current Limit Protection Threshold Factory default Thermal Protection Threshold (Junction Temperature) Factory default Configurable via I2C/SMBus Configurable via I2C/SMBus Thermal Protection Hysteresis 4400 100 ppm/°C 12700 – 125 – °C -40 – 125 °C – 15 – °C NOTES: 12. Does not include margin limits. 13. Percentage of Full Scale (FS) with temperature compensation applied. 14. VOUT measured at the termination of the VSEN+ and VSEN-sense points. 15. The device requires a minimum delay period following an enable signal and prior to ramping its output as described in “Soft-Start Delay and Ramp Times” on page 14. 16. Factory default Power Good delay is set to the same value as the soft-start ramp time. Refer to “Soft-Start Delay and Ramp Times” on page 14 for further restrictions on PG Delay. 17. Percentage of Full Scale (FS) with temperature compensation applied 18. tSW = 1/fSW, where fSW is the switching frequency. 19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 20. Nominal capacitance of logic pins is 5pF. FN6906 Rev 6.0 Jun 22, 2021 Page 9 of 35 ZL6105 The ZL6105 is an innovative mixed-signal power conversion and power management IC based on Zilker Labs patented Digital-DC technology that provides an integrated, high performance step-down converter for a wide variety of power supply applications. Today’s embedded power systems are typically designed for optimal efficiency at maximum load, reducing the peak thermal stress by limiting the total thermal dissipation inside the system. Unfortunately, many of these systems are often operated at load levels far below the peak where the power system has been optimized, resulting in reduced efficiency. While this may not cause thermal stress to occur, it does contribute to higher electricity usage and results in higher overall system operating costs. Zilker Labs’ efficiency-adaptive ZL6105 DC/DC controller helps mitigate this scenario by enabling the power converter to automatically change their operating state to increase efficiency and overall performance with little or no user interaction needed. Auto compensation is available to eliminate the need for manual compensation of the PID filter. Its unique PWM loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no software required, resulting in a very flexible device that is also very easy to use. An extensive set of power management functions are fully integrated and can be configured using simple pin connections. The user configuration can be saved in an internal non-volatile memory (NVM). Additionally, all functions can be configured and monitored using the SMBus hardware interface using standard PMBus commands, allowing ultimate flexibility. Once enabled, the ZL6105 is immediately ready to regulate power and perform power management tasks with no programming required. Advanced configuration options and real-time configuration changes are available via the I2C/SMBus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. Integrated sub-regulation circuitry enables single supply operation from any supply between 3V and 14V with no secondary bias supplies needed. The ZL6105 can be configured by simply connecting its pins according to the tables provided in the following sections. Additionally, a comprehensive set of development tools and application notes are available to help simplify the design process. An evaluation board is also available to help the user become familiar with the device. This board can be evaluated as a standalone platform using pin configuration settings. A Windows™ based GUI is also provided to enable full configuration and monitoring capability via the I2C/SMBus interface using an available computer and the included USB cable. Application notes are available to assist the user in designing to specific application demands. Please visit ZL6105 to access the most up-to-date documentation. FN6906 Rev 6.0 Jun 22, 2021 The ZL6105 operates as a voltage-mode, synchronous buck converter with a selectable constant frequency pulse width modulator (PWM) control scheme that uses external MOSFETs, capacitors, and an inductor to perform power conversion. VIN DB VR QH GH ZL CIN BST SW CB VOUT C OUT QL GL FIGURE 5. SYNCHRONOUS BUCK CONVERTER Figure 5 illustrates the basic synchronous buck converter topology showing the primary power train components. This converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. In its most simple configuration, the ZL6105 requires two external N-channel power MOSFETs, one for the top control MOSFET (QH) and one for the bottom synchronous MOSFET (QL). The amount of time that QH is on as a fraction of the total switching period is known as the duty cycle D, which is described by Equation 1: D VOUT VIN (EQ. 1) During time D, QH is on and VIN – VOUT is applied across the inductor. The current ramps up as shown in Figure 6. When QH turns off (time 1-D), the current flowing in the inductor must continue to flow from the ground up through QL, during which the current ramps down. Since the output capacitor COUT exhibits a low impedance at the switching frequency, the AC component of the inductor current is filtered from the output voltage so the load sees nearly a DC voltage. VIN - VOUT ILPK IO 0 -VOUT CURRENT (A) Digital-DC Architecture Power Conversion Overview VOLTAGE (V) ZL6105 Overview ILV D 1-D TIME FIGURE 6. INDUCTOR WAVEFORM Typically, buck converters specify a maximum duty cycle that effectively limits the maximum output voltage that can be realized for a given input voltage. This duty cycle limit ensures that the low-side MOSFET is allowed to turn on for a minimum amount of time during each switching cycle, which enables the bootstrap capacitor (CB in Figure 6) to be charged up and provide adequate Page 10 of 35 ZL6105 gate drive voltage for the high-side MOSFET. See “High-side Driver Boost Circuit” on page 12 for more details. In general, the size of components L1 and COUT as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, fSW. Therefore, the highest efficiency circuit may be realized by switching the MOSFETs at the lowest possible frequency; however, this will result in the largest component size. Conversely, the smallest possible footprint may be realized by switching at the fastest possible frequency but this gives a somewhat lower efficiency. Each user should determine the optimal combination of size and efficiency when determining the switching frequency for each application. The block diagram for the ZL6105 is illustrated in Figure 4. In this circuit, the target output voltage is regulated by connecting the differential VSEN pins directly to the output regulation point. The VSEN signal is then compared to a reference voltage that has been set to the desired output voltage level by the user. The error signal derived from this comparison is converted to a digital value with a low-resolution, analog to digital (A/D) converter. The digital signal is applied to an adjustable digital compensation filter, and the compensated signal is used to derive the appropriate PWM duty cycle for driving the external MOSFETs in a way that produces the desired output. The ZL6105 has several features to improve the power conversion efficiency. A non-linear response (NLR) loop improves the response time and reduces the output deviation as a result of a load transient. The ZL6105 monitors the power converter’s operating conditions and continuously adjusts the turn-on and turn-off timing of the high-side and low-side MOSFETs to optimize the overall efficiency of the power supply. Adaptive performance optimization algorithms such as dead-time control, diode emulation, and frequency control are available to provide greater efficiency improvement. Power Management Overview The ZL6105 incorporates a wide range of configurable power management features that are simple to implement with no external components. Additionally, the ZL6105 includes circuit protection features that continuously safeguard the device and load from damage due to unexpected system faults. The ZL6105 can continuously monitor input voltage, output voltage/current, internal temperature, and the temperature of an external thermal diode. A Power-Good output signal is also included to enable power-on reset functionality for an external processor. All power management functions can be configured using either pin configuration techniques (see Figure 8) or via the I2C/SMBus interface. Monitoring parameters can also be pre-configured to provide alerts for specific conditions. See Application Note AN2033 for more details on SMBus monitoring. Multi-mode Pins PIN-STRAP SETTINGS This is the simplest implementation method, as no external components are required. Using this method, each pin can take on one of three possible states: LOW, OPEN, or HIGH. These pins can be connected to the V25 pin for logic HIGH settings as this pin provides a regulated voltage higher than 2V. Using a single pin, one of three settings can be selected. Using two pins, one of nine settings can be selected. TABLE 1. MULTI-MODE PIN CONFIGURATION PIN TIED TO VALUE LOW (Logic LOW) < 0.8 VDC OPEN (N/C) No connection HIGH (Logic HIGH) > 2.0 VDC Resistor to SGND Set by resistor value Logic high Open ZL ZL Multi- mode Pin Multi- mode Pin RSET Logic low Pin-strap Settings Resistor Settings FIGURE 7. PIN-STRAP AND RESISTOR SETTING EXAMPLES RESISTOR SETTINGS This method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi-mode pin and SGND. Standard 1% resistor values are used, and only every fourth E96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. Up to 31 unique selections are available using a single resistor. I2C/SMBUS METHOD Almost any ZL6105 function can be configured via the I2C/SMBus interface using standard PMBus commands. Additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configured and/or verified via the I2C/SMBus. See Application Note AN2033 for more details. The SMBus device address and VOUT_MAX are the only parameters that must be set by external pins. All other device parameters can be set via the I2C/SMBus. The device address is set using the SA0 and SA1 pins. VOUT_MAX is determined as 10% greater than the voltage set by the V0 and V1 pins. In order to simplify circuit design, the ZL6105 incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device with no programming. Most power management features can be configured using these pins. The multi-mode pins can respond to four different connections as shown in Table 1. These pins are sampled when power is applied or by issuing a PMBus Restore command (see Application Note AN2033). FN6906 Rev 6.0 Jun 22, 2021 Page 11 of 35 ZL6105 Power Conversion Functional Description Internal Bias Regulators and Input Supply Connections The ZL6105 employs two internal low dropout (LDO) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. The internal bias regulators are as indicated in the following: VR - The VR LDO provides a regulated 5V bias supply for the MOSFET driver circuits. It is powered from the VDD pin. A 4.7µF filter capacitor is required at the VR pin. V25 - The V25 LDO provides a regulated 2.5V bias supply for the main controller circuitry. It is powered from an internal 5V node. A 10µF filter capacitor is required at the V25 pin. When the input supply (VDD) is higher than 5.5V, the VR pin should not be connected to any other pins. It should only have a filter capacitor attached as shown in Figure 8. Due to the dropout voltage associated with the VR bias regulator, the VDD pin must be connected to the VR pin for designs operating from a supply below 5.5V. Figure 8 illustrates the required connections for both cases. VIN VIN VDD ZL VDD ZL VR TABLE 2. OUTPUT VOLTAGE PIN-STRAP SETTINGS V0 V1 LOW OPEN HIGH LOW 0.6V 0.8V 1.0V OPEN 1.2V 1.5V 1.8V HIGH 2.5V 3.3V 5.0V The resistor setting method can be used to set the output voltage to levels not available in Table 2. Resistors R0 and R1 are selected to produce a specific voltage between 0.6V and 5.0V in 10mV steps. Resistor R1 provides a coarse setting and resistor R0 provides a fine adjustment, thus eliminating the additional errors associated with using two 1% resistors (this typically adds approximately 1.4% error). To set VOUT using resistors, follow the steps indicated to calculate an index value and then use Table 3 to select the resistor that corresponds to the calculated index value as follows: 1. Calculate Index1: (EQ. 2) Index1 = 4 x VOUT (VOUT in 10mV steps) 2. Round the result down to the nearest whole number. 3. Select the value of R1 from Table 3 using the Index1 rounded value from step 2. 4. Calculate Index0: (EQ. 3) Index0 = 100 x VOUT - (25 x Index1) VR 5. Select the value of R0 from Table 3 using the Index0 value from step 4. 3V ≤VIN ≤ 5.5V 5.5V
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