IRL7833LPBF

PD - 95270 Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Consumer Use l Lead-Free Benefits l l l HEXFET® Power MOSFET IRL7833PbF IRL7833SPbF IRL7833LPbF Qg 32nC VDSS RDS(on) max 30V 3.8m: Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current TO-220AB IRL7833 D2Pak IRL7833S TO-262 IRL7833L Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Max. 30 ± 20 150 600 140 72 0.96 -55 to + 175 Units V ™ f 110f A W Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range g g W/°C °C Mounting Torque, 6-32 or M3 screw 10 lbf in (1.1N m) y y Thermal Resistance Parameter RθJC RθCS RθJA RθJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient h Junction-to-Ambient (PCB Mount) Typ. Max. 1.04 ––– 62 40 Units °C/W h ––– 0.50 ––– ––– gà Notes  through † are on page 12 www.irf.com 1 05/18/04 IRL7833/S/LPbF Static @ TJ = 25°C (unless otherwise specified) Parameter BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Min. Typ. Max. Units 30 ––– ––– ––– 1.4 ––– ––– ––– ––– ––– 150 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 18 3.1 3.7 ––– -11 ––– ––– ––– ––– ––– 32 8.7 5.1 13 5.3 18 22 18 50 21 6.9 4170 950 470 ––– ––– 3.8 4.5 2.3 ––– 1.0 150 100 -100 ––– 47 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– pF VGS = 0V VDS = 15V ns nC nC VDS = 16V VGS = 4.5V ID = 30A S nA V mV/°C µA V Conditions VGS = 0V, ID = 250µA mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 38A VGS = 4.5V, ID = 30A f f VDS = VGS, ID = 250µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 30A See Fig. 16 VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V ID = 26A Clamped Inductive Load f ƒ = 1.0MHz Avalanche Characteristics EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Ù dh Typ. ––– ––– ––– Max. 560 30 14 Units mJ A mJ Repetitive Avalanche Energy ™ ––– ––– ––– ––– ––– ––– ––– ––– 42 34 Diode Characteristics Parameter IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Min. Typ. Max. Units 150 f Conditions MOSFET symbol D A 600 1.2 63 51 V ns nC Ùh showing the integral reverse G S p-n junction diode. TJ = 25°C, IS = 30A, VGS = 0V TJ = 25°C, IF = 30A, VDD = 15V di/dt = 100A/µs f f 2 www.irf.com IRL7833/S/LPbF 1000 TOP VGS 10V 7.0V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 1000 TOP VGS 10V 7.0V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V ID, Drain-to-Source Current (A) 100 BOTTOM ID, Drain-to-Source Current (A) 100 BOTTOM 2.7V 10 2.7V 10 20µs PULSE WIDTH Tj = 25°C 1 0.1 1 10 100 1000 1 0.1 1 20µs PULSE WIDTH Tj = 175°C 10 100 1000 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (Α) ID = 75A VGS = 10V T J = 175°C 1.5 100 1.0 TJ = 25°C 10 2.0 3.0 4.0 VDS = 15V 20µs PULSE WIDTH 5.0 6.0 7.0 8.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 VGS, Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRL7833/S/LPbF 100000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd 12.0 ID= 30A VGS, Gate-to-Source Voltage (V) 10.0 VDS= 24V VDS= 15V C, Capacitance(pF) 10000 8.0 6.0 Ciss Coss 1000 Crss 4.0 2.0 100 1 10 100 0.0 0 5 10 15 20 25 30 35 40 VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000.00 T J = 175°C 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) ISD, Reverse Drain Current (A) 100.00 ID, Drain-to-Source Current (A) 100 100µsec 10 1msec 1 Tc = 25°C Tj = 175°C Single Pulse 0.1 1 10 VDS, Drain-to-Source Voltage (V) 10msec 10.00 1.00 T J = 25°C VGS = 0V 0.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VSD, Source-to-Drain Voltage (V) 100 Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRL7833/S/LPbF 160 2.5 LIMITED BY PACKAGE VGS(th) Gate threshold Voltage (V) 2.0 120 ID , Drain Current (A) 1.5 80 ID = 250µA 1.0 40 0.5 0 25 50 75 100 125 150 175 0.0 TC, Case Temperature (°C) -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10. Threshold Voltage Vs. Temperature 10 (Z thJC ) 1 D = 0.50 Thermal Response 0.20 0.10 0.1 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1 / t 2 +TC 1 P DM t1 t2 J = P DM x Z thJC 0.1 t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRL7833/S/LPbF 15V 2000 ID TOP 12A 21A 30A VDS L DRIVER 1600 BOTTOM RG 20V VGS D.U.T IAS tp + V - DD EAS , Single Pulse Avalanche Energy (mJ) 1200 A 0.01Ω 800 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 400 0 25 50 75 100 125 150 175 Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS LD VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T VGS Pulse Width < 1µs Duty Factor < 0.1% Current Regulator Same Type as D.U.T. 50KΩ 12V .2µF .3µF Fig 14a. Switching Time Test Circuit D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID Current Sampling Resistors VGS td(on) tr td(off) tf Fig 13. Gate Charge Test Circuit Fig 14b. Switching Time Waveforms 6 www.irf.com IRL7833/S/LPbF D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V ƒ + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt ‚ - „ +  RG • • • • dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRL7833/S/LPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by; * Ploss = Pconduction + P + Poutput drive Ploss = Irms × Rds(on) + ( g × Vg × f ) Q ( 2 ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput This can be expanded and approximated by; ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝2 ⎠ *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgd +⎜I × × Vin × ig ⎝ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝2 ⎠ ⎞ ⎞⎛ Qgs 2 f⎟ + ⎜ I × × Vin × f ⎟ ig ⎠⎝ ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRL7833/S/LPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048) 4 15.24 (.600) 14.84 (.584) 1.15 (.045) MIN 1 2 3 LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 1.40 (.055) 3X 1.15 (.045) 2.54 (.100) 2X NOTES: 0.93 (.037) 0.69 (.027) M BAM 3X 0.55 (.022) 0.46 (.018) 0.36 (.014) 2.92 (.115) 2.64 (.104) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS . TO-220AB Part Marking Information E XAMPL E : T H IS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T HE AS S E MB L Y L INE "C" INT E R NAT IONAL RE CT IF IE R L OGO AS S E MB L Y L OT CODE P AR T NU MB E R Note: "P" in assembly line position indicates "Lead-Free" DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C www.irf.com 9 IRL7833/S/LPbF D2Pak Package Outline D2Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN THE AS SEMBLY LINE "L" Note: "P" in assembly line position indicates "Lead-Free" INTERNATIONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBE R F530S DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L OR INT ERNAT IONAL RECTIF IER LOGO PART NUMBER F 530S DAT E CODE P = DESIGNAT E S LEAD-F REE PRODUCT (OPTIONAL) YE AR 0 = 2000 WE EK 02 A = ASSE MBLY SIT E CODE ASSE MBLY LOT CODE 10 www.irf.com IRL7833/S/LPbF TO-262 Package Outline TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN T HE AS S EMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT ERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C OR INT ERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY SITE CODE www.irf.com 11 IRL7833/S/LPbF Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) D2Pak Tape & Reel Information FEED DIRECTION 1.85 (.073) 1.65 (.065) 11.60 (.457) 11.40 (.449) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Notes:  Repetitive rating; pulse width limited by max. junction temperature. ‚ Starting TJ = 25°C, L = 1.3mH, RG = 25Ω, IAS = 30A. ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%. „ Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. … When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. † This is only applied to TO-220AB package. TO-220AB package isnot recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.05/04 12 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/