IRS21303DPBF

PRELIMINARY Data Sheet No. PD60256 revA IRS2130D/IRS21303D/IRS2132D 3-PHASE BRIDGE DRIVER Features • • • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Three Independent half-bridge drivers Matched propagation delay for all channels 2.5 V logic compatible Outputs out of phase with inputs Cross-conduction prevention logic All parts are LEAD-FREE Integrated bootstrap diode function Product Summary VOFFSET IO+/- (min.) VOUT ton/off (typ.) Deadtime (typ.) 600 V max. 200 mA / 420 mA 10 V – 20 V (IRS213(0,2)D) 13 V – 20 V (IRS21303D) 500 ns 2.0 µs (IRS2130D) 0.7 µs (IRS213(2,03)D) Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives Description Packages The IRS213(0, 03, 2)D are high voltage, high speed power MOSFET and IGBT drivers with three independent high and low side referenced output channels. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 2.5 V logic. A ground-referenced operational amplifier provides analog feedback of bridge 28-Lead SOIC 28-Lead PDIP current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The 44-Lead PLCC w/o 12 Leads floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V. Typical Connection www.irf.com 1 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Zener clamps are included between VCC & VSO (25 V), VCC & VSS (20V), and VBx & VSx (20 V). Symbol VB1,2,3 VS1,2,3 VHO1,2,3 VCC VSS VLO1,2,3 VIN VFLT VCAO VCAdVS/dt PD Definition High side floating supply voltage High side floating offset voltage High side floating output voltage Low side and logic fixed supply voltage Logic ground Low side output voltage Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) FAULT output voltage Operational amplifier output voltage Operational amplifier inverting input voltage Allowable offset supply voltage transient (28 lead PDIP) Package power dissipation @ TA ≤ +25 °C (28 lead SOIC) (44 lead PLCC) (28 lead PDIP) Min. -0.3 VB1,2,3 - 20 VS1,2,3 - 0.3 -0.3 VCC - 20 -0.3 VSS -0.3 VSS -0.3 VSS -0.3 VSS -0.3 — — — — — — — — -55 — Max. 625 VB1,2,3 + 0.3 VB1,2,3 + 0.3 25 VCC + 0.3 VCC + 0.3 (VSS + 15) or (VCC + 0.3), whichever is lower VCC +0.3 VCC +0.3 VCC +0.3 50 1.5 1.6 2.0 83 78 63 150 150 300 Units V V/ns W Rth,JA TJ TS TL Thermal resistance, junction to ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds) (28 lead SOIC) (44 lead PLCC) °C/W °C www.irf.com 2 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested with all supplies biased at a 15 V differential. Symbol VB1,2,3 VS1,2,3 VHO1,2,3 VCC VSS VLO1,2,3 VIN VFLT VCAO VCATA Definition High side floating supply voltage High side floating offset voltage High side floating output voltage Low side and logic fixed supply voltage Logic ground Low side output voltage Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP) FAULT output voltage Operational amplifier output voltage Operational amplifier inverting input voltage Ambient temperature IRS213(0,2)D IRS21303D IRS213(0,2)D IRS21303D Min. VS1,2,3 +10 VS1,2,3 +13 Note 1 VS1,2,3 10 13 -5 0 VSS VSS VSS VSS -40 Max. VS1,2,3 +20 600 VB1,2,3 20 5 VCC VSS + 5 VCC VSS + 5 VSS + 5 125 Units V °C Note 1: Logic operational for VS of (VSO - 8 V) to (VSO + 600 V). Logic state held for VS of (VSO - 8 V) to (VSO – VBS). (Please refer to the Design Tip DT97-3 for more details). Note 2: The CAO pin and all input pins (except CA-) are internally clamped with a 5.2 V zener diode. www.irf.com 3 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Static Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol VIH VIL VIT,TH+ VOH VOL ILK IQBS IQCC IIN+ IINIITRIP+ IITRIPVBSUV+ VBSUVVCCUV+ VCCUVVCCUVH VBSUVH Ron, FLT IO+ IORBS VOS ICACMRR PSRR VOH,AMP VOL,AMP Definition Logic “0” input voltage (OUT = LO) Logic “1” input voltage (OUT = HI) ITRIP input positive going threshold High level output voltage, VBIAS - VO Low level output voltage, VO Offset supply leakage current Quiescent VBS supply current Quiescent VCC supply current Logic “1” input bias current (OUT = HI) Logic “0” input bias current (OUT = LO) “High” ITRIP bias current “Low” ITRIP bias current IRS213(0,2)D VBS supply undervoltage positive going threshold IRS21303D IRS213(0,2)D VBS supply undervoltage negative going threshold IRS21303D IRS213(0,2)D VCC supply undervoltage positive going threshold IRS21303D IRS213(0,2)D VCC supply undervoltage negative going threshold IRS21303D IRS213(0,2)D Hysteresis IRS21303D IRS213(0,2)D Hysteresis IRS21303D FAULT low on-resistance Output high short circuit pulsed current Output low short circuit pulsed current Integrated bootstrap diode resistance Operational amplifier input offset voltage CA- input bias current Operational amplifier common mode rejection ratio Operational amplifier power supply rejection ratio Operational amplifier high level output voltage Operational amplifier low level output voltage Min. Typ. Max. Units Test Conditions 2.2 — 400 — — — — — — — — — 7.5 11 7.1 9 8.3 11 8 9 — — — — 200 420 — — — TBD TBD 4.9 — — — 490 — — — 30 4 300 220 5 — 8.35 — 7.95 — 9 — 8.7 — 0.3 2 0.4 2 55 250 500 200 — — 80 75 5.2 — — 0.8 580 1 400 50 70 6 400 300 100 10 9.2 13 8.8 11 9.7 13 9.4 11 — — — 75 — mA — — 10 50 — dB — 5.4 30 V mV Ω mV nA V mV V mV µA mA µA nA VIN = 0 V, Io= 20 mA VIN = 5 V, Io= 20 mA VB = VS = 600 V VIN = 0 V VIN = 5 V ITRIP = 5 V ITRIP = 0 V V Ω VO = 0 V, VIN = 0 V PW ≤ 10 µs VO = 15 V, VIN = 5 V PW ≤ 10 µs VSO = VCA- = 0.2 V VCA- = 2.5 V VSO = VCA- = 0.1 V & 1.1 V VSO = VCA- = 0.2 V VCC = 10 V & 20 V VCA- = 0 V, VSO =1 V VCA- = 1 V, VSO =0 V Note: Please refer to Feature Description section for integrated bootstrap functionality information. www.irf.com 4 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Static Electrical Characteristics - (Continued) VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol ISRC,AMP ISNK,AMP IO+,AMP IO-,AMP Definition Operational amplifier output source current Operational amplifier output sink current Operational amplifier output high short circuit current Operational amplifier output low short circuit current Min. Typ. Max. Units Test Conditions 4 1 — — 7 2.1 10 4 — — mA — — VCA- = 0 V, VSO =1 V VCAO = 4 V VCA- = 1 V, VSO =0 V VCAO = 2 V VCA- = 0 V, VSO =5 V VCAO = 0 V VCA- = 5 V, VSO =0 V VCAO = 5 V Dynamic Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified. Symbol ton toff tr tf titrip tbl tflt tflt, in tfltclr DT SR+ SR- Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time ITRIP to output shutdown propagation delay ITRIP blanking time ITRIP to FAULT indication delay Min. Typ. Max. Units Test Conditions 400 400 — — 400 — 350 500 500 80 35 660 400 550 700 700 125 55 920 — 870 ns VS1,2,3 = 0 V to 600 V Input filter time (all six inputs) — 325 — LIN1,2,3 to FAULT clear time IRS213(0,2)D 5300 8500 13700 LIN1,2,3 & HIN1,2,3 to FAULT clear time IRS21303D IRS2130D 1300 2000 3100 Deadtime IRS213(2,03)D 500 700 1100 Operational amplifier slew rate (+) 5 10 — Operational amplifier slew rate (-) 2.4 3.2 — V/µs 1 V input step NOTE: For high side PWM, HIN pulse width must be > 1.5 µs. www.irf.com 5 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Fig. 1. Input/Output Timing Diagram Fig. 2. Deadtime Waveform Definitions Fig. 3. Input/Output Switching Time Waveform Definitions www.irf.com 6 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Fig. 4. Overcurrent Shutdown Switching Time Waveform Definitions Fig. 5. Input Filter Function Fig. 6. Diagnostic Feedback Operational Amplifier Circuit www.irf.com 7 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Lead Definitions Symbol HIN1,2,3 LIN1,2,3 FAULT VCC ITRIP CAO CAVSS VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3 VSO Description Logic input for high side gate driver outputs (HO1,2,3), out of phase Logic input for low side gate driver output (LO1,2,3), out of phase Indicates over-current or undervoltage lockout (low side) has occurred, negative logic Low side and logic fixed supply Input for over-current shutdown Output of current amplifier Negative input of current amplifier Logic ground High side floating supply High side gate drive output High side floating supply return Low side gate drive output Low side return and positive input of current amplifier Lead Assignments www.irf.com 8 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Functional Block Diagram www.irf.com 9 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Functional Block Diagram www.irf.com 10 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY at a very high PWM duty cycle due to the bootstrap FET equivalent resistance (RBS, see page 4). In these cases, better performances can be achieved by using the IRS213(0,03,2) non D version with an external bootstrap network. - 1 Features Description 1.1 Integrated Bootstrap Functionality The IRS213(0,03,2)D family embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide range of applications. There is one bootstrap FET for each channel and it is connected between each of the floating supply (VB1, VB2, VB3) and VCC (see Fig. 7). The bootstrap FET of each channel follows the state of the respective low side output stage (i.e., bootFet is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately 1.1(VCC). In that case the bootstrap FET stays off until the VB voltage returns below that threshold (see Fig. 8). 2 PCB Layout Tips 2.1 Distance from H to L Voltage The IRS213(0,03,2)J package lacks some pins (see page 8) in order to maximizing the distance between the high voltage and low voltage pins. It’s strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device (VB1,2,3, VS1,2,3) side. 2.2 Ground Plane To minimize noise coupling ground plane must not be placed under or near the high voltage floating side. 2.3 Gate Drive Loops Current loops behave like an antenna able to receive and transmit EM noise (see Fig. 9). In order to reduce EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-togate parasitic capacitance. The parasitic autoinductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. IGC VBX (V CC ) Fig. 7. Simplified BootFet Connection Vth~17V Vcc=15V gate resistance CGC HO X ( LOX ) Gate Drive Loop Phase voltage LO VGE VSX ( Vs0 ) BootFet ON BootFet OFF BootFet ON Bootstrap FET state Fig. 9. Antenna Loops Fig. 8. State Diagram Bootstrap FET is suitable for most PWM modulation schemes and can be used either in parallel with the external bootstrap network (diode + resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations in the following situations: when used in non-complementary PWM schemes (typically 6-step modulations) 2.4 Supply Capacitors Supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/resistance. www.irf.com 11 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray inductance. See DT04-4 at www.irf.com for more detailed information. 2.5 Routing and Placement Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In particular it’s recommended to limit phase voltage negative transients. www.irf.com 12 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Figures 10-40 provide information on the experimental performance of the IRS2132DS HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 1000 800 600 Exp. Turn-on Propagation Delay (ns) 1200 900 600 Exp. Turn-off Propagation Delay (ns ) 1500 400 200 0 -50 300 0 -50 -25 0 25 50 75 100 125 Temperature (oC) -25 0 25 50 o 75 100 125 Temperature ( C) Fig. 10. Turn-On Propagation Delay vs. Temperature Fig. 11. Turn-Off Propagation Delay vs. Temperature Turn-On Rise Time (ns) Turn-Off fall Time (ns) 250 200 150 100 50 0 -50 -25 0 25 50 o Exp. 125 100 75 50 Exp. 25 0 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) Fig. 12. Turn-On Rise Time vs. Temperature Fig. 13. Turn-Off Fall Time vs. Temperature www.irf.com 13 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY DT Propagation Delay (ns) 1500 1200 900 600 300 0 -50 -25 0 25 50 75 100 125 Temperature (oC) Exp. 1500 1200 TiTRIP Propagation Delay (ns) 900 E xp. 600 300 0 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Fig. 14. DT Propagation Delay vs. Temperature Fig. 15. TITRIP Propagation Delay vs. Temperature ITRIP to FAULT Propagation Delay (ns) FAULT Low On Resistance ( Ohm) 1500 1200 900 Exp. 250 200 150 100 50 Exp. 600 300 0 -50 -25 0 25 50 o 0 -50 -25 0 25 50 o 75 100 125 75 100 125 Temperature ( C) Temperature ( C) Fig. 16. ITRIP to FAULT Propagation Delay vs. Temperature VCC Quiescent Supply Current (mA) VBS Quiescent Supply Current (uA) 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 Temperature (oC) Fig.17. FAULT Low On Resistance vs. Temperature 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 Temperature (oC) Exp. Exp. Fig. 18. VCC Quiescent Current vs. Temperature Fig. 19. VBS Quiescent Current vs. Temperature www.irf.com 14 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY 11 10 9 8 7 6 -50 -25 0 25 50 o Exp. 11 10 9 8 7 6 Exp. VCCUV+ Threshold (V) 75 100 125 VCCUV- Threshold (V) -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) Fig. 20. VCCUV+ Threshold vs. Temperature Fig. 21. VCCUV- Threshold vs. Temperature 11 10 VBSUV+ Threshold (V) VBSUV- Threshold (V) 11 10 9 8 7 6 Exp. 9 8 7 6 -50 -25 0 25 50 o Exp. 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) Fig. 22. VBSUV+ Threshold vs. Temperature Fig. 23. VBSUV- Threshold vs. Temperature ITRIP Positive Going Threshold (mV) 500 EXP. ITRIP Negative Going Threshold (mV) 750 750 500 Exp. 250 250 0 -50 -25 0 25 50 75 100 125 Temperature (oC) 0 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Fig. 24. ITRIP Positive Going Threshold vs. Temperature Fig. 25. ITRIP Negative Going Threshold vs. Temperature www.irf.com 15 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Output Low Short Circuit Current (mA) Output High Short Circuit Pulsed Current (mA) 500 400 300 200 100 0 -50 -25 0 25 50 o 750 600 Exp. 450 300 150 0 -50 -25 0 25 50 o Exp. 75 100 125 75 100 125 Temperature ( C) Temperature ( C) Fig. 26. Output High Short Circuit Pulsed Current vs. Temperature "HIGH" ITRIP Bias Current (uA) "LOW" ITRIP Bias Current (nA) Fig. 27. Output Low Short Circuit Current vs. Temperature 25 20 15 10 Exp. 25 20 15 10 5 Exp. 5 0 0 -50 -25 0 25 50 75 100 125 Temperature (oC) -50 -25 0 25 50 75 100 125 Temperature (oC) Fig. 28. "High" ITRIP Bias Current vs. Temperature Fig. 29. "Low" ITRIP Bias Current vs. Temperature 8 6 VOH,AMP (V) 25 20 Exp. Exp. VOL,AMP (mV) 15 10 5 0 4 2 0 -50 -25 0 25 50 o 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) Fig. 30. VOH,AMP vs. Temperature Fig. 31. VOL,AMP vs. Temperature www.irf.com 16 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY 20 15 SR-,AMP (V/us) 5 4 3 2 1 0 Exp. SR+,AMP (V/us) 10 5 0 Exp. -50 -25 0 25 50 o 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) Fig. 32. SR+,AMP vs. Temperature 5 4 ISNK,AMP (mA) 3 2 1 0 -50 -25 0 25 50 75 100 125 Temperature (oC) Exp. Fig. 33. SR-,AMP vs. Temperature 12 10 ISRC,AMP (mA) 8 6 4 2 0 -50 -25 0 25 50 o Exp. 75 100 125 Temperature ( C) Fig. 34. ISNK,AMP vs. Temperature Fig. 35. ISRC,AMP vs. Temperature 15 12 Exp. 20 16 IO+,AMP (mA) 12 8 Exp. IO-,AMP (mA) 9 6 3 0 -50 -25 0 25 50 o 4 0 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) Fig. 36. IO-,AMP vs. Temperature Fig. 37. IO+,AMP vs. Temperature www.irf.com 17 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY 90 70 VOS,AMP (mV) PSRR (dB) 125 100 Exp. 50 30 10 Exp. 75 50 25 0 -10 -50 -25 0 25 50 o 75 100 125 -50 -25 0 25 50 o 75 100 125 Temperature ( C) Temperature ( C) Fig. 38. VOS,AMP vs. Temperature Fig. 39. PSRR vs. Temperature 150 125 100 CMRR (dB) 75 50 25 0 -50 Exp. -25 0 25 50 o 75 100 125 Temperature ( C) Fig. 40. CMRR vs. Temperature www.irf.com 18 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Case Outlines www.irf.com 19 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Case Outlines www.irf.com 20 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 11.90 12.10 B 3.90 4.10 C 23.70 24.30 D 11.40 11.60 E 10.80 11.00 F 18.20 18.40 G 1.50 n/a H 1.50 1.60 28SOICW Imperial Min Max 0.468 0.476 0.153 0.161 0.933 0.956 0.448 0.456 0.425 0.433 0.716 0.724 0.059 n/a 0.059 0.062 F D C E B A G H REEL DIMENSIONS FOR 28SOICW Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 30.40 n/a 1.196 G 26.50 29.10 1.04 1.145 H 24.40 26.40 0.96 1.039 www.irf.com 21 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY LOADED TAPE FEED DIRECTION B A H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 23.90 24.10 B 3.90 4.10 C 31.70 32.30 D 14.10 14.30 E 17.90 18.10 F 17.90 18.10 G 2.00 n/a H 1.50 1.60 44PLCC Imperial Min Max 0.94 0.948 0.153 0.161 1.248 1.271 0.555 0.562 0.704 0.712 0.704 0.712 0.078 n/a 0.059 0.062 F D C E B A G H REEL DIMENSIONS FOR 44PLCC Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 38.4 G 34.7 35.8 H 32.6 33.1 Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 1.511 1.366 1.409 1.283 1.303 www.irf.com 22 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY ORDER INFORMATION 28-Lead PDIP IRS2130DPbF 28-Lead PDIP IRS21303DPbF 28-Lead PDIP IRS2132DPbF 28-Lead SOIC IRS2130DSPbF 28-Lead SOIC IRS21303DSPbF 28-Lead SOIC IRS2132DSPbF 44-Lead PLCC IRS2132DJPbF 44-Lead PLCC IRS21303DJPbF 44-Lead PLCC IRS2132DJPbF 28-Lead SOIC Tape & Reel IRS2130DSTRPbF 28-Lead SOIC Tape & Reel IRS21303DSTRPbF 28-Lead SOIC Tape & Reel IRS2132DSTRPbF 44-Lead PLCC Tape & Reel IRS2130DJTRPbF 44-Lead PLCC Tape & Reel IRS21303DJTRPbF 44-Lead PLCC Tape & Reel IRS2132DJTRPbF WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105 This part has been qualified per industrial level http://www.irf.com Data and specifications subject to change without notice.5/19/2006 www.irf.com 23