IRS233JPBF

May 8, 2008 IRS233(0,2)(D)(S & J)PbF 3-PHASE-BRIDGE DRIVER Features • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage – dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent half-bridge drivers Matched propagation delay for all channels 3.3 V logic compatible Outputs out of phase with inputs Cross-conduction prevention logic Integrated Operational Amplifier Integrated Bootstrap Diode function (IRS233(0,2)D) RoHS Compliant Product Summary VOFFSET IO+/VOUT ton/off (typ.) Deadtime (typ.) 600V max. 200 mA / 420 mA 10 V – 20 V (233(0,2)(D)) 500 ns 2.0 us (IRS2330(D)) 0.7 us (IRS2332(D)) • • • • • • • • • • • Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives Description The IRS233(0,2)(D)(S & J) is a high voltage, high speed power MOSFET and IGBT driver with three independent high and low side referenced output channels. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 3.3 V logic. A ground-referenced operational amplifier provides analog feedback of bridge current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The floating channel can be used to drive N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Packages 28-Lead SOIC 44-Lead PLCC w/o 12 Leads Typical Connection Absolute Maximum Ratings www.irf.com 1 IRS233(0,2)(D)(S&J)PbF Qualification Information Qualification Level † Industrial†† Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. SOIC28W MSL3†††, 260°C (per IPC/JEDEC J-STD-020) MSL3†††, 245°C (per IPC/JEDEC J-STD-020) Moisture Sensitivity Level PLCC44 Human Body Model ESD Machine Model IC Latch-Up Test RoHS Compliant † †† ††† Class 2 (per JEDEC standard JESD22-A114) Class B (per EIA/JEDEC standard EIA/JESD22-A115) Class I, Level A (per JESD78) Yes Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com 2 IRS233(0,2)(D)(S&J)PbF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB1,2,3 VS1,2,3 VHO1,2,3 VCC VSS VLO1,2,3 Definition High Side Floating Supply Voltage High Side Floating Offset Voltage High Side Floating Output Voltage Low Side and Logic Fixed Supply Voltage Logic Ground Low Side Output Voltage _______ ______ Logic Input Voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) FAULT Output Voltage Operational Amplifier Output Voltage Operational Amplifier Inverting Input Voltage Allowable Offset Supply Voltage Transient Package Power Dissipation @ TA ≤ +25 °C Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (soldering, 10 seconds) (28 lead SOIC) (44 lead PLCC) (28 lead SOIC) (44 lead PLCC) Min. -0.3 VB1,2,3 - 20 VS1,2,3 - 0.3 -0.3 VCC - 20 -0.3 VSS -0.3 VSS -0.3 VSS -0.3 VSS -0.3 — — — — — — -55 — Max. 620 VB1,2,3 + 0.3 VB1,2,3 + 0.3 20 VCC + 0.3 VCC + 0.3 (VSS + 15) or (VCC + 0.3) Whichever is lower VCC +0.3 VCC +0.3 VCC +0.3 50 1.6 2.0 78 63 150 150 300 Units V VIN VFLT VCAO VCAdVS/dt PD RthJA TJ TS TL V/ns W °C/W °C www.irf.com 3 IRS233(0,2)(D)(S&J)PbF Recommended Operating Conditions The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested with all supplies biased at 15 V differential. Symbol VB1,2,3 VS1,2,3 VSt1,2,3 VHO1,2,3 VCC VSS VLO1,2,3 VIN VFLT VCAO VCATA Definition High Side Floating Supply Voltage Static High side floating offset voltage Transient High side floating offset voltage High Side Floating Output Voltage Low Side and Logic Fixed Supply Voltage Logic Ground Low Side Output Voltage Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP) FAULT Output Voltage Operational Amplifier Output Voltage Operational Amplifier Inverting Input Voltage Ambient temperature Min. VS1,2,3 +10 VSO-8 (Note1) -50 (Note2) VS1,2,3 10 -5 0 VSS VSS VSS VSS -40 Max. VS1,2,3 +20 600 600 VB1,2,3 20 5 VCC VSS + 5 VCC VSS + 5 VSS + 5 125 Units V °C Note 1: Logic operational for VS of (VSO -8 V) to (VSO +600 V). Logic state held for VS of (VSO -8 V) to (VSO – VBS). Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to the Application Information section of this datasheet for more details. Note 3: CAO input pin is internally clamped with a 5.2 V zener diode. Dynamic Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified. Symbol ton toff tr tf titrip tbl tflt tflt, in tfltclr DT MDT Definition Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time ITRIP to Output Shutdown Propagation Delay ITRIP Blanking Time ITRIP to FAULT Indication Delay Input Filter Time (All Six Inputs) LIN1,2,3 to FAULT Clear Time (2330/2) Deadtime: Deadtime matching: : (IRS2330(D)) (IRS2332(D)) (IRS2330(D)) (IRS2332(D)) Min Typ Max Units Test Conditions 400 400 — — 400 — 350 — 500 500 80 35 660 400 550 325 700 700 125 55 920 — 870 — ns VIN = 0 V & 5 V without external deadtime VIN = 0 V & 5 V without external deadtime larger than DT PM input 10 µs VS1,2,3 = 0 V to 600 V VS1,2,3 = 0 V 5300 8500 13700 1300 2000 3100 500 700 1100 — — 400 — — 140 — — — — 50 75 MT PM Delay matching time (t ON , t OFF) Pulse width distortion NOTE: For high side PWM, HIN pulse width must be > 1.5 usec www.irf.com 4 IRS233(0,2)(D)(S&J)PbF Dynamic Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified. Symbol SR+ SR- Definition Operational Amplifier Slew Rate (+) Operational Amplifier Slew Rate (-) Min Typ Max Units Test Conditions 5 2.4 10 3.2 — — V/µs 1 V input step www.irf.com 5 IRS233(0,2)(D)(S&J)PbF Static Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol VIH VIL VIT,TH+ VOH VOL ILK IQBS IQCC IIN+ IINIITRIP+ IITRIPVBSUV+ VBSUVVCCUV+ VCCUVVCCUVH VBSUVH Ron, FLT IO+ IORBS VOS ICACMRR PSRR VOH,AMP VOL,AMP Definition Logic “0” input Voltage (OUT = LO) Logic “1” input Voltage (OUT = HI) ITRIP Input Positive Going Threshold High Level Output Voltage, VBIAS - VO Low Level Output Voltage, VO Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current Logic “1” Input Bias Current (OUT =HI) Logic “0” Input Bias Current (OUT = LO) “High” ITRIP Bias Current “LOW” ITRIP Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive going Threshold VCC Supply Undervoltage Negative Going Threshold Hysteresis Hysteresis FAULT Low On-Resistance Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current Integrated Bootstrap Diode resistance Operational Amplifier Input Offset Voltage CA- Input Bias Current Operational Amplifier Common Mode Rejection Ratio Operational Amplifier Power Supply Rejection Ratio Operational Amplifier High Level Output Voltage Operational Amplifier Low Level Output Voltage Min Typ Max Units Test Conditions — 0.8 400 — — — — — — — 490 — — — 30 4 2.2 — 580 1000 400 50 50 6.2 µA mA µA nA V mV VIN = 0 V, IO = 20 mA VIN = 5 V, IO = 20 mA VB = VS = 600 V VIN = 0 V or 4 V VIN = 0 V VIN = 0 V VIN = 4 V ITRIP = 4 V ITRIP = 0 V -400 -300 -100 -300 -220 -100 — 5 10 — — 30 7.5 7.1 8.3 8 — — — — 420 — — — — — 4.8 — 8.35 7.95 9 8.7 0.3 0.4 55 -250 500 200 — — 80 75 5.2 — 9.2 8.8 9.7 9.4 — — 75 -180 V Ω mA VO = 0 V, VIN = 0 V PW ≤ 10 us VO = 15 V, VIN = 5 V PW ≤ 10 us VSO = 0.2 V VCA- = 1 V VSO = 0.1 V & 5 V VSO = 0.2 V VCC = 9.7 V & 20 V VCA- = 0 V, VSO =1 V VCA- = 1 V, VSO =0 V — — 20 100 — dB — 5.6 40 V mV Ω mV nA Note: The integrated bootstrap diode does not work well with the trapezoidal control. www.irf.com 6 IRS233(0,2)(D)(S&J)PbF Static Electrical Characteristics- Continued VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol ISRC,AMP ISNK,AMP IO+,AMP IO-,AMP Definition Operational Amplifier Output Source Current Operational Amplifier Output Sink Current Operational Amplifier Output High Short Circuit Current Operational Amplifier Output Low Short Circuit Current Min Typ Max Units Test Conditions — 1 -30 — -7 2.1 -10 4 -4 — mA — — VCA- = 0 V, VSO =1 V VCAO = 4 V VCA- = 1 V, VSO =0 V VCAO = 2 V VCA- = 0 V, VSO =5 V VCAO = 0 V VCA- = 5 V, VSO =0 V VCAO = 5 V Functional Block Diagram IRS2330D/IRS2332D HIN1 HIN2 HIN3 LIN1 LIN2 LIN3 FAULT CLEAR LOGIC C FAULT LOGIC S INPUT SIGNAL GENERATOR H3 L3 PULSE GENERATOR LEVEL SHIFTER SET INPUT SIGNAL GENERATOR INPUT SIGNAL GENERATOR H1 L1 PULSE GENERATOR LEVEL SHIFTER SET LATCH UV DETECTOR DRIVER VB1 HO1 VS1 Integrated BS Diode RESET H2 L2 PULSE GENERATOR LEVEL SHIFTER SET LATCH DRIVER VB2 HO2 VS2 Integrated BS Diode UV RESET DETECTOR LATCH UV DETECTOR DRIVER VB3 HO3 VS3 Integrated BS Diode RESET VCC DRIVER ITRIP 0.5V CURRENT COMPARATOR UNDER VOLTAGE DETECTOR DRIVER LO2 LO1 CAO CURRENT AMP CADRIVER LO3 VSO VSS Note: IRS2330 & IRS2332 are without integrated bootstrap diode. www.irf.com 7 IRS233(0,2)(D)(S&J)PbF Lead Definitions Symbol HIN1,2,3 LIN1,2,3 FAULT VCC ITRIP CAO CAVSS VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3 VSO Description Logic input for high side gate driver outputs (HO1,2,3), out of phase Logic input for low side gate driver output (LO1,2,3), out of phase Indicates over-current or undervoltage lockout (low side) has occurred, negative logic Low side and logic fixed supply Input for over-current shutdown Output of current amplifier Negative input of current amplifier Logic Ground High side floating supply High side gate drive output High side floating supply return Low side gate drive output Low side return and positive input of current amplifier Lead Assignments www.irf.com 8 IRS233(0,2)(D)(S&J)PbF Application Information and Additional Details Information regarding the following topics are included as subsections within this section of the datasheet. • • • • • • • • • • • • • • • • • • • • IGBT/MOSFET Gate Drive Switching and Timing Relationships Deadtime Matched Propagation Delays Input Logic Compatibility Undervoltage Lockout Protection Shoot-Through Protection Fault Reporting Over-Current Protection Over-Temperature Shutdown Protection Truth Table: Undervoltage lockout, ITRIP Advanced Input Filter Short-Pulse / Noise Rejection Integrated Bootstrap Functionality Bootstrap Power Supply Design Separate Logic and Power Grounds Negative VS Transient SOA DC- bus Current Sensing PCB Layout Tips Additional Documentation IGBT/MOSFET Gate Drive The IRS233(2,0)(D) HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the highside power switch and VLO for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage. Figure 1: HVIC sourcing current Figure 2: HVIC sinking current www.irf.com 9 IRS233(0,2)(D)(S&J)PbF Switching and Timing Relationships The relationship between the input and output signals of the IRS233(0,2)(D) are illustrated below in Figures 3. From these figures, we can see the definitions of several timing parameters (i.e., PWIN, PWOUT, tON, tOFF, tR, and tF) associated with this device. LINx (or HINx) 50% PWIN 50% tON tR 90% 10% PWOUT tOFF 90% tF LOx (or HOx) 10% Figure 3: Switching time waveforms The following two figures illustrate the timing relationships of some of the functionality of the IRS233(0,2)(D); this functionality is described in further detail later in this document. During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output are held in the off state. Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault condition is latched until the all LINx become high. www.irf.com 10 IRS233(0,2)(D)(S&J)PbF Figure 4: Input/output timing diagram Deadtime This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals. The deadtime circuitry of the IRS233(0,2)(D) is matched with respect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. LINx HINx 50% 50% DT 50% LOx HOx 50% DT Figure 5: Illustration of deadtime www.irf.com 11 IRS233(0,2)(D)(S&J)PbF Matched Propagation Delays The IRS233(0,2)(D) family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the lowside channels and the high-side channels. Additionally, the propagation delay for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the high-side channels are matched with each other. The propagation turn-on delay (tON) of the IRS233(0,2)(D) is matched to the propagation turn-on delay (tOFF). Input Logic Compatibility The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS233(0,2)(D) family has been designed to be compatible with 3.3 V and 5 V logic-level signals. The IRS233(0,2)(D) features an integrated 5.2 V Zener clamp on the HIN, LIN, and ITRIP pins. Figure 6 illustrates an input signal to the IRS233(0,2)(D), its input threshold values, and the logic state of the IC as a result of the input signal. Figure 6: HIN & LIN input thresholds Undervoltage Lockout Protection This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS (high-side circuitry) power supply. Figure 7 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled. Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the fault condition. Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the IC. The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure. www.irf.com 12 IRS233(0,2)(D)(S&J)PbF Figure 7: UVLO protection Shoot-Through Protection The IRS233(0,2)(D) family of high-voltage ICs is equipped with shoot-through protection circuitry (also known as crossconduction prevention circuitry). Figure 8 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Note that the IRS233(0,2)(D) has inverting inputs (the output is out-of-phase with its respective input). Shoot-through protection enabled HIN LIN HO LO Figure 8: Illustration of shoot-through protection circuitry IRS233(0,2)(D) HIN 0 0 1 1 LIN 0 1 0 1 HO 0 1 0 0 LO 0 0 1 0 Table 1: Input/output truth table www.irf.com 13 IRS233(0,2)(D)(S&J)PbF Fault Reporting The IRS233(0,2)(D) family provides an integrated fault reporting output. There are two situations that would cause the HVIC to report a fault via the FAULT pin. The first is an undervoltage condition of VCC and the second is if the ITRIP pin recognizes a fault. Once the fault condition occurs, the FAULT pin is internally pulled to VSS and the fault condition is latched. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. Over-Current Protection The IRS233(0,2)(D) HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is reported through the FAULT pin. The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R0, R1, and R2) connected to ITRIP as shown in Figure 9, and the ITRIP threshold (VIT,TH+). The circuit designer will need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the voltage at node VX reaches the over-current threshold (VIT,TH+) at that current level. VIT,TH+ = R0IDC-(R1/(R1+R2)) Vcc HIN(x3) VB ( x3) LIN(x3) HO( x3) FAULT VS (x3) ITRIP VSS LO(x3) COM R1 R2 R0 IDC- Figure 9: Programming the over-current protection For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5 V; if necessary, an external voltage clamp may be used. Over-Temperature Shutdown Protection The ITRIP input of the IRS233(0,2)(D) can also be used to detect over-temperature events in the system and initiate a shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to design the resistor network as shown in Figure 10 and select the maximum allowable temperature. This network consists of a thermistor and two standard resistors R3 and R4. As the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node VX. The resistor values should be selected such the voltage VX should reach the threshold voltage (VIT,TH+) of the ITRIP functionality by the time that the maximum allowable temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V. When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g., DL4148) can be used. This network is shown in Figure 11; the OR-ing diodes have been labeled D1 and D2. www.irf.com 14 IRS233(0,2)(D)(S&J)PbF Figure 10: Programming over-temperature protection Figure 11: Using over-current protection and over-temperature protection Truth Table: Undervoltage lockout and ITRIP Table 2 provides the truth table for the IRS233(0,2)(D). The first line shows that the UVLO for VCC has been tripped; the FAULT output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case and when VCC is greater than VCCUV, the FAULT output returns to the high impedance state. The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new falling transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the FAULT pin will return to VCC. VCC