IS41C85125-35KI

IS41C85125 IS41LV85125 512K x 8 (4-MBIT) DYNAMIC RAM WITH FAST PAGE MODE FEATURES • • • • Fast access and cycle time TTL compatible inputs and outputs Refresh Interval: 1024 cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • Single power supply: -- 5V ± 10% (IS41C85125) -- 3.3V ± 10% (IS41LV85125) • Industrial temperature available ISSI DESCRIPTION ® PRELIMINARY INFORMATION AUGUST 2001 The ISSI IS41C85125 and IS41LV85125 are 512,288 x 8-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1024 random accesses within a single row with access cycle time as short as 12 ns per 8-bit word. These features make the IS41C85125 and the IS41LV85125 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C85125 and IS41LV85125 are available in a 28-pin, 400-mil SOJ package. KEY TIMING PARAMETERS Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -60 60 15 30 25 110 Unit ns ns ns ns ns PIN CONFIGURATION 28-Pin SOJ VCC I/O0 I/O1 I/O2 I/O3 NC WE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND I/O7 I/O6 I/O5 I/O4 CAS OE NC A8 A7 A6 A5 A4 GND PIN DESCRIPTIONS A0-A9 I/O0-I/O7 WE OE RAS CAS VCC GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 1 IS41C85125 IS41LV85125 FUNCTIONAL BLOCK DIAGRAM ISSI ® OE WE CAS CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC OE RAS CAS WE RAS RAS CLOCK GENERATOR DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS REFRESH COUNTER DATA I/O BUFFERS I/O0-I/O7 ROW DECODER ADDRESS BUFFERS A0-A9 MEMORY ARRAY 512,288 x 8 TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write Hidden Refresh Read Write(1) RAS-Only Refresh CBR Refresh Notes: 1. EARLY WRITE only. RAS H L L L L→H→L L→H→L L H→L CAS H L L L L L H L WE X H L H→L H L X X OE X L X L→H L X X X Address tR/tC X ROW/COL ROW/COL ROW/COL ROW/COL ROW/COL ROW/NA X I/O High-Z DOUT DIN DOUT, DIN DOUT DOUT High-Z High-Z 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 FUNCTIONAL DESCRIPTION The IS41C85125 and IS41LV85125 are CMOS DRAMs optimized for high-speed bandwidth, low-power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 19 address bits. The first ten address bits (A0-A9) are entered as row address and latter nine address bits (A0-A8) are entered as column address. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ten bits of row address and CAS is used to latch the latter nine bits of column address. ISSI Refresh Cycle ® at or before the falling edge of CAS or WE, whichever occurs last. To retain data, 1024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory: 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Memory Cycle A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensure proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 3 IS41C85125 IS41LV85125 ABSOLUTE MAXIMUM RATINGS(1) Symbol VT VCC IOUT PD TA TSTG Parameters Voltage on Any Pin Relative to GND Supply Voltage Output Current Power Dissipation Operation Temperature Storage Temperature 5V 3.3V 5V 3.3V Rating –1.0 to +7.0 –0.5 t0 +4.6 –1.0 to +7.0 –0.5 t0 +4.6 50 1 0 to 70 –40 to +85 –55 to +125 Unit V V mA W °C °C ISSI ® Com. Ind. Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND) Symbol VCC VCC VIH VIH VIL VIL TA Parameter Supply Voltage Supply Voltage Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Ambient Temperature Voltage 5V 3.3V 5V 3.3V 5V 3.3 Com. Ind. Min. 4.5 3.0 2.4 2.0 –1.0 –0.3 0 –40 Typ. 5.0 3.3 — — — — — — Max. 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 Unit V V V V V V °C CAPACITANCE(1,2) Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A9 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O7 Max. 5 7 7 Unit pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.) Symbol IIL IIO VOH VOL ICC1 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Stand-by Current: TTL Test Condition Any input 0V ≤ VIN ≤ Vcc Other inputs not under test = 0V Output is disabled (Hi-Z) 0V ≤ VOUT ≤ Vcc IOH = –2.5 mA IOL = 2.1 mA RAS, CAS ≥ VIH 5V 5V 3.3V 3.3V 5V 3.3V Com. Ind. Com. Ind. Speed Min. –10 –10 2.4 — — — — — — — — — — — — — — — ISSI Max. 10 10 — 0.4 2 3 1 2 2 1 230 170 220 160 230 170 230 170 µA µA V V mA ® Unit ICC2 ICC3 Stand-by Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current Refresh Current: CBR (2,3,5) Average Power Supply Current RAS, CAS ≥ VCC – 0.2V mA mA RAS, CAS, Address Cycling, tRC = tRC (min.) RAS = VIL, CAS, Cycling tPC = tPC (min.) RAS Cycling, CAS ≥ VIH tRC = tRC (min.) RAS, CAS Cycling tRC = tRC (min.) -35 -60 -35 -60 -35 -60 -35 -60 ICC4 mA ICC5 mA ICC6 mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured.The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each fast page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 5 IS41C85125 IS41LV85125 ISSI -35 -60 Max. — 35 10 18 10K — 10K — — 28 — — — — — 20 — — — — — 15 10 — — — — — — — — Min. 110 — — — 60 40 10 10 60 20 0 10 0 10 40 15 30 0 15 3 5 3 — 10 10 5 0 0 0 10 50 Max. — 60 15 30 10K — 10K — — 45 — — — — — 30 — — — — — 15 15 — — — — — — — — Min. 60 — — — 35 20 6 5 35 11 0 6 0 6 30 12 18 0 8 3 5 3 — 10 10 5 0 0 0 5 30 ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol t RC t RAC t CAC t AA t RAS t RP t CAS t CP t CSH t RCD t ASR t RAH t ASC t CAH t AR t RAD t RAL t RPC t RSH t CLZ t CRP t OD tOE t OEHC tOEP tOES t RCS t RRH t RCH t WCH t WCR Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued) 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 ISSI -35 -60 Max. — — — — — — — — — — — — — — — 100K 21 — 15 15 — — — — 16 50 Min. 10 10 15 15 0 40 15 15 0 10 140 80 36 49 25 60 — 56 3 3 10 10 10 0 — 1 Max. — — — — — — — — — — — — — — — 100K 34 — 15 15 — — — — 16 50 Min. 5 10 8 8 0 30 15 8 0 6 80 45 25 30 12 35 — 40 3 3 10 8 8 0 — 1 ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol tWP tWPZ tRWL tCWL tWCS t DHR t ACH tOEH t DS t DH t RWC t RWD t CWD tAWD t PC tRASP tCPA tPRWC tOFF tWHZ t CLCH t CSR t CHR tORD tREF tT Parameter Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width Access Time from CAS Precharge(15) READ-WRITE Cycle Time(24) Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Refresh Period (1024 Cycles) Transition Time (Rise or Fall)(2, 3) Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 7 IS41C85125 IS41LV85125 ISSI ® Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD • tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • tRWD (MIN), tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless of CAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 AC WAVEFORMS FAST-PAGE-MODE READ CYCLE tRC tRAS tRP ISSI ® RAS tCSH tCRP tRCD tRSH tCAS tCLCH tRRH CAS tAR tRAD tASR tRAH tASC tRAL tCAH ADDRESS WE Row tRCS Column tRCH Row tAA tRAC tCAC tCLC tOFF(1) I/O OE Open tOE Valid Data tOD Open tOES Don't Care Note: 1. tOFF is referenced from rising edge of CAS. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 9 IS41C85125 IS41LV85125 FAST PAGE MODE READ-MODIFY-WRITE CYCLE ISSI tRASP tRP ® RAS tCSH tCAS tCRP tRCD tCP tPRWC tCAS tCP tRSH tCAS tCRP CAS tAR tRAH tASR tRAD tASC tCAH tCPWD tASC tAR tCWL tRWD tAWD tCWD tCAH tCPWD tRAL tCAH tASC ADDRESS Row Column Column tCWL tAWD tCWD Column tCWL tRWL tWP tAWD tCWD tRCS tWP tWP WE tAA tCAC tCAC tOEA tOEA tAA tCAC tOEA tAA OE tRAC tCLZ tOEZ tOED tDH tDS tCLZ OUT IN OUT tOEZ tOED tDH tDS IN tOEZ tOED tDH tCLZ OUT IN tDS I/O Don't Care 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 FAST-PAGE-MODE EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP ISSI ® RAS tCSH tCRP tRCD tRSH tCAS tCLCH CAS tAR tASR tRAD tRAH tASC tRAL tCAH tACH ADDRESS Row Column tCWL tRWL tWCR tWCS tWCH tWP Row WE tDHR tDS tDH I/O Valid Data Don't Care Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 11 IS41C85125 IS41LV85125 ISSI tRWC tRAS tRP ® FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS tCSH tCRP tRCD tRSH tCAS tCLCH CAS tAR tRAD tASR tRAH tASC tCAH tACH tRAL ADDRESS Row tRCS Column tRWD tCWD tAWD Row tCWL tRWL tWP WE tAA tRAC tCAC tCLZ tDS tDH I/O Open tOE Valid DOUT tOD Valid DIN Open tOEH OE Don't Care 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 FAST PAGE MODE EARLY WRITE CYCLE tRASP ISSI tRP tRHCP tRSH tCAS tCP tCRP ® RAS tCSH tCAS tCRP tRCD tCP tPC tCAS CAS tAR tRAL tRAH tASR tRAD tASC tCAH tASC tAR tCWL tWCS tWP tWCH tWCS tWP tCAH tASC tCAH ADDRESS Row Column Column tCWL tWCH tWCS Column tCWL tWCH tWP WE tWCR OE tDHR tDS tDH tDS tDH tDS tDH I/O Valid DIN Valid DIN Valid DIN Don't Care Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 13 IS41C85125 IS41LV85125 READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCAS tCP ISSI ® CAS tAR tASR tRAD tRAH tASC tCAH tASC ADDRESS WE Row tRCS Column tRCH tRCS Column tAA tRAC tCAC tCLZ tWHZ tCLZ I/O OE Open tOE Valid Data Open tOD Don't Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS tASR tRAH ADDRESS I/O Row Open Row Don't Care 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01 IS41C85125 IS41LV85125 CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) ISSI tRP tRAS tRP tRAS ® RAS tRPC tCP tCHR tCSR tRPC tCSR tCHR CAS I/O Open HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR CAS tAR tASR tRAD tRAH tASC tRAL tCAH ADDRESS Row Column tAA tRAC tCAC tCLZ tOFF(2) I/O Open tOE tORD Valid Data Open tOD OE Don't Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION 09/25/01 Rev. 00A 15 IS41C85125 IS41LV85125 ORDERING INFORMATION IS41C85125 Commercial Range: 0⋅ C to 70⋅ C Speed (ns) Order Part No. 35 60 IS41C85125-35K IS41C85125-60K Package 28-pin, 400-mil SOJ 28-pin, 400-mil SOJ ISSI IS41LV85125 Commercial Range: 0⋅ C to 70⋅ C Speed (ns) Order Part No. 35 60 IS41LV85125-35K IS41LV85125-60K Package 28-pin, 400-mil SOJ 28-pin, 400-mil SOJ ® Industrial Range: –40⋅ C to 85⋅ C Speed (ns) Order Part No. 35 60 IS41C85125-35KI IS41C85125-60KI Package 28-pin, 400-mil SOJ 28-pin, 400-mil SOJ Industrial Range: –40⋅ C to 85⋅ C Speed (ns) Order Part No. 60 Package IS41LV85125-60KI 28-pin, 400-mil SOJ ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00A 09/25/01