IS42S32200B
512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length: (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Self refresh modes • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Industrial temperature availability • Package 400-mil 86-pin TSOP II • Lead free package is available
ISSI
®
PRELIMINARY INFORMATION September 2003
OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S32200B is
organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve highspeed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATION
(86-Pin TSOP (Type II)
VDD DQ0 VDDQ DQ1 DQ2 GNDQ DQ3 DQ4 VDDQ DQ5 DQ6 GNDQ DQ7 NC VDD DQM0 WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 GNDQ DQ17 DQ18 VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 GND DQ15 GNDQ DQ14 DQ13 VDDQ DQ12 DQ11 GNDQ DQ10 DQ9 VDDQ DQ8 NC GND DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 GND NC DQ31 VDDQ DQ30 DQ29 GNDQ DQ28 DQ27 VDDQ DQ26 DQ25 GNDQ DQ24 GND
PIN DESCRIPTIONS
A0-A10 BA0, BA1 DQ0 to DQ31 CLK CKE CS RAS CAS WE Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command Write Enable
DQ19 DQ20 GNDQ DQ21 DQ22 VDDQ DQ23 VDD
VDD GND VDDQ GNDQ NC
Power Ground Power Supply for DQ Pin Ground for DQ Pin No Connection
DQM0 to DQM3 Input/Output Mask
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
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I S42S32200B
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE
ISSI
®
function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A10 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE
DQM0-3 COMMAND DECODER & CLOCK GENERATOR
DATA IN BUFFER
32 32
MODE REGISTER
10
REFRESH CONTROLLER
DQ 0-31
SELF REFRESH CONTROLLER
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1
10
DATA OUT BUFFER
32 32
VDD/VDDQ GND/GNDQ
REFRESH COUNTER
2048 2048 2048 2048
ROW DECODER
MULTIPLEXER
MEMORY CELL ARRAY
10
ROW ADDRESS LATCH
10
ROW ADDRESS BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN ADDRESS LATCH
256 (x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN ADDRESS BUFFER
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PIN FUNCTIONS
Symbol A0-A10 Pin No. 25 to 27 60 to 66 24 Type Input Pin Function (In Detail)
ISSI
Address Inputs: A0-A10 are sampled during the ACTIVE command (row-address A0-A10) and READ/WRITE command (A0-A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands.
®
BA0, BA1 CAS CKE
22,23 18 67
Input Pin Input Pin Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units using the DQM0-DQM3 pins
CLK CS
68 20
Input Pin Input Pin
DQ0 to 2, 4, 5, 7, 8, 10,11,13 DQ31 74,76,77,79,80,82,83,85 45,47,48,50,51,53,54,56 31,33,34,36,37,39,40,42 DQM0 DQM3 16,28,59,71
DQ Pin
Input Pin
DQMx control thel ower and upper bytes of the DQ buffers. In read mode, the output buffers are place in a High-Z state. During a WRITE cycle the input data is masked. When DQMx is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. DQ0 through DQ7 are controlled by DQM0. DQ8 throughDQ15 are controlled by DQM1. DQ16 through DQ23 are controlled by DQM2. DQ24 through DQ31 are controlled by DQM3. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VDDQ is the output buffer power supply. VDD is the device internal power supply. GNDQ is the output buffer ground. GND is the device internal ground.
RAS WE VDDQ VDD GNDQ GND
19 17 3,9,35,41,49,55,25,81 1,15,29,43 6,12,32,38,46,52,78,84 44,58,72,86
Input Pin Input Pin Supply Pin Supply Pin Supply Pin Supply Pin
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FUNCTION (In Detail)
A0-A10 are address inputs sampled during the ACTIVE (row-address A0-A10) and READ/WRITE command (A0-A7 with A10 defining auto PRECHARGE). A10 is sampled during a PRECHARGE command to determine if all banks are to be PRECHARGED (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address (BA0 and BA1) defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the “Command Truth Table” for details on device commands. The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, CLOCK SUSPEND mode, or SELF-REFRESH mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQ0 through DQ7 are controlled by DQM0. DQ8 through DQ15 are controlled by DQM1. DQ16 through DQ23 are controlled by DQM2. DQ24 through DQ31 are controlled by DQM3. In read mode, DQMx control the output buffer. When DQMx is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH Impedance State when DQMx is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, DQMx control the input buffer. When DQMx is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When DQMx is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE , forms the device command. See the “Command Truth Table” item for details on device commands. WE , in conjunction with RAS and CAS , forms the device command. See the “Command Truth Table” item for details on device commands. VDDQ is the output buffer power supply. VDD is the device internal power supply. GNDQ is the output buffer ground. GND is the device internal ground.
ISSI
READ
®
The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’s will be High-Z two clocks later. DQ’s will provide valid data when the DQM signal was registered LOW.
WRITE
A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7. Whether or not AUTO-PRECHARGE is used is determined by A10. The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. A memory array is written with corresponding input data on DQ’s and DQM input logic level appearing at the same time. Data will be written to memory when DQM signal is LOW. When DQM is HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0, BA1 can be used to select which bank is precharged or they are treated as “Don’t Care”. A10 determined whether one or all banks are precharged. After executing this command, the next command for the selected banks(s) is executed after passage of the period tRP, which is the period required for bank precharging. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst. This function allows for individual-bank precharge without requiring an explicit command. A10 to enables the AUTO PRECHARGE function in conjunction with a specific READ or WRITE command. For each individual READ or WRITE command, auto precharge is either
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enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed.
ISSI
BURST TERMINATE
®
AUTO REFRESH COMMAND
This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generated during this operation. The stipulated period (tRC) is required for a single refresh operation, and no other commands can be executed during this period. This command is executed at least 4096 times every 64ms. During an AUTO REFRESH command, address bits are “Don’t Care”. This command corresponds to CBR Auto-refresh.
The BURST TERMINATE command forcibly terminates the burst read and write operations by truncating either fixed-length or full-page bursts and the most recently registered READ or WRITE command prior to the BURST TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents new commands from being executed. Operations in progress are not affected, apart from whether the CLK signal is enabled
NO OPERATION
When CS is low, the NOP command prevents unwanted commands from being registered during idle or wait states.
SELF REFRESH
During the SELF REFRESH operation, the row address to be refreshed, the bank, and the refresh interval are generated automatically internally. SELF REFRESH can be used to retain data in the SDRAM without external clocking, even if the rest of the system is powered down. The SELF REFRESH operation is started by dropping the CKE pin from HIGH to LOW. During the SELF REFRESH operation all other inputs to the SDRAM become “Don’t Care”.The device must remain in self refresh mode for a minimum period equal to tRAS or may remain in self refresh mode for an indefinite period beyond that.The SELFREFRESH operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins.The next command cannot be executed until the device internal recovery period (tRC) has elapsed. Once CKE goes HIGH, the NOP command must be issued (minimum of two clocks) to provide time for the completion of any internal refresh in progress. After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an AUTO-REFRESH should immediately be performed for all addresses.
LOAD MODE REGISTER
During the LOAD MODE REGSITER command the mode register is loaded from A0-A10. This command can only be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputs on A0-A10 selects the row. Until a PRECHARGE command is issued to the bank, the row remains open for accesses.
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TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row)
(3) (4) (4)
ISSI
CS H L L L L L
(5)
®
RAS X H L H H H L L L — —
CAS X H H L L H H L L — —
WE X H H H L L L H L — —
DQM X X X L/H(8) L/H(8) X X X X L H
ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code — —
DQs X X X X Valid Active X X X Active High-Z
READ (Select bank/column, start READ burst) BURST TERMINATE
WRITE (Select bank/column, start WRITE burst)
PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER
(2) (8) (6,7)
L L L — —
Write Enable/Output Enable Write Inhibit/Output High-Z
(8)
NOTES: 1. CKE is HIGH for all commands except SELF REFRESH. 2. A0-A10 define the op-code written to the mode register. 3. A0-A10 provide row address, and BA0, BA1 determine which bank is made active. 4. A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables auto precharge; BA0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and DQs are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
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TRUTH TABLE – CKE (1-4)
CURRENT STATE Power-Down Self Refresh Clock Suspend Power-Down Self Refresh
(5) (6) (7)
ISSI
COMMANDn X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOP X COMMAND INHIBIT or NOP AUTO REFRESH VALID ACTIONn Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry CKEn-1 L L L L L L H H H H CKEn L L L H H H L L L H
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Clock Suspend All Banks Idle All Banks Idle
Reading or Writing
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
NOTES: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on clock edges occurring during the tXSR period. A minimum of two NOP commands must be sent during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1.
TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENT STATE Any Idle COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH(7) LOAD MODE REGISTER(7) PRECHARGE Row Active
(11) (10)
CS RAS CAS WE H L L L L L L L L L L L L
(10) (10) (10) (8)
X H L L L L H H L H H L H H H L H
X H H L L H L L H L L H H L L H H
X H H H L L H L L H L L L H L L L 7
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)(10) PRECHARGE (Deactivate row in bank or banks) Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) WRITE (Select column and start WRITE burst) BURST TERMINATE
(9)
READ (Select column and start new READ burst)
(10)
PRECHARGE (Truncate READ burst, start PRECHARGE)(8) READ (Select column and start READ burst)
L L L L
WRITE (Select column and start new WRITE burst) BURST TERMINATE(9)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8)
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®
NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after tXSR has been met (if the previous state was SELF REFRESH). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and CURRENT STATE BANK n truth tables. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank.
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TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m (1-6)
CURRENT STATE Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE(9) ACTIVE (Select and activate row) READ (Select column and start READ burst) PRECHARGE(9) ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE(9) ACTIVE (Select and activate row) READ (Select column and start READ burst) PRECHARGE(9)
(7,8,16) (7,8,17) (7,8,14) (7,8,15) (7,12) (7,13) (7,10) (7,11) (7) (7)
ISSI
H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L
®
CS RAS CAS WE
WRITE (Select column and start WRITE burst)
WRITE (Select column and start new WRITE burst)
WRITE (Select column and start new WRITE burst)
NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved.
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®
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted by bank m’s burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Consecutive READ Bursts). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Fig CAP 3). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where t WR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4).
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I S42S32200B
FUNCTIONAL DESCRIPTION
The 64Mb SDRAMs 512K x 32 x 4 banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
ISSI
Initialization
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SDRAMs must be powered up and initialized in a predefined manner. The 64M SDRAM is initialized after the power is applied to VDD and VDDQ (simultaneously) and the clock is stable. A 100µs delay is required prior to issuing any command other than a COMMAND INHIBIT or a NOP. The COMMAND INHIBIT or NOP may be applied during the 100us period and continue should at least through the end of the period. With at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied once the 100µs delay has been satisfied. All banks must be precharged. This will leave all banks in an idle idle state where two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SRDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power up in an unknown state.
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REGISTER DEFINITION Mode Register
The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS\ latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information
ISSI
®
until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4- M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 and M12 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
MODE REGISTER DEFINITION
BA0,1
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
(1)
0
(1)
Burst Type M3Type 0 1 Sequential Interleaved B urst Length M2 M1 M0 0 0 0 0 1 1 1 1 Latency Mode M6 M5 M4 0 0 0 0 1 1 1 1 MRS M8 M7 0 — 0 — MRS Mode Register Set All Other States Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sequential 1 2 4 8 Reserved Reserved Reserved Full Page Interleave 1 2 4 8 Reserved Reserved Reserved Reserved
Write Burst Mode M9 0 1 Mode Burst Write Single-Bit Write
Note: 1. Maintain low during Mode Register Set.
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Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected.
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All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 (x32) when the burst length is set to two; by A2-A7 (x32) when the burst length is set to four; and by A3-A7 (x32) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table.
BURST DEFINITION
Burst Length 2 A1 0 4 0 1 1 A2 0 0 0 8 0 1 1 1 1 Full Page (y) n = A0-A7 (location 0-y) A1 0 0 1 1 0 0 1 1 Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... …Cn - 1, Cn… 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1 1-0 0-1 1-0 Order of Accesses Within a Burst Type = Sequential Type = Interleaved
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CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.
CAS Latency Allowable Operating Frequency (MHz)
Speed 6 7 CAS Latency = 2 — 100 CAS Latency = 3 166 143
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are
CAS Latency
T0 CLK T1 T2 T3
COMMAND DQ
READ
NOP tAC
NOP DOUT
tLZ CAS Latency - 2
tOH
T0 CLK
T1
T2
T3
T4
COMMAND DQ
READ
NOP
NOP tAC
NOP DOUT
tLZ CAS Latency - 3
tOH
DON'T CARE UNDEFINED
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OPERATION BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. Minimum tRCD should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in the following example, which covers any case where 2 < [tRCD (MIN)/tCK] ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
CLK CKE CS RAS CAS WE A0-A10 BA0, BA1 ROW ADDRESS BANK ADDRESS HIGH - Z
ISSI
Activating Specific Row Within Specific Bank
®
Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] ≤ 3
T0 CLK
T1
T2
T3
T4
COMMAND
ACTIVE
NOP tRCD
NOP
READ or WRITE
DON'T CARE
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READS
READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. The CAS Latency diagram shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Consecutive READ Bursts for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Random READ Accesses, or each subsequent READ may be performed to a different bank. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that DQ contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. 16
ISSI
READ COMMAND
CLK CKE CS RAS CAS WE A0-A7 A8, A9
AUTO PRECHARGE COLUMN ADDRESS HIGH-Z
®
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
The DQM input is used to avoid DQ contention, as shown in Figures RW1 and RW2. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure RW2, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure RW1 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure RW2 shows the case where the additional NOP is needed. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the
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same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE diagram for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the
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PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ Burst Termination diagram for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.
CAS Latency
T0 CLK
T1
T2
T3
COMMAND DQ
READ
NOP tAC
NOP DOUT
tLZ CAS Latency - 2
tOH
T0 CLK
T1
T2
T3
T4
COMMAND DQ
READ
NOP
NOP tAC
NOP DOUT
tLZ CAS Latency - 3
tOH
DON'T CARE UNDEFINED
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Consecutive READ Bursts
ISSI
T0 T1 T2 T3 T4 T5 T6
®
CLK
COMMAND
READ
NOP
NOP
NOP
READ x =1 cycle
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP x = 2 cycles
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DOUT b
DON'T CARE
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Random READ Accesses
ISSI
T0 CLK T1 T2 T3 T4 T5
®
COMMAND
READ
READ
READ
READ
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ CAS Latency - 2
DOUT n
DOUT b
DOUT m
DOUT x
DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ CAS Latency - 3
DOUT n
DOUT b
DOUT m
DOUT x
DON'T CARE
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RW1 - READ to WRITE
ISSI
T0 CLK T1 T2 T3 T4
®
DQM
COMMAND
READ
NOP
NOP
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ CAS Lantency 3
tHZ DOUT n
DIN b tDS DON'T CARE
RW2 - READ to WRITE With Extra Clock Cycle
T0 CLK
T1
T2
T3
T4
T5
DQM
COMMAND
READ
NOP
NOP
NOP
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ
tHZ DOUT n
DIN b tDS
CAS Lantency 3
DON'T CARE
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READ to PRECHARGE
ISSI
®
T0 CLK
T1
T2
T3
T4
T5 tRP
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
x = 1 cycle
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
T0 CLK
T1
T2
T3
T4
T5 tRP
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP x = 2 cycles
NOP
ACTIVE
ADDRESS
BANK, COL n
BANK, COL b
BANK a, ROW
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
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READ Burst Termination
ISSI
®
T0 CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP
NOP
x = 1 cycle
ADDRESS
BANK a, COL n
DQ CAS Latency - 2
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
T0 CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
BURST TERMINATE
NOP x = 2 cycles
NOP
NOP
ADDRESS
BANK, COL n
DQ CAS Latency - 3
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
DON'T CARE
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WRITEs
WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram.
ISSI
®
WRITE Command
CLK CKE CS RAS CAS WE A0-A7 A8, A9
AUTO PRECHARGE COLUMN ADDRESS HIGH - Z
A10
NO PRECHARGE
BA0, BA1
BANK ADDRESS
The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see WRITE Burst). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command.
An example is shown in WRITE to WRITE diagram. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Random WRITE Cycles, or each subsequent WRITE may be performed to a different bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a subsequent READ command. Once the READ com mand is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in WRITE to READ. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be fol lowed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in the WRITE to PRECHARGE diagram. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in WRITE Burst Termination, where data n is the last desired data element of a longer burst. 23
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WRITE Burst
T0 CLK T1 T2 T3
ISSI
®
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK, COL n
DQ
DIN n
DIN n+1
Burst length = 2 DQM ix low.
DON'T CARE
WRITE to WRITE
T0 CLK T1 T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DIN b
DQMx is low. Each Write Command may be to any bank.
DON'T CARE
Random WRITE Cycles
T0 CLK T1 T2 T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK, COL n
BANK, COL b
BANK, COL m
BANK, COL x
DQ
DIN n
DIN b
DIN m
DIN x
DQMx is low. Each Write Command may be to any bank. 24
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WRITE to READ
ISSI
T0 CLK T1 T2 T3 T4 T5
®
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK, COL n
BANK, COL b
DQ
DIN n
DIN n+1
DOUT b
DOUT b+1
DON'T CARE
WRITE to PRECHARGE (tWR = 1 CLK (tCK ≥ tWR)
T0 CLK T1 T2 T3 T4 T5 T6
DQM tRP COMMAND WRITE NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
tWR DQ DIN n DIN n+1 DON'T CARE
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WRITE to PRECHARGE (tWR = 2 CLK (tWR > tCK)
T0 CLK T1 T2 T3 T4 T5 T6
ISSI
®
DQM tRP COMMAND WRITE NOP NOP
PRECHARGE
NOP
NOP
ACTIVE
ADDRESS
BANK a, COL n
BANK (a or all)
BANK a, ROW
tWR DQ DIN n DIN n+1 DON'T CARE
WRITE Burst Termination
T0 CLK T1 T2
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK, COL n
(ADDRESS)
DQ
DIN n
(DATA)
DON'T CARE
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PRECHARGE
The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.
ISSI
PRECHARGE Command
CLK
HIGH - Z
®
CKE CS RAS CAS WE A0-A9
ALL BANKS
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if powerdown occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See figure below.
A10
BANK SELECT
BA0, BA1
BANK ADDRESS
POWER-DOWN
CLK tCKS CKE ≥ tCKS
COMMAND
NOP Input buffers gated off
NOP
ACTIVE tRCD tRAS tRC DON'T CARE
All banks idle
Enter power-down mode
Exit power-down mode
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27
I S42S32200B
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended.
ISSI
®
Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See following examples.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.
Clock Suspend During WRITE Burst
T0 CLK T1 T2 T3 T4 T5
CKE
INTERNAL CLOCK COMMAND NOP WRITE NOP NOP
ADDRESS
BANK a, COL n
DQ
DIN n
DIN n+1
DIN n+2 DON'T CARE
Burst Length 4 or greater DQM is low.
Clock Suspend During WRITE Burst
T0 CLK T1 T2 T3 T4 T5 T6
CKE
INTERNAL CLOCK COMMAND READ NOP NOP NOP NOP NOP
ADDRESS
BANK a, COL n
DQ
DIN n
DIN n+1
DIN n+2
DIN n+3 DON'T CARE
CAS Latency=2. Burst Length =4 or greater. DQM is low. 28
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I S42S32200B
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).
ISSI
READ with Auto Precharge
®
SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered. 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
T0 CLK COMMAND NOP
READ - AP BANK n
T1
T2
T3
T4
T5
T6
T7
NOP
READ - AP BANK m
NOP
NOP
NOP
NOP
BANK n
Page Active
READ with Burst of 4
Interrupt Burst, Precharge tRP - BANK n
Idle tRP - BANK m Precharge
Internal States
BANK m Page Active
BANK n, COL a BANK m, COL b
READ with Burst of 4
ADDRESS DQ
DOUT a CAS Latency - 3 (BANK n)
DOUT a+1
DOUT b
DOUT b+1 DON'T CARE
CAS Latency - 3 (BANK m)
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
T0 CLK COMMAND
Read - AP BANK n
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
WRITE - AP BANK m
NOP
NOP
NOP
BANK n
READ with Burst of 4 Page Active Page Active
BANK n, COL a BANK m, COL b
Interrupt Burst, Precharge tRP - BANK n WRITE with Burst of 4
Idle tRP - BANK m Write-Back
Internal States
BANK m ADDRESS DQM DQ
DOUT a CAS Latency - 3 (BANK n)
DIN b
DIN b+1
DIN b+2
DIN b+3 DON'T CARE
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I S42S32200B
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
ISSI
®
4. Interrupted by a WRITE (with or without auto precharge): AWRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0 CLK T1 T2 T3 T4 T5 T6 T7
COMMAND
NOP
WRITE - AP BANK n
NOP
READ - AP BANK m
NOP
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m Precharge
Internal States
BANK m Page Active
READ with Burst of 4
ADDRESS
BANK n, COL a
BANK m, COL b
DQ
DIN a
DIN a+1 CAS Latency - 3 (BANK m)
DOUT b
DOUT b+1 DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0 CLK T1 T2 T3 T4 T5 T6 T7
COMMAND
NOP
WRITE - AP BANK n
NOP
NOP
WRITE - AP BANK m
NOP
NOP
NOP
BANK n
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back tWR - BANK n
Precharge tRP - BANK n tRP - BANK m Write-Back
Internal States
BANK m Page Active
WRITE with Burst of 4
ADDRESS
BANK n, COL a
BANK m, COL b
DQ
DIN a
DIN a+1
DIN a+2
DIN b
DIN b+1
DIN b+2
DIN b+3 DON'T CARE
30
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I S42S32200B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD MAX VDDQ MAX VIN VOUT PD MAX ICS TOPR TSTG Parameters Maximum Supply Voltage Maximum Supply Voltage for Output Buffer Input Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Com. Ind. Storage Temperature Rating –1.0 to +4.6 –1.0 to +4.6 –1.0 to +4.6 –1.0 to +4.6 1 50 0 to +70 –40 to +85 –55 to +150 Unit V V V V W mA °C °C
ISSI
®
DC RECOMMENDED OPERATING CONDITIONS(2,5) (At TA = 0 to +70°C)
Symbol VDD, VDDQ VIH VIL Parameter Supply Voltage Input High Voltage(3) Input Low Voltage(4) Min. 3.0 2.0 -0.3 Typ. 3.3 — — Max. 3.6 VDD + 0.3 +0.8 Unit V V V
CAPACITANCE CHARACTERISTICS(1,2) (At TA = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol CIN1 CIN2 CI/O Parameter Input Capacitance: A0-A10, BA0, BA1 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) Data Input/Output Capacitance: DQ0-DQ31 Typ. — — — Max. 4 4 5 Unit pF pF pF
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to GND. 3. VIH (max) = VDDQ + 2.0V with a pulse width ≤ 3 ns. The pluse width cannot be greater than one third of the cycle rate. 4. VIL (min) = GND – 2.0V with a pulse < 3 ns. The pluse width cannot be greater than one third of the cycle rate. 5. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated anytime the tREF refresh requirement is exceeded.
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I S42S32200B
ISSI
Test Condition 0V ≤ VIN ≤ VDD, with pins other than the tested pin at 0V Output is disabled 0V ≤ VOUT ≤ VDD IOUT = –2 mA IOUT = +2 mA One Bank Operation, Burst Length=1 tRC ≥ tRC (min.) IOUT = 0mA CKE ≤ VIL (MAX) CKE ≥ VIH (MIN) CAS latency = 3 -6 -7 S p e e d Min. – 5 – 5 2.4 — — — Max. 5 5 — 0.4 150 130 µA µA V V mA mA
®
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter IIL IOL V OH VOL I CC1 Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Operating Current(1,2) Unit
ICC2P ICC2PS ICC2N I CC2NS I CC3P ICC3PS ICC3N ICC3NS ICC4
Precharge Standby Current (In Power-Down Mode) Precharge Standby Current (In Non Power-Down Mode) Active Standby Current (In Power-Down Mode) Active Standby Current (In Non Power-Down Mode) Operating Current (In Burst Mode)(1)
CKE ≤ VIL (MAX)
CKE ≥ VIH (MIN)
tCK = tCK (MIN) IOUT = 0mA
tCK = tCK (MIN) tCK = ∞ tCK = tCK (MIN) tCK = ∞ Com. Ind. tCK = tCK (MIN) Com. Ind. tCK = ∞ Com. Ind. tCK = tCK (MIN) tCK = ∞ Com. Ind. CAS latency = 3
— — — — — — — — — — — — -6 -7 -6 -7 -6 -7 -6 -7 —
— — — — — — — — — — — — — — — — — — — — —
3 2 45 30 35 7 8 6 7 70 60 65 185 180 180 180 185 160 185 180 1.5
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
CAS latency = 2
ICC5
Auto-Refresh Current
tRC = tRC (MIN)
CAS latency = 3
CAS latency = 2
I CC6
Self-Refresh Current
CKE ≤ 0.2V
Notes: 1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
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I S42S32200B
(1,2,3)
ISSI
-6 Min. Max. CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 6 10 — — 2.5 2.5 2 1
(5)
®
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter tCK3 tCK2 tAC3 tAC2 tCHI tCL tOH tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKA tCS tCH tRC tRAS tRP tRCD tRRD Clock Cycle Time Access Time From CLK(4) CLK HIGH Level Width CLK LOW Level Width Output Data Hold Time Output LOW Impedance Time
-7 Min. Max. 7 10 — — 3 3 2 1 — — 2 1 1.5 1 2 1 2 1 70 20 20 14 — — 6.5 8 — — — — 5.5 8 — — — — — — — — — — — —
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
— — 5.5 7.5 — — — — 5.5 7.5 — — — — — — — — — — — —
Output HIGH Impedance Time CAS Latency = 3 CAS Latency = 2 Input Data Setup Time Input Data Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time CKE to CLK Recovery Delay Time Command Setup Time (CS, RAS, CAS, WE, DQM) Command Hold Time (CS, RAS, CAS, WE, DQM) Command Period (REF to REF / ACT to ACT) Command Period (ACT to PRE) Command Period (PRE to ACT) Active Command To Read / Write Command Delay Time Command Period (ACT [0] to ACT[1])
— — 1.5 1 1.5 1 1.5 1 1.5 1 60 18 18 12
1CLK+6 —
1CLK+7 —
42 120,000
48 120,000
Notes: 1. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated anytime the tREF refresh requirement is exceeded. 2. Measured with tT = 1 ns. 3. The reference level is 1.5V when measuring input signal timing. Rise/fall times are measured between VIH (min.) and VIL (max.). 4. Access time is measured at 1.5V with the load shown in the figure below. 5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.) when the output is in the high impedance state. 6. CLK must be toggled a minimum of two times during this period.
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I S42S32200B
AC ELECTRICAL CHARACTERISTICS
Symbol Parameter tDPL3 tDPL2 tDAL3 tDAL2 tWR tXSR tRFC tREF Input Data To Precharge Command Delay time CAS Latency = 3 CAS Latency = 2 Input Data To Active / Refresh CAS Latency = 3 Command Delay time (During Auto-Precharge) CAS Latency = 2
(2)
ISSI
(1,2,3)
®
-6 Min. 2CLK 2CLK 2CLK+tRP 2CLK+tRP 0.3 1CLK+6ns
(6)
-7 Max. — — — — 1.2 — — — 64 Min. 2CLK 2CLK 2CLK+tRP 2CLK+tRP 0.3 1CLK+7ns 70 70 — Max. — — — — 1.2 — — — 64 Units ns ns ns ns ns tCK ns ns ms
tT Transition Time
Write Recovery Time Exit Self Refresh and Active Command Auto Refresh Period Refresh Cycle Time (4096)
70 60 —
Notes: 1. An initial pause of 100us is required after power up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (Vdd and VddQ must be powered up simultaneously. GND and GNDQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated anytime the tREF refresh requirement is exceeded. 2. Measured with tT = 1 ns. 3. The reference level is 1.5V when measuring input signal timing. Rise/fall times are measured between VIH (min.) and VIL (max.). 6. CLK must be toggled a minimum of two times during this period.
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I S42S32200B
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL — — tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH PARAMETER Clock Cycle Time Operating Frequency READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 CL=3 CL=2 -6 6 166 1 1 1 0 0 2 0 5 4 2 1 1 2 2 3 2 -7 7 143 1 1 1 0 0 2 0 5 4 2 1 1 2 2 3 2
ISSI
UNITS ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
®
AC TEST CONDITIONS (Input/Output Reference Level: 1.5V) Input Load Output Load
tCK tCHI
2.75V
tCL
CLK 1.5V
0.25V
50 Ω
tCS tCH
I/O 30 pF
+1.5V
2.75V
INPUT 1.5V
0.25V
tOH OUTPUT
1.5V
tAC
1.5V
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I S42S32200B
INITIALIZE AND LOAD MODE REGISTER
ISSI
®
T0 CLK tCK tCKS tCKH CKE tCMH tCMS COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 DQ T Power-up: VCC and CLK stable T = 100µs Min. NOP
T1
Tn+1 tCH
To+1 tCL
Tp+1
Tp+2
Tp+3
tCMH tCMS PRECHARGE
tCMH tCMS
AUTO REFRESH
NOP
AUTO REFRESH
NOP
Load MODE REGISTER
NOP
ACTIVE
tAS tAH CODE tAS tAH CODE SINGLE BANK ALL BANKS BANK ROW ROW
ALL BANKS
tRP Precharge all banks
tRFC AUTO REFRESH
tRFC AUTO REFRESH
tMRD Program MODE REGISTER DON'T CARE
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I S42S32200B
POWER-DOWN MODE CYCLE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 ROW A10 ALL BANKS ROW BA0, BA1 DQ SINGLE BANK tAS tAH BANK High-Z Two clock cycles Precharge all active banks All banks idle, enter power-down mode Input buffers gated off while in power-down mode All banks idle BANK PRECHARGE NOP NOP NOP ACTIVE tCK T1 tCL tCKS T2 tCH tCKS Tn+1 Tn+2
ISSI
®
Exit power-down mode
DON'T CARE
CAS latency = 2, 3
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I S42S32200B
CLOCK SUSPEND MODE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 tAS tAH COLUMN m(2) tAS tAH tAS tAH BANK DQ tLZ tAC DOUT m tOH tAC tHZ DOUT m+1 BANK tDS tDH DIN N COLUMN n READ NOP tCMS tCMH NOP NOP NOP NOP WRITE tCK T1 tCL T2 tCH tCKS tCKH T3 T4 T5 T6 T7 T8
ISSI
T9
®
NOP
DIN N +1 DON'T CARE UNDEFINED
CAS latency = 2, burst length = 2
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I S42S32200B
AUTO-REFRESH CYCLE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 BA0, BA1 DQ ALL BANKS PRECHARGE NOP
Auto Refresh
ISSI
T1 tCK tCL T2 tCH Tn+1 To+1
®
NOP
Auto Refresh
NOP
ACTIVE
ROW ROW SINGLE BANK BANK(s) tAS tAH High-Z tRP tRFC tRFC DON'T CARE BANK
CAS latency = 2, 3
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I S42S32200B
SELF-REFRESH CYCLE
ISSI
T0 T1 tCK tCH tCL tCKS ≥ tRAS tCKS NOP
Auto Refresh
®
T2
Tn+1
To+1
To+2
CLK
tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9 A10 ALL BANKS SINGLE BANK tAS tAH BANK DQ High-Z tRP Precharge all active banks
CAS latency = 2, 3
PRECHARGE
NOP
NOP
Auto Refresh
BA0, BA1
tXSR CLK stable prior to exiting Exit self refresh mode self refresh mode (Restart refresh time base) DON'T CARE
Enter self refresh mode
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I S42S32200B
READ WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC tLZ CAS Latency ROW tAS tAH ROW tAS tAH BANK COLUMN m ALL BANKS ACTIVE NOP READ tCMS tCMH NOP NOP NOP PRECHARGE NOP tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8
ISSI
®
ACTIVE
ROW ROW
DISABLE AUTO PRECHARGE BANK tAC tAC DOUT m tOH tAC DOUT m+1 tOH
SINGLE BANK BANK tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH DON'T CARE UNDEFINED BANK
CAS latency = 2, Burst Length = 4
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I S42S32200B
READ WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC tLZ CAS Latency ROW tAS tAH ROW tAS tAH BANK BANK tAC tAC DOUT m tOH tAC DOUT m+1 tOH tAC DOUT m+2 tOH tRP tHZ DOUT m+3 tOH COLUMN m) ENABLE AUTO PRECHARGE ACTIVE NOP READ tCMS tCMH NOP NOP NOP NOP NOP tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8
ISSI
®
ACTIVE
ROW ROW BANK
DON'T CARE UNDEFINED
CAS latency = 2, Burst Length = 4
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I S42S32200B
SINGLE READ WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC tLZ CAS Latency ROW tAS tAH ROW tAS tAH BANK COLUMN m ALL BANKS ROW DISABLE AUTO PRECHARGE BANK tAC tOH DOUT m tHZ SINGLE BANK BANK BANK ROW ACTIVE NOP READ tCMS tCMH NOP NOP PRECHARGE NOP ACTIVE tCK T1 tCL T2 tCH T3 T4 T5 T6 T7
ISSI
T8
®
NOP
DON'T CARE tRP UNDEFINED
CAS latency = 2, Burst Length = 1
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I S42S32200B
SINGLE READ WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9, A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK BANK tAC DQ tRCD tRAS tRC CAS Latency tRP tOH DOUT m tHZ COLUMN m ENABLE AUTO PRECHARGE ROW BANK ROW
ACTIVE NOP NOP NOP READ NOP NOP ACTIVE
ISSI
T1 tCK tCL T2 tCH T3 T4 T5 T6 T7 T8
®
NOP
tCMS tCMH
DON'T CARE UNDEFINED
CAS latency = 2, Burst Length = 1
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I S42S32200B
ALTERNATING BANK READ ACCESSES
ISSI
T1 tCK tCL T2 tCH T3 T4 T5 T6 T7 T8
®
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 ACTIVE
NOP
READ tCMS tCMH
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
COLUMN m ENABLE AUTO PRECHARGE
ROW ROW
COLUMN b(2) ENABLE AUTO PRECHARGE
ROW ROW
BANK 0 tLZ
BANK 3 tOH DOUT m tAC tAC tOH DOUT m+1 tAC
BANK 3 tOH DOUT m+2 tAC tRP - BANK 0 tRCD - BANK 3 CAS Latency - BANK 3 tOH DOUT m+3 tAC
BANK 0 tOH DOUT b tAC tRCD - BANK 0
DQ
tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0
CAS Latency - BANK 0
DON'T CARE
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I S42S32200B
READ - FULL-PAGE BURST
ISSI
T1 tCK tCL T2 tCH T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4
®
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 A0-A9, A10 BA0, BA1 tAS tAH
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
tCMS tCMH
ROW tAS tAH ROW tAS tAH BANK
COLUMN m
BANK tAC tLZ tRCD CAS Latency DOUT m tOH tAC tAC DOUT m+1 tOH each row (x32) has 256 locations tAC DOUT m+2 tOH tAC DOUT m-1 tOH tAC DOUT m tOH tHZ DOUT m+1 tOH DON'T CARE Full-page burst not self-terminating. Use BURST TERMINATE command. UNDEFINED
DQ
Full page completion
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Rev. 00C 09/29/03
I S42S32200B
READ - DQM OPERATION
ISSI
T0 T1 tCK tCL T2 tCH T3 T4 T5 T6 T7 T8
®
CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 tAH ACTIVE
NOP
READ tCMS tCMH
NOP
NOP
NOP
NOP
NOP
NOP
ROW tAS tAH ROW tAS tAH BANK
COLUMN m
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK tAC tOH DOUT m tHZ tLZ tAC tOH DOUT m+2 tAC tOH DOUT m+3 tHZ DON'T CARE UNDEFINED
DQ tLZ tRCD CAS Latency
CAS Latency = 2, Burst Length = 4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
47
I S42S32200B
WRITE - WITHOUT AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK COLUMN m ALL BANKS ACTIVE NOP WRITE tCMS tCMH NOP NOP NOP PRECHARGE NOP tCK T1 tCL T2 tCH T3 T4 T5 T6 T7
ISSI
T8
®
ACTIVE
ROW ROW
DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH
SINGLE BANK BANK BANK
DQ tRCD tRAS tRC
DIN m
DIN m+3 tWR tRP
DON'T CARE
Burst Length = 4
48
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
I S42S32200B
WRITE - WITH AUTO PRECHARGE
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 DQ tRCD tRAS tRC ROW tAS tAH ROW tAS tAH BANK BANK tDS tDH tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH COLUMN m ENABLE AUTO PRECHARGE ACTIVE NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP NOP tCK T1 tCL T2 tCH T3 T4 T5 T6 T7 T8
ISSI
T9
®
ACTIVE
ROW ROW BANK
DIN m
DIN m+3 tWR tRP
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
49
I S42S32200B
SINGLE WRITE - WITHOUT AUTO PRECHARGE
ISSI
T0 T1 tCK tCL T2 tCH T3 T4 T5 T6 T7 T8
®
CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK ACTIVE
NOP
WRITE tCMS tCMH
NOP
NOP
PRECHARGE
NOP
ACTIVE
NOP
COLUMN m
ROW
ALL BANKS
ROW
DISABLE AUTO PRECHARGE SINGLE BANK
BANK tDS tDH
BANK
BANK
DQ tRCD tRAS tRC
DIN m tWR tRP DON'T CARE
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
I S42S32200B
SINGLE WRITE - WITH AUTO PRECHARGE
ISSI
®
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 tAH ACTIVE tCK
T1 tCL
T2 tCH
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
WRITE tCMS tCMH
NOP
NOP
NOP
ACTIVE
NOP
ROW tAS tAH ROW tAS tAH BANK
COLUMN m ENABLE AUTO PRECHARGE
ROW ROW
BANK tDS tDH
BANK
DQ tRCD tRAS tRC
DIN m tWR tRP DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
51
I S42S32200B
ISSI
T1 tCK tCL T2 tCH T3 T4 T5 T6 T7 T8 T9
®
ALTERNATING BANK WRITE ACCESS
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK 0 BANK 0 tDS DQ tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 tDH tDS tDH DIN m+1 COLUMN m ENABLE AUTO PRECHARGE ROW BANK 1 tDS tDH DIN m+2 tDS tDH BANK 1 tDS tDH DIN b tDS tDH tDS tDH ROW COLUMN b ENABLE AUTO PRECHARGE ROW BANK 0 tDS tDH ROW ACTIVE NOP WRITE tCMS tCMH NOP ACTIVE NOP WRITE NOP NOP ACTIVE
DIN m
DIN m+3
DIN b+1
DIN b+2
DIN b+3 tRCD - BANK 0 tWR - BANK 1
tWR - BANK 0 tRCD - BANK 1
tRP - BANK 0
DON'T CARE
52
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
I S42S32200B
WRITE - FULL PAGE BURST
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS A0-A9 A10 BA0, BA1 tAH COLUMN m
ACTIVE NOP WRITE NOP NOP NOP NOP
ISSI
T1 tCK tCL T2 tCH T3 T4 T5 Tn+1 Tn+2
®
BURST TERM
NOP
tCMS tCMH
ROW tAS tAH ROW tAS tAH BANK
BANK tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH DIN m tRCD DIN m+1 DIN m+2 DIN m+3
256 locations within same row
DQ
DIN m-1
Full-page burst does not self-terminate. Can use BURST TERMINATE to stop.
Full page completed
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
53
I S42S32200B
WRITE - DQM OPERATION
T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND DQM0-DQM3 tAS tAH A0-A9 A10 BA0, BA1 ROW tAS tAH ROW tAS tAH BANK COLUMN m
ENABLE AUTO PRECHARGE
ISSI
T1 tCK tCL T2 tCH T3 T4 T5 T6 T7
®
ACTIVE
NOP
WRITE tCMS tCMH
NOP
NOP
NOP
NOP
NOP
DISABLE AUTO PRECHARGE
BANK tDS tDH tDS tDH DIN m+2 tDS tDH DIN m tRCD DIN m+3 DON'T CARE
DQ
54
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
I S42S32200B
ORDERING INFORMATION Commercial Range: 0°C to 70°C
Frequency 166 MHz 166 MHz 143 MHz 143 MHz Speed (ns) 6 6 7 7 Order Part No. IS42S32200B-6T IS42S32200B-6TL IS42S32200B-7T IS42S32200B-7TL Package 400-mil TSOP II
ISSI
®
400-mil TSOP II, Lead free 400-mil TSOP II 400-mil TSOP II, Lead free
Industrial Range: -40°C to 85°C
Frequency 166 MHz 166 MHz 143 MHz 143 MHz Speed (ns) 6 6 7 7 Order Part No. IS42S32200B-6TI IS42S32200B-6TLI IS42S32200B-7TI IS42S32200B-7TLI Package 400-mil TSOP II 400-mil TSOP II, Lead free 400-mil TSOP II 400-mil TSOP II, Lead free
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C 09/29/03
55
PACKAGING INFORMATION
Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II)
ISSI
N/2+1 E1 E
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be
®
N
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
1 D
N/2
SEATING PLANE
ZD
A
e
b
L A1
α
C
Symbol Ref. Std. No. Leads (N) A A1 A2 b C D E1 E e L L1 ZD α
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 54 — 0.047 0.002 0.006 — — 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 — — 0° 8°
Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 86 A A1 A2 b C D E1 E e L L1 ZD α — 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.12 0.21 22.02 22.42 10.16 BSC 11.56 11.96 0.50 BSC 0.40 0.60 0.80 REF 0.61 REF 0° 8° — 0.047 0.002 0.006 0.037 0.041 0.007 0.011 0.005 0.008 0.867 0.8827 0.400 BSC 0.455 0.471 0.020 BSC 0.016 0.024 0.031 REF 0.024 BSC 0° 8°
— 1.20 0.05 0.15 — — 0.30 0.45 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 — — 0.71 REF 0° 8°
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C 01/28/02
1
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