IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
ISSI
November 2005
®
256 Mb Synchronous DRAM
DESCRIPTION
IS42S83200A is a synchronous 256Mb SDRAM and is organized as 4-bank x 8,388,608-word x 8-bit; and IS42S16160A is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
IS42S83200A and IS42S16160A achieve very high speed clock rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.
FEATURES
ITEM
tCLK Clock Cycle Time (Min.) CL=2 CL=3
IS42S83200A/16160A
-6
6 42 15 CL=2 CL=3
-7
7 45 20 5.4 63
-75
10 7.5 45 20 6 5.4 67.5 110
Unit ns ns ns ns ns ns ns mA mA mA
tRAS Active to Precharge Command Period (Min.) (Min.) tRCD Row to Column Delay tAC tRC Icc1 Icc6 Access Time from CLK Ref /Active Command Period Operation Current (Single Bank) Self Refresh Current (Max.) (Min.) (Max.)
IS42S83200A IS42S16160A
-
5 60
130 3
130 3
3
(Max.) -6,-7,-75
- Single 3.3V ±0.3V power supply - Max. Clock frequency: -6:166MHz -7:143MHz -75:133MHz - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- DQML and DQMU (IS42S16160A) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto and self refresh - 8192 refresh cycles /64ms(4 banks concurrent refresh) - LVTTL Interface - Row address A0-12 /Column address A0-9(x8) / A0-8(x16) - Package: 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch - Lead-free available
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
1
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
PIN CONFIGURATION (TOP VIEW)
x8 x16
Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
400mil x 875mil 54pin 0.8mm pitch TSOP(II)
CLK CKE /CS /RAS /CAS /WE DQ0-15
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe : Write Enable : Data I/O
DQM, DQMU/L A0-12 BA0,1 Vdd VddQ Vss VssQ
: Output Disable / Write Mask : Address Input : Bank Address Input : Power Supply : Power Supply for Output
: Ground
: Ground for Output
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
BLOCK DIAGRAM
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
DQ0-7
I /O Buffer
M emory Array
8 192x1024x8 Cell Array
M emory Array
8192x1024x8 Cell Array
M emory Array
8192x1024x8 Cell Array
M emory Array
8192x1024x8 Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-12
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
Note:This figure shows the IS42S83200A The IS42S16160A configuration is 8192x512x16 of cell array and DQ0-15
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
3
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
PIN FUNCTION
CLK
I nput
Master Clock: All other inputs are referenced to the rising edge of CLK C lock Enable: CKE controls internal clock.When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self-refresh. After self-refresh mode is started, CKE becomes asynchronous input. Self-refresh is maintained as long as CKE is low. C hip Select: When /CS is high, any command means No Operation. C ombination of /RAS, /CAS, /WE defines basic commands. A 0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8)/A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. B ank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE , READ , WRITE commands.
C KE
I nput
/CS /RAS, /CAS, /WE
I nput I nput
A 0-12
I nput
B A0,1
I nput
DQ0-7(x8), DQ0-15(x16) DQM(x8), DQMU/L(x16) V dd, Vss V ddQ, VssQ
I nput / Output D ata In and Data out are referenced to the rising edge of CLK.
D in Mask / Output Disable: When DQM(U/L) is high in burst write, Din for the current cycle is masked. When DQM(U/L) is high in burst read, Dout is disabled at the next but one cycle. P ower Supply for the memory array and peripheral circuitry.
I nput
P ower Supply
P ower Supply V ddQ and VssQ are supplied to the Output Buffers only.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
BASIC FUNCTIONS
The IS42S83200A/16160A provides basic
functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh.
Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals,
/CS, CKE and A10 are used as chip select, refresh opt ion,
and precharge option, respectively .
To know the detailed definition of commands,
please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A 10
Chip Select : L=select, H=deselect C ommand C ommand C ommand Refresh Option @ refresh command Precharge Option @ precharge or read/write command
define basic command
A ctivate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
R ead (READ) [/RAS =H, /CAS =L, /WE =H]
R EAD command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, R EADA ).
W rite (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA ).
P recharge (PRE) [/RAS =L, /CAS =H, /WE =L]
P RE command deactivates the active bank indicated by BA. This com mand also terminates burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all, P REA ) .
A uto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
R EFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
5
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
/CS H L L L L L /RAS X H L L L H /CAS X H H H H L /WE BA0,1 X H H L L L X X V V X V A10 /AP X X V L H L A0-9, 11-12 X X V X X V note
®
COMMAND TRUTH TABLE
COMMAND
Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set
MNEMONIC
DESEL NOP ACT PRE PREA WRITE
CKE n-1 H H H H H H
CKE n X X X X X X
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA REFA REFS REFSX TBST MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
H X X X X X L
V X X X X X V 1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-9,11-12=L, A0-A6 =Mode Address
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Command DESEL NOP TBST NOP NOP ILLEGAL*2 Action
®
FUNCTION TRUTH TABLE
Current State /CS H L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L L L L L H H L L L H L H L BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add /RAS X H H H L L L L X H H H H L L L L X H H H /CAS X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 Address
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
7
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Command DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
®
FUNCTION TRUTH TABLE (continued)
Current State /CS H L L L /RAS X H H H /CAS X H H L /WE X H L H X X X BA, CA, A10 Address
Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
WRITE
L L L L L H L L L L L L L L H L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
READ with AUTO PRECHARGE
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
WRITE with AUTO PRECHARGE
L L L L L L
READ / READA ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Command DESEL NOP TBST Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2
®
FUNCTION TRUTH TABLE (continued)
Current State /CS H L L PRE CHARGING L L L L L H L L ROW ACTIVATING L L L L L H L L WRITE RECOVERING L L L L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
9
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Command DESEL NOP TBST Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL
®
FUNCTION TRUTH TABLE (continued)
Current State /CS H L L REFRESHING L L L L L H L L MODE REGISTER SETTING L L L L L /RAS X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
®
FUNCTION TRUTH TABLE (continued)
Current State CKE CKE n-1 H L SELFREFRESH*1 L L L L L POWER DOWN H L L H H H ALL BANKS IDLE*2 H H H H L ANY STATE other than listed above H H L L ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
11
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
S ELF REFRESH
®
SIMPLIFIED STATE DIAGRAM
REFS
REFSX
M ODE REGISTER SET
MRS
REFA
I DLE
AUTO REFRESH
CKEL
C LK SUSPEND
A CT CKEL CKEH
CKEH
POWER DOWN
ROW ACTIVE
TERM
TERM
WRITE
READ
R EADA
WRITE SUSPEND
CKEL
WRITEA
CKEL
WRITE
CKEH
READ
WRITE
READ
CKEH
READ SUSPEND
WRITEA
WRITEA
R EADA
R EADA
WRITEA SUSPEND
CKEL
CKEL
WRITEA
CKEH
P RE
P RE
P RE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
P RE
PRE CHARGE
A utomatic Sequence Command Sequence
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
M ODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
®
POWER ON SEQUENCE
B efore starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2 . Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. 3 . Issue precharge commands for all banks. (PRE or PREA) 4 . After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize t he mode register.
CLK /CS /RAS /CAS /WE
After these sequence, the SDRAM is idle state and ready for normal operation.
BA0,1 A12-A0
BA0 BA1 A12 A11 A10 A9
A8 A7
0
V
A6
A5
A4
A3
BT
A2
A1
BL
A0
0
0
0
0
0
SW
0
LTMODE
SW
0 1
Burst Write Single Write
LATENCY MODE
CL 000 001 010 011 100 101 110 111
/CAS LATENCY R R 2 3 R R R R
BURST LENGTH
BL 000 001 010 011 100 101 110 111
0 1
BT=0 1 2 4 8 R R R Full Page
BT=1 1 2 4 8 R R R R
BURST TYPE
SEQUENTIAL INTERLEAVED
R: Reserved for Future Use
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
13
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Write Y
®
CLK
Command
Read
Y
Q0
Address
DQ
Q1
Q2
Q3
D0
D1
D2
D3
/CAS Latency
CL= 3 BL= 4
Burst Length
Burst Type
Burst Length
Initial Address BL
Column Addressing
Sequential
0 1 2 3
1 2 3 4 5 6 7 0 1 2 3 0 1 0
A2
0 0 0 0 1 1 1 1 -
A1
0 0 1 1 0 0 1 1 0 0 1 1 -
A0
0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 1 2 2 3 0 1 0 1 4 5 6 7 0 1 6 7 0 1 2 3 2 3 4 5
Interleaved
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6
3 4 5 6 7 0 1 2 3 0 1 2
4 5 6 7 0 1 2
1 0 3 2 5 4 7 6 1 0 3
2 1 0
2 3 0 1 6 7 4 5 2 3 0
3 2 1 0 7 6 5 4 3 2 1 0
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0
3
7 0 1 2 3 0 1
1
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
R EAD
A fter tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, fol lowed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A0-9(X8), A0-8(X16) , and the address sequence of burst data is defined by the B urst Type. A R EAD command may be applied t o any active bank, so the row precharge time (tRP) can be h idden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
In any case, tRCD+BL ≥ tRASmin must be met.
®
OPERATIONAL DESCRIPTION
BANK ACTIVATE
T he SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-12. The minimum activation interval between one bank and the other bank is tRRD.Multiple banks can be active state concurrently by issuing mul tiple ACT commands.
P RECHARGE
T he PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued.BA0-1 are “DON’T CARE” i n this case.
Bank Activation and Precharge All (BL=4, CL=3)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT
tRRD
ACT
tRCD
READ Yb 0 01 Qb0 Qb1
PRE
tRP
ACT Xa
Xa Xa 00
Xb Xb 01
1
Xa 00
Qb2
Qb3
Precharge All
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
15
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
Multi Bank Interleaving Read (CL=2, BL=4)
ISSI
READ PRE
tRCD
®
CLK Command A0-9,11-12 A10 BA0-1 DQ
ACT
tRCD
READ
Ya
0
ACT
ACT
tRP
Xa
Xa
00
Xb
Xb
01
Yb
Xa
0
0
01
Xa
00
00
00
Qa3
Qb0
Qa0
Qa1
Qa2
Qb1
Qb2
Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
ACT
tRCD
READ
BL
tRP
ACT
Xa
Ya
Xa
Xa
1
Xa
00
00
00
Qa0
Qa1
Qa2
Qa3
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK Command DQ
ACT
tRCD
READ
BL
ACT
Qa0
Qa1
Qa0
CL=2
CL=3
Qa2
Qa1
Qa3
DQ
Qa2
Qa3
internal precharge starts
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
WRITE
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
A WRITE command can be issued to any active bank. The start address is specified by A0-9(x8), A0-8(x16). 1st input data is set at the same cycle as the WRITE. T he consecutive data length to be write is d efined b y the Burst Length. The address sequence o f burst data is defined by Burst Type. Minmum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command , the write recovery time (tWR) is
r equired. When A10 is high at a WRITE command , auto-precharge (WRITEA) is performed. Any com mand (READ,WRITE,PRE,ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle . The next ACT command can be issued after (BL+tWR-1+tRP) from the previous WRITEA. In any case, tRCD+BL+tWR-1 ≥ tRASmin must be met.
Write (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
ACT
tRCD
Write
BL
PRE
tRP
ACT
Xa
Xa
Ya
Xa
0
00
tWR
0
Xa
00
00
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
ACT
tRCD
Write
BL
tRP
ACT
Xa
Ya
1
Xa
Xa
00
Xa
00
tWR
00
Da0
Da1
Da2
Da3
internal precharge starts
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
17
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
BURST INTERRUPTION [ Read Interrupted by Read ]
B urst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval is minimum 1 CLK..
Read interrupted by Read (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
READ
READ READ
Ya
Yb
Yc
0
0
00
Qa1
0
10
00
Qa0
Qa2
Qb0
Qc0
Qc1
Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion.
Read interrupted by Write (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1
ACT
Xa
READ
Write
Ya
Ya
0
00
Xa
00
0
00
DQM
DQ
Qa0
Da0
Da1
Da2
Da3
Output disable by DQM
by WRITE
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4.
Read interrupted by Precharge (BL=4)
CLK Command
READ
PRE
DQ
Command
READ
Q0
PRE
Q1
Q2
CL=2
DQ
Q0
Q1
Command
READ PRE
DQ
Q0
Command
READ
PRE
DQ
Command
READ
Q0
PRE
Q1
Q2
CL=3
DQ
Command
READ PRE
Q0
Q1
DQ
Q0
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
19
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency.
®
[Read Interrupted by Burst Terminate]
S imilarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active.
Read interrupted by Terminate (BL=4)
CLK Command
READ
TBST
DQ
Command
READ
Q0
TBST
Q1
Q2
CL=2
DQ
Command
Q0
READ TBST
Q1
DQ
Q0
Command
READ
TBST
DQ
Command
TBST
Q0
READ
Q1
Q2
CL=3
DQ
Command
READ TBST
Q0
Q1
DQ
Q0
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
Write
Write
Write
Ya
0
Yb
Yc
0
0
10
00
00
Da1
Da0
Da2
Db0
Dc0
Dc1
Dc2
Dc3
[ Write Interrupted by Read ]
B urst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write interrupted by Read (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
ACT
Write
Ya
READ
Yb
Xa
Xa
0
0
00
Da1
Qb0
00
00
Da0
Qb1
Qb2
Qb3
don't care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
21
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
[ Write Interrupted by Precharge ]
B urst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
Write interrupted by Precharge (BL=4)
CLK Command A0-9,11-12 A10 BA0-1
DQM
tWR
ACT
Xa
0
00
Write
Ya
0
PRE
tRP
ACT
Xa
0
0
00
00
00
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write interrupted by Terminate (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
ACT
Xa
Write
Ya
0
00
Da0
TBST
Write
Yb
0
00
0
00
Da1
Db0
Db1
Db2
Db3
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after(BL+tWR-1+ tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited.
WRITEA interrupted by WRITE to another bank (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ
Write
Ya
1
Write
BL
tRP
ACT
Xa
tWR
Yb
0
Xa
00
Da0
Da1
10
00
Db0
Db1
Db2
Db3
activate
auto-precharge
interrupted
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK Command
Write
Read
BL
tRP
ACT
A0-9,11-12 A10 BA0-1 DQ
Ya
1
00
Da0
Da1
Yb
tWR
Xa
Xa
00
0
10
Qb0
Qb1
Qb2
Qb3
activate
auto-precharge
interrupted
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
23
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited.
READA interrupted by READ to another bank (CL=2, BL=4)
CLK Command
A0-9,11-12 A10 BA0-1 DQ
auto-precharge
Read
Ya
Read
BL
tRP
ACT
Yb
Xa
Xa
00
1
00
0
10
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
interrupted
activate
[Full Page Burst]
F ull page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal.
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
24
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
c oncurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to autorefresh interval is minimum tRFC. Any command must not be supplied to the device before tRFC from the REFA command.
®
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256M bit memory cells. The auto-refresh is performed on 4 banks
Auto-Refresh
CLK
/CS
/RAS
NOP or DESELECT
/CAS
/WE
CKE
A0-12 BA0-1
minimum tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
25
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
nous inputs is saved. To exit the self-refresh, supply ing stable CLK inputs, asserting DESEL or NOP com mand and then asserting CKE=H. After tRFC from the 1st CLK egde following CKE=H, all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
®
SELF REFRESH
S elf-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input . All other inputs including CLK are disabled and ignored, so that power consumption due to synchro
Self-Refresh
CLK
Stable CLK
NOP
/CS /RAS /CAS
/WE
CKE A0-12
BA0-1
new command
X
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC for recovery
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input s uspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
tIH
CKE
tIS
tIH
tIS
int.CLK
Power Down by CKE
CLK CKE Command
PRE
NOP NOP NOP
Standby Power Down
CKE Command
ACT
NOP NOP NOP
Active Power Down
DQ Suspend by CKE
CLK
CKE Command
Write
Read
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
27
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
t o write mask latency is 0. During reads, DQM(U,L) forces output to Hi-Z word by word. DQM(U,L) to output Hi-Z latency is 2.
®
DQM CONTROL
DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM(U,L) masks input data word by word. DQM(U,L)
DQM Function
CLK Command DQMU/L
Write
Read
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMU/L=H
disabled by DQMU/L=H
28
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Ratings
-0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 50
®
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd VddQ VI VO IO Pd Topr Tstg
Parameter
Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature
Conditions
with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ
Unit
V V V V mA mW ˚C ˚C
Ta = 25˚C
1000 0 - 70 -65 - 150
RECOMMENDED OPERATING CONDITIONS
(Ta=0 - 70 ˚C ,unless otherwise noted)
Symbol
Vdd Vss VddQ VssQ VIH*1 VIL*2
Parameter
Supply Voltage Supply Voltage Supply Voltage for output Supply Voltage for output High-Level Input Voltage all inputs Low-level Input Voltage all inputs
Limits
Min.
3.0 0 3.0 0 2.0 -0.3
Typ.
3.3 0 3.3 0
Max.
3.6 0 3.6 0 VddQ +0.3 0.8
Unit
V V V V V V
NOTES: 1. VIH (max) = VDDQ + 2.0V for a pulse width of < 3ns. 2. VIL (min) = -2.0V for a pulse width of < 3ns. 3. All voltages referenced to VSS/VSSQ.
CAPACITANCE
(Ta=0 -70˚C,Vdd=VddQ=3.3± 0 . 3 V , V s s = V s s Q = 0 V , u n l e s s o t h e r w i s e n o t e d )
Limits (max.) -6 /-7 -75 3.8 3.8 3.5 6.5 5.0 5.0 4.0 6.5
Symbol
CI(A) CI(C) CI(K) CI/O
Parameter
Input Capacitance, address pin Input Capacitance, contorl pin Input Capacitance, CLK pin Input Capacitance, I/O pin
Test Condition
Limits (min.) 2.5 2.5 2.5 4.0
Unit pF pF pF pF
@ 1MHz 1.4V bias 200mV swing Vcc=3.3V
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
29
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Organization Limits (max.) -6 -7 -75 Unit Note
®
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
ITEM
Symbol
Operating current
Icc1
tRC=min, tCLK=min BL=1,IOL=0mA
x8 x16
130 20 15 2 2 30 20
130 20 15 2 2 30 20
110
mA 1 mA mA mA mA 2 mA mA mA mA 5 3,5 4,5 2,3 2,4
20 15 2 2 30 20 150
Precharge Standby current in Non-Power down mode Precharge Standby current in Power down mode Active Standby current
Icc2N Icc2NS Icc2P Icc2PS Icc3N Icc3NS
CKE=VILmax tCLK=15ns CKE=VIHmin CLK=VILmax(fixed) CKE=VIHmin tCLK=15ns(Note) CKE=VIHmin tCLK=VILmax(fixed) CKE=/CS=VIHmin tCLK=15ns(Note) CKE=VIHmin tCLK=VILmax(fixed)
x8/x16 x8/x16 x8/x16 x8/x16 x8/x16 x8/x16 x8
Burst current
Icc4
All Bank Active tCLK = min BL=4, CL=3, IOL=0mA
160
160
x16
160 3
mA mA mA
Auto-refresh current Self-refresh current
Icc5 Icc6
tRC=min, tCLK=min CKE < 0.2V x8/x16
x8/x16 -6,-7,-75
160 3
160 3
NOTE:
1.address are changed 3 times during tRC , only 1 bank is active & all other banks are idle
2.all banks are idle
3.input signals are changed one time during 3x tCLK
4.input signals are stable
5.all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Symbol
Parameter High-Level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current Input Current
Test Conditions Min.
Limits Max.
unit
VOH (DC) VOL (DC) IOZ II
IOH=-2mA IOL= 2mA Q floating VO=0 -- VddQ VIH = 0 -- VddQ +0.3V
2.4
0.4 10 10
V V µA µA
-10 -10
30
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Limits
®
AC TIMING REQUIREMENTS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V
Input Timing Measurement Level:1.4V
Symbol
tCLK
Parameter
CLK cycle time
CL=2 CL=3
Unit -75 -7 Min. Max. Min. Max. Min. Max.
-6
6 2 2 1 1.8 1 60 60 15 42 120K 15 12 12 12 7.8 10 7 2.5 2.5 1 1.8 1 63 70 20 45 20 14 14 14 7.8 10
10 7.5 2.5 2.5 1 1.8 1 67.5 75 20 10 ns ns ns ns ns ns ns ns ns ns 120K ns ns ns ns ns 7.8 us
tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF
CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time Input Hold time Row Cycle time Refresh Cycle Time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Mode Register Set Cycle time Refresh Interval time
(all inputs) (all inputs)
120K 45
20 15 15 15
CLK
1 .4V
DQ
1 .4V
Any AC timing is referenced to the input signal passing through 1.4V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
31
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
-75
Max. Min.
®
SWITCHING CHARACTERISTICS
(Ta=0 - 70˚C, Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V, unless otherwise noted)
Limits S ymbol Parameter
Min.
-6
Max. Min.
-7
Unit Note
Max. 6 ns
tAC
Access t ime f rom C LK
CL=2
CL=3
CL=2
5
5.4
5.4
3
ns
tOH
Output Hold time from CLK
ns
CL=3
2.5
2.7
3
ns
ns
5.4
*1
tOLZ
tOHZ
Delay time , output lowimpedance from CLK
Delay time , output highimpedance from CLK
0
2 .5
5
0
2.7 5.4
0
3
ns
NOTE: 1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
O utput Load Condition
CLK
VOUT
50pF
1.4V
DQ
1.4V
Output Timing Measurement Reference Point
CLK
tOLZ
1 .4V
DQ
1 .4V
tAC
tOH
tOHZ
32
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Burst Write (Single Bank) [BL=4]
0 1 2 3 4 5 6 7
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD tRCD
/CAS
tWR tWR
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
33
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16 tRC
®
Burst Write (Multi Bank) [BL=4]
0 1 2 3 4 5 6 7
CLK
tRC
/CS
tRAS tRRD
tRP
/RAS
tRCD
tRCD
tRCD
/CAS
tWR tWR
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
0
1
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
PRE#0
ACT#0
WRITE#0 ACT#1
PRE#0
WRITEA#1 (Auto-Precharge)
Italic paramater shows minimum case
34
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
9 10 11 12 13 14 15 16
®
Burst Read (Single Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7 8
CLK
tRC
/CS
tRAS
tRP
tRAS
/RAS
tRCD tRCD
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y X Y
X
X
X
X
0
0
0
0
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
35
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16 tRC
®
Burst Read (Multi Bank) [CL=2, BL=4]
0 1 2 3 4 5 6 7
CLK
tRC
/CS
tRRD tRAS
/RAS
tRCD
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y X Y X Y X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READA#0 ACT#1 READA#1
ACT#0
READ#0 ACT#1
PRE#0
Italic paramater shows minimum case
36
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Write Interrupted by Write [BL=4]
0 1 2 3 4 5 6 7
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
0
1
0
0
1
D0
D0
D0
D0
D0
D1
D1
D1
D0
D0
D0
D0
ACT#0 WRITE#0 ACT#1
WRITE#0 WRITEA#1 interrupt interrupt same bank other bank
WRITE#0 interrupt other bank
PRE#0 ACT#1
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
37
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Read Interrupted by Read [CL=2, BL=4]
0 1 2 3 4 5 6 7
CLK
/CS
tRRD
/RAS
tRCD tRCD
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y X Y Y Y X
X
X
X
X
X
X
0
0
1
1
1
0
1
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT#0 READ#0 ACT#1
READ#1 READA#1 interrupt interrupt other bank same bank
READ#0 interrupt other bank
ACT#1
Italic paramater shows minimum case
38
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4]
0 1 2 3 4 5 6 7
CLK
/CS
tRRD
/RAS
tRCD tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1 DQ
X X Y Y Y
X
X
X
X
0
1
0
1
1
1
D0
D0
Q1
Q1
D1
D1
D1
D1
ACT#0
WRITE#0 ACT#1
READ#1
WRITE#1
PRE#1
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
39
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Write / Read Terminated by Precharge [CL=2, BL=4]
0 1 2 3 4 5 6 7
CLK
tRC
/CS
tRP tRAS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y X Y X
X
X
X
X
X
X
0
0
0
0
0
0
0
D0
D0
Q0
Q0
ACT#0
WRITE#0
PRE#0 ACT#0 Terminate
READ#0
PRE#0 Terminate
ACT#0
Italic paramater shows minimum case
40
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Write / Read Terminated by Burst Terminate [CL=2, BL=4]
0 1 2 3 4 5 6 7
CLK
/CS
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y Y Y
X
X
0
0
0
0
0
D0
D0
Q0
Q0
D0
D0
D0
D0
ACT#0
WRITE#0 TBST
READ#0 TBST
WRITE#0
PRE#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
41
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Single Write Burst Read [CL=2, BL=4]
0 1 2 3 4 5 6 7
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y Y
X
X
0
0
0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE#0
READ#0
Italic paramater shows minimum case
42
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
®
Power-Up Sequence and Intialize
CLK
200µs
/CS
tRP tRFC tRFC tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
NOP Power On PRE ALL REFA REFA REFA MRS ACT#0
MA
X
0
X
0
X
0
0
Minimum 8 REFA cycles
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
43
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Auto Refresh
0 1 2 3 4 5 6 7
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y
X
X
0
0
D0
D0
D0
D0
PRE ALL
REFA
ACT#0
WRITE#0
All banks must be idle before REFA is issued.
Italic paramater shows minimum case
44
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
Self Refresh
0 1 2 3 4 5 6 7
CLK
tRFC
/CS
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
PRE ALL Self Refresh Entry All banks must be idle before REFS is issued.
Self Refresh Exit
ACT#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
45
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
8 9 10 11 12 13 14 15 16
®
CLK Suspension [CL=2, BL=4]
0 1 2 3 4 5 6 7
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X Y Y
X
X
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE#0 internal CLK suspended
READ#0
internal CLK suspended
Italic paramater shows minimum case
46
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
9 10 11 12 13 14 15 16
®
Power Down
0 1 2 3 4 5 6 7 8
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down Active Power Down
CKE
DQM
A0-9,11
A10
A12
BA0,1
DQ
X
X
X
0
PRE ALL
ACT#0
Italic paramater shows minimum case
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
47
IS42S83200A IS42S16160A
(4-bank x 8,388,608 - word x 8-bit) (4-bank x 4,194,304 - word x 16-bit)
ISSI
Package 54-pin TSOP-II 54-pin TSOP-II 54-pin TSOP-II
®
ORDERING INFORMATION Commercial Range: 0°C to +70°C
Frequency 166 MHz 143 MHz 133 MHz Speed (ns) 6 7 7.5 Order Part No. IS42S16160A-6T IS42S16160A-7T IS42S83200A-75T
Commercial Range: 0°C to +70°C, Lead-free
Frequency 166 MHz 143 MHz 133 MHz Speed (ns) 6 7 7.5 Order Part No. IS42S16160A-6TL IS42S16160A-7TL IS42S83200A-75TL Package 54-pin TSOP-II 54-pin TSOP-II 54-pin TSOP-II
48
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D 11/01/05
PACKAGING INFORMATION
Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II)
ISSI
N/2+1 E1 E
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be
®
N
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
1 D
N/2
SEATING PLANE
ZD
A
e
b
L A1
α
C
Symbol Ref. Std. No. Leads (N) A A1 A2 b C D E1 E e L L1 ZD α
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 54 — 0.047 0.002 0.006 — — 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 — — 0° 8°
Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 86 A A1 A2 b C D E1 E e L L1 ZD α — 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.12 0.21 22.02 22.42 10.16 BSC 11.56 11.96 0.50 BSC 0.40 0.60 0.80 REF 0.61 REF 0° 8° — 0.047 0.002 0.006 0.037 0.041 0.007 0.011 0.005 0.008 0.867 0.8827 0.400 BSC 0.455 0.471 0.020 BSC 0.016 0.024 0.031 REF 0.024 BSC 0° 8°
— 1.20 0.05 0.15 — — 0.30 0.45 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 — — 0.71 REF 0° 8°
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C 01/28/02
1
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