IS61C632A-7TQ

ISSI ISSI® IS61C632A IS61C632A ® 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM MAY 1998 FEATURES • Fast access time: – 4 ns-125 MHZ; 5 ns-100 MHz; 6 ns-83 MHz; 7 ns-75 MHz; 8 ns-66 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin TQFP and PQFP package • Single +3.3V power supply • Two Clock enables and one Clock disable to eliminate multiple bank bus contention. • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state DESCRIPTION The ISSI IS61C632A is a high-speed, low-power synchronous static RAM designed to provide a burstable, highperformance, secondary cache for the i486™, Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 32,768 words by 32 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61C632A and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ (or no connect) on MODE pin selects INTERLEAVED Burst. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. SR001-1B 05/18/98 1 ISSI IS61C632A ® BLOCK DIAGRAM MODE CLK Q0 CLK A0' A0 BINARY COUNTER ADV CE ADSC ADSP CLR A14-A0 15 D Q1 Q A1' A1 32K x 32 MEMORY ARRAY 13 15 ADDRESS REGISTER CE CLK 32 GW BWE BW4 D 32 Q DQ32-DQ25 BYTE WRITE REGISTERS CLK D BW3 Q DQ24-DQ17 BYTE WRITE REGISTERS CLK D BW2 Q DQ16-DQ9 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE1 CE2 CE3 4 D Q ENABLE REGISTER INPUT REGISTERS CLK 32 OUTPUT REGISTERS CLK DATA[32:1] OE CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. SR001-1B 05/18/98 ISSI IS61C632A ® PIN CONFIGURATION A8 A9 GW BWE OE ADSC ADSP ADV VCC GND CLK BW4 BW3 BW2 BW1 CE3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQ16 DQ15 VCCQ GNDQ DQ14 DQ13 DQ12 DQ11 GNDQ VCCQ DQ10 DQ9 GND NC VCC ZZ DQ8 DQ7 VCCQ GNDQ DQ6 DQ5 DQ4 DQ3 GNDQ VCCQ DQ2 DQ1 NC MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 NC NC NC DQ17 DQ18 VCCQ GNDQ DQ19 DQ20 DQ21 DQ22 GNDQ VCCQ DQ23 DQ24 VCCQ VCC NC GND DQ25 DQ26 VCCQ GNDQ DQ27 DQ28 DQ29 DQ30 GNDQ VCCQ DQ31 DQ32 NC CE2 A6 A7 CE 100-Pin TQFP and PQFP (Top View) PIN DESCRIPTIONS A0-A14 Address Inputs OE Output Enable CLK Clock DQ1-DQ32 Data Input/Output Processor Address Status ZZ Sleep Mode Controller Address Status MODE Burst Sequence Mode Burst Address Advance VCC +3.3V Power Supply Synchronous Byte Write Enable GND Ground Byte Write Enable VCCQ Isolated Output Buffer Supply: +3.3V GNDQ Isolated Output Buffer Ground ADSP ADSC ADV BW1-BW4 BWE GW CE1, CE2, CE3 Global Write Enable Synchronous Chip Enable Integrated Silicon Solution, Inc. SR001-1B 05/18/98 3 ISSI IS61C632A ® TRUTH TABLE ADDRESS USED CE1 CE2 Deselected, Power-down None H X X X L X Deselected, Power-down None L L X L X Deselected, Power-down None L X H L Deselected, Power-down None L L X Deselected, Power-down None L X External External External External External Next Next Next Next Next Next Current Current Current Current Current Current L L L L L X X H H X H X X H H X H H H H H H X X X X X X X X X X X X OPERATION Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst CE3 ADSP ADSC ADV WRITE OE DQ X X High-Z X X X High-Z X X X X High-Z H L X X X High-Z H H L X X X High-Z L L L L L X X X X X X X X X X X X L L H H H H H X X H X H H X X H X X X L L L H H H H H H H H H H H H X X X X X L L L L L L H H H H H H X X L H H H H H H L L H H H H L L L H X L H L H L H X X L H L H X X Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW4) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. PARTIAL TRUTH TABLE FUNCTION READ READ WRITE Byte 1 WRITE All Bytes WRITE All Bytes 4 GW BWE BW1 BW2 BW3 H H H X L H X L L X X H L L X X H H L X X H H L X BW4 X H H L X Integrated Silicon Solution, Inc. SR001-1B 05/18/98 ISSI IS61C632A ® INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Value Unit –10 to +85 °C –55 to +150 °C 1.8 W 100 mA –0.5 to VCCQ + 0.3 V –0.5 to 5.5 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. SR001-1B 05/18/98 5 ISSI IS61C632A ® OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C VCC 3.3V +10%, –5% –40°C to +85°C 3.3V +10%, –5% Industrial DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage IOH = –5.0 mA 2.4 — V VOL Output LOW Voltage IOL = 5.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V VIL Input LOW Voltage –0.3 0.8 V ILI Input Leakage Current GND ≤ VIN ≤ VCCQ(2) Com. Ind. –5 –10 5 1- µA ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. Ind. –5 –10 5 10 µA POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions ICC AC Operating Supply Current Device Selected, All Inputs = VIL or VIH OE = VIH, Cycle Time ≥ tKC min. ISB Standby Current Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time ≥ tKC min. IZZ Power-Down Mode ZZ = VCCQ, CLK Running Current All Inputs ≤ GND + 0.2V or ≥ VCC – 0.2V Com. Ind. Com. Ind. -4 Typ. Max -5 Typ. Max. -6 Typ. Max. -7 Typ. Max. -8 Typ. Max. Unit 150 180 — — 140 170 — — 130 160 140 170 120 150 130 160 110 140 mA 120 150 µA 15 — 45 — 15 — 45 — 15 20 45 50 15 20 45 50 15 20 45 50 mA µA 1 — 10 — 1 — 10 — 1 2 10 20 1 2 10 20 1 2 10 20 mA mA Note: 1. MODE pin has an internal pull-up. ZZ pin has an internal pull-down. These pins may be a No Connect, tied to GND, or tied to VCCQ. 2. MODE pin should be tied to Vcc or GND. They exhibit ±10 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V. 6 Integrated Silicon Solution, Inc. SR001-1B 05/18/98 ISSI IS61C632A ® CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω OUTPUT Output Buffer 30 pF 50Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. SR001-1B 05/18/98 5 pF Including jig and scope 351 Ω Figure 2 7 ISSI IS61C632A ® READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -4 Min. Max. Symbol Parameter -5 Min. Max. -6 Min. Max. -7 Min. Max. -8 Min. Max. Unit tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns Clock Access Time — 4 — 5 — 6 — 7 — 8 ns Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — 2 — ns Clock High to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns tKQHZ(2,3) Clock High to Output High-Z 1.5 4 1.5 5 2 6 2 6 2 6 ns tOEQ tKQ tKQX (2) tKQLZ (2,3) Output Enable to Output Valid — 4 — 5 — 6 — 6 — 6 ns (2) Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — ns (2,3) Output Enable to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns tOEHZ(2,3) Output Disable to Output High-Z — 4.5 — 4.8 — 6 — 6 — 6 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 25 — 35 — 45 — 66.7 — 80 — ns tOEQX tOELZ tCFG Configuration Setup (1) Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with the load in Figure 2. 8 Integrated Silicon Solution, Inc. SR001-1B 05/18/98 ISSI IS61C632A ® READ CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP tSS ADSC initiate read tSH ADSC tAVH tAVS Suspend Burst ADV tAS A14-A0 tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE1 Masks ADSP CE1 Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE3 tOEHZ tOEQ OE DATAOUT tKQX tOEQX tOELZ High-Z 1a 2a 2b 2c 2d tKQLZ 3a tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read Integrated Silicon Solution, Inc. SR001-1B 05/18/98 Burst Read Unselected 9 ISSI IS61C632A ® WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter -4 Min. Max. -5 Min. Max. -6 Min. Max. -7 Min. Max. -8 Min. Max. Unit tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tDS Data In Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tDH Data In Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tCFG Configuration Setup(1) 25 — 35 — 45 — 52 — 60 — ns Notes: 1. Configuration signal MODE is static and must not change during normal operation. 10 Integrated Silicon Solution, Inc. SR001-1B 05/18/98 ISSI IS61C632A ® WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC tAVH ADV must be inactive for ADSP Write tAVS ADV tAS A14-A0 tAH WR1 WR2 tWS tWH tWS tWH tWS tWH WR3 GW BWE BW4-BW1 WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE1 Masks ADSP CE1 Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE3 OE DATAOUT High-Z tDS DATAIN High-Z tDH 1a Single Write Integrated Silicon Solution, Inc. SR001-1B 05/18/98 BW4-BW1 only are applied to first cycle of WR2 2a 2b Burst Write 2c 2d 3a Write Unselected 11 ISSI IS61C632A ® READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter -4 Min. Max. -5 Min. Max. -6 Min. Max. -7 Min. Max. -8 Min. Max. Unit tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns Clock Access Time — 4 — 5 — 6 — 7 — 8 ns Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — 2 — ns Clock High to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns tKQHZ(2,3) Clock High to Output High-Z 1.5 4 1.5 5 2 6 2 6 2 6 ns tOEQ tKQ tKQX (2) tKQLZ (2,3) Output Enable to Output Valid — 4.5 — 4.8 — 6 — 6 — 6 ns (2) Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — ns (2,3) Output Enable to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns tOEHZ(2,3) Output Disable to Output High-Z — 4.5 — 4.8 — 6 — 6 — 6 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tWS Write Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tCFG Configuration Setup(1) 25 — 35 — 45 — 52 — 60 — ns tOEQX tOELZ Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with the load in Figure 2. 12 Integrated Silicon Solution, Inc. SR001-1B 05/18/98 ISSI IS61C632A ® READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP tSS tSH ADSC ADV tAS A14-A0 tAH RD1 RD2 WR1 tWS tWH tWS tWH RD3 GW BWE tWS tWH WR1 BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE1 Masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC CE2 Unselected with CE3 CE3 tOEHZ tOEQ OE DATAOUT High-Z 2a 1a tKQLZ tKQ DATAIN tKQX tOEQX tOELZ 2c 2d tKQHZ tKQX tKQHZ High-Z 1a tDS Single Read Integrated Silicon Solution, Inc. SR001-1B 05/18/98 2b tDH Single Write Burst Read Unselected 13 ISSI IS61C632A ® SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -4 Min. Max. Symbol Parameter -5 Min. Max. -6 Min. Max. -7 Min. Max. -8 Min. Max. Unit tKC Cycle Time 8 — 10 — 12 — 13 — 15 — ns tKH Clock High Time 4 — 4 — 4 — 6 — 6 — ns tKL Clock Low Time 4 — 4 — 4 — 6 — 6 — ns Clock Access Time — 4 — 5 — 6 — 7 — 8 ns Clock High to Output Invalid 1.5 — 1.5 — 2 — 2 — 2 — ns Clock High to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns tKQHZ(4,5) Clock High to Output High-Z 1.5 4 1.5 5 2 6 2 6 2 6 ns tOEQ tKQ tKQX (4) tKQLZ (4,5) Output Enable to Output Valid — 4.5 — 5 — 6 — 6 — 6 ns (4) Output Disable to Output Invalid 0 — 0 — 0 — 0 — 0 — ns (4,5) Output Enable to Output Low-Z 0 — 0 — 0 — 0 — 0 — ns tOEHZ(4,5) Output Disable to Output High-Z — 4.5 — 4.8 — 6 — 6 — 6 ns tAS Address Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns tAH Address Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns 2 — 2 — 2 — 2 — 2 — cyc tOEQX tOELZ (1) tZZS ZZ Standby tZZREC ZZ Recovery(2) 2 — 2 — 2 — 2 — 2 — cyc tCFG Configuration Setup(3) 25 — 35 — 45 — 52 — 60 — ns Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Configuration signal MODE is static and must not change during normal operation. 4. Guaranteed but not 100% tested. This parameter is periodically sampled. 5. Tested with the load in Figure 2. 14 Integrated Silicon Solution, Inc. SR001-1B 05/18/98 ISSI IS61C632A ® SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tAS tAH tKH tKL ADSP ADSC ADV A14-A0 RD1 RD2 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE1 CE2 CE3 tOEHZ tOEQ OE tOEQX tOELZ DATAOUT High-Z 1a tKQLZ tKQ DATAIN tKQX tKQHZ High-Z tZZS tZZREC ZZ Single Read Integrated Silicon Solution, Inc. SR001-1B 05/18/98 Snooze with Data Retention Read 15 ISSI IS61C632A ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part Number Package 4 4 IS61C632A-4TQ IS61C632A-4PQ TQFP PQFP 5 5 IS61C632A-5TQ IS61C632A-5PQ TQFP PQFP 6 6 IS61C632A-6TQ IS61C632A-6PQ TQFP PQFP 7 7 IS61C632A-7TQ IS61C632A-7PQ TQFP PQFP 8 8 IS61C632A-8TQ IS61C632A-8PQ TQFP PQFP Industrial Range: –40°C to +85°C Speed (ns) Order Part Number Package 6 6 IS61C632A-6TQI IS61C632A-6PQI TQFP PQFP 7 7 IS61C632A-7TQI IS61C632A-7PQI TQFP PQFP 8 8 IS61C632A-8TQI IS61C632A-8PQI TQFP PQFP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 e-mail: sales@issi.com http://www.issi.com 16 Integrated Silicon Solution, Inc. SR001-1B 05/18/98