IS61LPS25618A-200B3

IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ISSI ® 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LPS: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VPS: VDD 2.5V + 5%, VDDQ 2.5V + 5% • JEDEC 100-Pin TQFP, 119-ball PBGA, and 165-ball PBGA packages • Automotive temperature available • Lead Free available PRELIMINARY INFORMATION FEBRUARY 2005 DESCRIPTION The ISSI IS61(64)LPS12832A, IS61(64)LPS/VPS12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 bits. The IS61(64)LPS/VPS12836A is organized as 131,072 words by 36 bits. The IS61(64)LPS/ VPS25618A is organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ t KC Parameter Clock Access Time Cycle Time Frequency 250 2.6 4 250 200 3.1 5 200 Units ns ns MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 1 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A BLOCK DIAGRAM MODE Q0 A0' ISSI ® CLK CLK A0 BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' A1 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY 15/16 17/18 17/18 A D Q ADDRESS REGISTER CE CLK 32, 36, or 18 32, 36, or 18 GW BWE BW(a-d) x18: a,b x32/x36: a-d DQ(a-d) BYTE WRITE REGISTERS CLK D Q CE CE2 CE2 D Q 2/4/8 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OUTPUT REGISTERS CLK OE 32, 36, or 18 DQa - DQd D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 165-PIN BGA 165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array ISSI 119-PIN BGA 119-Ball, 14x22 mm BGA 1mm Ball Pitch, 7x17 Ball Array ® BOTTOM VIEW BOTTOM VIEW Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 3 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ISSI 5 A A A Vss Vss Vss BWb Vss NC Vss BWa Vss Vss Vss NC A NC 6 A CE2 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ ® 119 BGA PACKAGE PIN CONFIGURATION 128K X 36 (TOP VIEW) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC NC 3 A A A Vss Vss Vss BWc Vss NC Vss BWd Vss Vss Vss MODE A NC 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1* A0* VDD A NC Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 BWx (x=a-d) BWE Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Synchronous Byte Write Controls Byte Write Enable Symbol OE ZZ MODE NC DQa-DQd DQPa-Pd VDD VDDQ Vss Pin Name Output Enable Power Sleep Mode Burst Sequence Selection No Connect Data Inputs/Outputs Output Power Supply Power Supply Output Power Supply Ground 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ISSI 5 A A A Vss Vss Vss Vss Vss NC Vss BWa Vss Vss Vss NC A NC 6 A CE2 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ ® 119 BGA PACKAGE PIN CONFIGURATION 256KX18 (TOP VIEW) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ 2 A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A NC 3 A A A Vss Vss Vss BWb Vss NC Vss Vss Vss Vss Vss MODE A NC 4 ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1* A0* VDD NC NC Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 BWx (x=a,b) BWE Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Synchronous Byte Write Controls Byte Write Enable Symbol OE ZZ MODE NC DQa-DQb DQPa-Pb VDD VDDQ Vss Pin Name Output Enable Power Sleep Mode Burst Sequence Selection No Connect Data Inputs/Outputs Output Power Supply Power Supply Output Power Supply Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 5 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ISSI 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A ® 165 PBGA PACKAGE PIN CONFIGURATION 128K X 36 (TOP VIEW) 1 A B C D E F G H J K L M N P R NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC NC 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 5 BWb BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Symbol BWE OE ZZ MODE NC DQx DQPx V DD VDDQ Vss Pin Name Byte Write Enable Output Enable Power Sleep Mode Burst Sequence Selection No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Isolated Output Power Supply 3.3V/2.5V Ground BWx (x=a,b,c,d) Synchronous Byte Write Controls 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 165 PBGA PACKAGE PIN CONFIGURATION 256K X 18 (TOP VIEW) 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE 2 A A NC DQb DQb DQb DQb NC NC NC NC NC NC NC NC 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 5 NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 6 CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0* 7 BWE GW Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC 8 ADSC OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A ISSI 11 A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A ® Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV ADSP ADSC GW CLK CE, CE2, CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance Address Status Processor Address Status Controller Global Write Enable Synchronous Clock Synchronous Chip Select Synchronous Byte Write Controls Symbol BWE OE ZZ MODE NC DQx DQPx VDD VDDQ Vss Pin Name Byte Write Enable Output Enable Power Sleep Mode Burst Sequence Selection No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Isolated Output Power Supply 3.3V/2.5V Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 7 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A PIN CONFIGURATION 100-PIN TQFP (128K X 36) A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A ISSI 100-PIN TQFP (128K X 32) A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A ® DQPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC (3 Chip-Enable option) (3 Chip-Enable option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Controller Address Status Synchronous Processor Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Vss ZZ DQa-DQd DQPa-DQPd GW MODE OE VDD VDDQ Synchronous Data Input/Output Parity Data Input/Output Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable A ADSC ADSP ADV BWa-BWd BWE CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A PIN CONFIGURATION 100-PIN TQFP (256K X 18) A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A ISSI ® NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Controller Address Status Synchronous Processor Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable Synchronous Clock Synchronous Data Input/Output DQPa-DQPb GW MODE OE VDD VDDQ Vss ZZ Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable A ADSC ADSP ADV BWa-BWb BWE CLK DQa-DQb CE, CE2, CE2 Synchronous Chip Enable Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A (3 Chip-Enable Option) 9 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A TRUTH TABLE(1-8) OPERATION Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Snooze Mode, Power-Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS CE None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current H L L L L X L L L L L X X H H X H X X H H X H CE2 X X H X H X L L L L L X X X X X X X X X X X X CE2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC ADV L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H WRITE OE X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X ISSI CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D ® NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes 10 GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 ISSI ® LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN VDD Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Voltage on VDD Supply Relative to Vss Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to VDDQ + 0.5 V –0.5 to VDD + 0.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 11 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A OPERATING RANGE (IS61/64LPSXXXXX) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C VDD 3.3V + 5% 3.3V + 5% 3.3V + 5% VDDQ 3.3V / 2.5V + 5% 3.3V / 2.5V + 5% 3.3V / 2.5V + 5% ISSI ® OPERATING RANGE (IS61/64VPSXXXXX) Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C VDD 2.5V + 5% 2.5V + 5% 2.5V + 5% VDDQ 2.5V + 5% 2.5V + 5% 2.5V + 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Vss ≤ VIN ≤ VDD (1) Test Conditions IOH = –4.0 mA (3.3V) IOH = –1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) Min. 2.4 — 2.0 -0.3 -5 -5 Max. — 0.4 VDD + 0.3 0.8 5 5 Min. 2.0 — 1.7 -0.3 -5 -5 2.5V Max. — 0.4 VDD + 0.3 0.7 5 5 Unit V V V V µA µA Output Leakage Current Vss ≤ VOUT ≤ VDDQ, OE = VIH 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -250 MAX x18 x32/x36 225 250 275 225 250 275 ISSI -200 MAX x18 x32/x36 200 210 225 200 210 225 Unit mA ® Symbol Parameter ICC AC Operating Supply Current Test Conditions Device Selected, OE = VIH, ZZ ≤ VIL, All Inputs ≤ 0.2V or ≥ VDD – 0.2V, Cycle Time ≥ tKC min. Device Deselected, VDD = Max., All Inputs ≤ VIL or ≥ VIH, ZZ ≤ VIL, f = Max. Device Deselected, VDD = Max., VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f=0 ZZ>VIH Temp. range Com. Ind. Auto. ISB Standby Current TTL Input Com. Ind. Auto. Com. Ind. Auto. typ.(2) Com. Ind. Auto. typ.(2) 90 100 120 70 75 90 40 30 35 45 25 90 100 120 70 75 90 90 100 120 70 75 90 40 90 100 120 70 75 90 mA ISBI Standby Current CMOS Input mA ISB2 Sleep Mode 30 35 45 30 35 45 25 30 35 45 mA Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100µA maximum leakage current when tied to ≤ VSS + 0.2V or ≥ VDD – 0.2V. 2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 13 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF ISSI ® Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω ZO = 50Ω Output 50Ω 3.3V OUTPUT 5 pF Including jig and scope Figure 2 351 Ω 1.5V Figure 1 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ISSI ® 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5 I/O OUTPUT LOAD EQUIVALENT 1,667 Ω ZO = 50Ω Output 50Ω 2.5V OUTPUT 5 pF Including jig and scope Figure 4 1,538 Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 15 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -250 Symbol fMAX tKC tKH tKL tKQ tKQX (2) (2,3) ISSI Max. 250 — — — 2.6 — — 2.6 2.8 — 2.6 — — — — — — — — — — 2 2 -200 Min. Max. — 5 2 2 — 1.5 1 — — 0 — 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 — — 200 — — — 3.1 — — 3.0 3.1 — 3.0 — — — — — — — — — — 2 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc ® Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down Min. — 4.0 1.7 1.7 — 0.8 0.8 — — 0 — 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 — — tKQLZ tOEQ tOELZ tAS tWS tCES tAVS tDS tAH tWH tCEH tAVH tDH tPDS tPUS tKQHZ(2,3) (2,3) (2,3) tOEHZ Note: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A READ/WRITE CYCLE TIMING tKC ISSI ADSP is blocked by CE inactive ® CLK tSS tSH tKH tKL ADSP tSS tSH ADSC initiate read ADSC tAVS tAVH Suspend Burst ADV tAS tAH Address RD1 tWS tWH RD2 RD3 GW tWS tWH BWE BWx tCES tCEH CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a 2a 2b 2c 2d tKQHZ DATAIN High-Z Pipelined Read Single Read Burst Read Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 17 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A WRITE CYCLE TIMING tKC ISSI ® CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH Address WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BWx tCES tCEH WR1 WR2 CE Masks ADSP WR3 CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 OE High-Z tDS tDH DATAOUT DATAIN High-Z 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a Single Write Burst Write Write Unselected 18 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current Conditions ZZ ≥ Vih Min. — — 2 — 0 Max. 60 2 — 2 — ISSI Unit mA cycle cycle cycle ns ® SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 19 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ISSI Package 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA ® ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Commercial Range: 0°C to +70°C Configuration 128Kx32 250 IS61LPS12832A-250TQ IS61LPS12832A-250B2 IS61LPS12832A-250B3 200 IS61LPS12832A-200TQ IS61LPS12832A-200B2 IS61LPS12832A-200B3 IS61LPS12836A-250TQ IS61LPS12836A-250B2 IS61LPS12836A-250B3 IS61LPS12836A-200TQ IS61LPS12836A-200B2 IS61LPS12836A-200B3 IS61LPS25618A-250TQ IS61LPS25618A-250B2 IS61LPS25618A-250B3 IS61LPS25618A-200TQ IS61LPS25618A-200B2 IS61LPS25618A-200B3 Frequency Order Part Number 128Kx36 250 200 256Kx18 250 200 20 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Industrial Range: -40°C to +85°C Configuration 128Kx32 250 IS61LPS12832A-250TQI IS61LPS12832A-250B2I IS61LPS12832A-250B3I IS61LPS12832A-200TQI IS61LPS12832A-200TQLI IS61LPS12832A-200B2I IS61LPS12832A-200B3I IS61LPS12836A-250TQI IS61LPS12836A-250B2I IS61LPS12836A-250B3I IS61LPS12836A-200TQI IS61LPS12836A-200TQLI IS61LPS12836A-200B2I IS61LPS12836A-200B3I IS61LPS25618A-250TQI IS61LPS25618A-250B2I IS61LPS25618A-250B3I IS61LPS25618A-200TQI IS61LPS25618A-200TQLI IS61LPS25618A-200B2I IS61LPS25618A-200B3I 100 TQFP 119 PBGA 165 PBGA 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA Frequency Order Part Number Package ISSI ® 200 128Kx36 250 200 256Kx18 250 200 Automotive Range: -40°C to +125°C Configuration 128Kx32 200 128Kx36 200 256Kx18 200 IS64LPS25618A-200TQA3 100 TQFP IS64LPS12836A-200TQA3 100 TQFP IS64LPS12832A-200TQA3 100 TQFP Frequency Order Part Number Package Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 21 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration 128Kx36 250 IS61VPS12836A-250TQ IS61VPS12836A-250B2 IS61VPS12836A-250B3 200 IS61VPS12836A-200TQ IS61VPS12836A-200B2 IS61VPS12836A-200B3 256Kx18 250 IS61VPS25618A-250TQ IS61VPS25618A-250B2 IS61VPS25618A-250B3 200 IS61VPS25618A-200TQ IS61VPS25618A-200B2 IS61VPS25618A-200B3 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA Frequency Order Part Number Package ISSI ® 22 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A Industrial Range: -40°C to +85°C Configuration 128Kx36 250 IS61VPS12836A-250TQI IS61VPS12836A-250B2I IS61VPS12836A-250B3I IS61VPS12836A-200TQI IS61VPS12836A-200B2I IS61VPS12836A-200B3I IS61VPS25618A-250TQI IS61VPS25618A-250B2I IS61VPS25618A-250B3I IS61VPS25618A-200TQI IS61VPS25618A-200B2I IS61VPS25618A-200B3I 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA Frequency Order Part Number Package ISSI ® 200 256Kx18 250 200 Automotive Range: -40°C to +125°C Configuration 128Kx32 200 128Kx36 200 256Kx18 200 IS64VPS25618A-200TQA3 100 TQFP IS64VPS12836A-200TQA3 100 TQFP IS64VPS12832A-200TQA3 100 TQFP Frequency Order Part Number Package Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 10/07/04 23 PACKAGING INFORMATION Plastic Ball Grid Array Package Code: B (119-pin) ISSI φ b (119X) 7 6 5 4 32 1 A B C D E F G H J K L M N P R T U ® E A 30ϒ D D2 D1 e A2 E2 A3 A1 E1 A4 SEATING PLANE MILLIMETERS Sym. N0. Leads A A1 A2 A3 A4 b D D1 D2 E E1 E2 e — 0.50 0.80 1.30 0.60 21.80 19.40 13.80 11.90 INCHES Min. Max. Notes: Min. 119 Max. 2.41 0.70 1.00 1.70 0.90 22.20 19.60 14.20 12.10 — 0.020 0.032 0.051 0.024 0.858 0.764 0.543 0.469 0.095 0.028 0.039 0.067 0.035 0.874 0.772 0.559 0.476 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.56 BSC 0.022 BSC 20.32 BSC 0.800 BSC 7.62 BSC 1.27 BSC 0.300 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 02/12/03 PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) TOP VIEW A1 CORNER 1 A B C D E F G H J K L M N P R φ b (165X) ISSI BOTTOM VIEW A1 CORNER 9 8 7 6 5 4 3 2 1 A B C D ® 2 3 4 5 6 7 8 9 10 11 11 10 e E F G D D1 H J K L M N P R e E1 E A2 A1 A BGA - 13mm x 15mm MILLIMETERS Sym. N0. Leads A A1 A2 D D1 E E1 e b — 0.25 — 14.90 13.90 12.90 9.90 — 0.40 INCHES Min. Nom. Max. 165 Notes: 1. Controlling dimensions are in millimeters. Min. Nom. Max. 165 — 0.33 0.79 15.00 14.00 13.00 10.00 1.20 0.40 — 15.10 14.10 13.10 10.10 — 0.50 — 0.010 — 0.587 0.547 0.508 0.390 — 0.016 — 0.031 0.591 0.551 0.512 0.394 0.039 0.018 0.047 — 0.594 0.555 0.516 0.398 — 0.020 0.013 0.016 1.00 0.45 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ ISSI D D1 ® E E1 N 1 C e SEATING PLANE L1 L A2 A1 b A Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03