IS61SP25618-133TQ

IS61SP25616 IS61SP25618 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +3.3V, +10%, -5% power supply • Power-down snooze mode ISSI ® APRIL 2001 DESCRIPTION The ISSI IS61SP25616 and IS61SP25618 is a high-speed synchronous static RAM designed to provide a burstable, high-performance memory for high speed networking and communication applications. It is organized as 262,144 words by 16 bits and 18 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ t KC Parameter Clock Access Time Cycle Time Frequency -166 3.5 6 166 -150 3.8 6.7 150 -133 4 7.5 133 -5 5 10 100 Units ns ns MHz ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 1 IS61SP25616 IS61SP25618 BLOCK DIAGRAM ISSI ® MODE ADV CLK BURST COUNTER ADSC ADSP A2-A17 A1 A0 2 18 16 CLK2 CLR 2 18 256K x 16/256K x 18 MEMORY ARRAY ADDRESS REGISTER GW 16 or 18 16 or 18 BWE BW1 BW1 BYTE WRITE REGISTER BW2 BW2 BYTE WRITE REGISTER 2 CLK DATA INPUT REGISTER DATA OUTPUT REGISTER CLK2 CLK CE1 CE2 CE2 ENABLE REGISTER ENABLE REGISTER OE DQ1 - DQ16 or DQ1 - DQ18 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 IS61SP25616 IS61SP25618 PIN CONFIGURATION 119-pin PBGA (Top View) 100-Pin TQFP ISSI A6 A7 CE CE2 NC NC BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 ® 1 A VCCQ B NC C NC D DQ9 E NC F VCCQ G NC H DQ12 J VCCQ K NC L DQ14 M VCCQ N DQ16 P NC R NC T NC U VCCQ 2 3 4 5 6 7 A6 CE2 A7 NC DQ10 NC DQ11 NC VCC DQ13 NC DQ15 NC NC A5 A11 NC A4 A3 A2 GND GND GND BW2 GND NC GND GND GND GND GND MODE A10 NC ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC NC A8 A9 A12 GND GND GND GND GND NC GND BW1 GND GND GND NC A14 NC A16 CE2 A15 NC NC DQ7 NC DQ5 VCC NC DQ3 NC DQ2 NC A13 A17 NC VCCQ NC NC NC DQ8 VCCQ DQ6 NC VCCQ DQ4 NC VCCQ NC DQ1 NC ZZ VCCQ NC NC NC VCCQ GND NC NC DQ9 DQ10 GND VCCQ DQ11 DQ12 NC VCC NC GND DQ13 DQ14 VCCQ GND DQ15 DQ16 NC NC GND VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 A17 NC NC VCCQ GND NC NC DQ8 DQ7 GND VCCQ DQ6 DQ5 GND NC VCC ZZ DQ4 DQ3 VCCQ GND DQ2 DQ1 NC NC GND VCCQ NC NC NC 256K x 16 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable BWE GW OE DQ1-DQ16 MODE VCC GND VCCQ ZZ Synchronous Byte Write Enable Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable A2-A17 CLK ADSP ADSC ADV BW1-BW2 CE, CE2, CE2 Synchronous Chip Enable Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 3 IS61SP25616 IS61SP25618 PIN CONFIGURATION ISSI 100-Pin TQFP 7 A6 A7 CE CE2 NC NC BW2 BW1 CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9 ® 119-pin PBGA (Top View) 1 A VCCQ B NC C NC D DQ9 E NC F VCCQ G NC H DQ12 J VCCQ K NC L DQ14 M VCCQ N DQ16 P NC R NC T NC U VCCQ NC NC NC NC NC VCCQ A11 A10 NC A14 A17 ZZ A5 MODE VCC GND A13 NC DQP2 GND A0 GND NC DQ1 NC GND A1 GND DQ2 NC DQ15 GND NC GND NC BWE DQ13 GND CLK GND BW1 GND NC DQ3 NC DQ4 NC VCCQ VCC NC VCC NC VCC VCCQ NC GND DQ11 NC GND BW2 DQ10 GND NC GND NC CE OE ADV GW GND GND GND GND GND DQP1 NC DQ7 NC DQ5 NC DQ8 VCCQ DQ6 NC A7 A2 VCC A12 A15 NC CE2 A3 A6 A4 2 3 4 5 6 ADSP ADSC A8 A9 A16 CE2 VCCQ NC NC NC NC VCCQ GND NC NC DQ9 DQ10 GND VCCQ DQ11 DQ12 NC VCC NC GND DQ13 DQ14 VCCQ GND DQ15 DQ16 DQP2 NC GND VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A17 NC NC VCCQ GND NC DQP1 DQ8 DQ7 GND VCCQ DQ6 DQ5 GND NC VCC ZZ DQ4 DQ3 VCCQ GND DQ2 DQ1 NC NC GND VCCQ NC NC NC 256K x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable GW OE DQ1-DQ16 MODE VCC GND VCCQ ZZ DQP1-DQP2 Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V Snooze Enable Parity Data I/O DQP1 is parity for DQ1-8; DQP2 is parity for DQ9-16 CE, CE2, CE2 Synchronous Chip Enable A2-A17 CLK ADSP ADSC ADV BW1-BW2 BWE 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16 IS61SP25616 IS61SP25618 TRUTH TABLE Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L X X L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L X L X H L H L L X H L H L H H H H X H X H H H X H H H H H X H X H H H X H ADV WRITE X X X X X X X X X X X X X Read X Write L Read L Read L Read L Read L Write L Write H Read H Read H Read H Read H Write H Write ISSI OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D ® PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 5 IS61SP25616 IS61SP25618 INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 ISSI ® LINEAR BURST ADDRESS TABLE (MODE = GND) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN VCC Parameter Value Unit Temperature Under Bias –40 to +85 °C Storage Temperature –55 to +150 °C Power Dissipation 1.6 W Output Current (per I/O) 100 mA Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V Voltage Relative to GND for –0.5 to VCC + 0.5 V for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 IS61SP25616 IS61SP25618 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V, +10%, –5% 3.3V, +10%, –5% ISSI ® DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions IOH = –4.0 mA IOL = 8.0 mA Min. 2.4 — 2.0 –0.3 –2 –5 –2 –5 Max. — 0.4 VCCQ + 0.3 0.8 2 5 2 5 Unit V V V V µA µA GND ≤ VIN ≤ VCCQ(2) GND ≤ VOUT ≤ VCCQ, OE = VIH Com. Ind. Com. Ind. POWER SUPPLY CHARACTERISTICS (Over Operating Range) -166 Max. 210 — -150 Max. 190 200 -133 Max 170 180 -5 Max. 160 170 Symbol ICC Parameter AC Operating Supply Current ISB Standby Current IZZ Power-down Mode Current Test Conditions Device Selected, Com. All Inputs = VIL or VIH Ind. OE = VIH, Vcc = Max. Cycle Time ≥ tKC min. Device Deselected, Com. VCC = Max., Ind. All Inputs = VIH or VIL CLK Cycle Time ≥ tKC min. ZZ = VCC Com. Clock Running Ind. All Inputs ≤ GND + 0.2V or ≥ Vcc – 0.2V Unit mA mA 60 — 60 70 60 70 60 70 mA mA 15 — 15 20 15 20 15 20 mA mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC. 2. The MODE pin could be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ Vcc – 0.2V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 7 IS61SP25616 IS61SP25618 CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF ISSI ® Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS ZO = 50Ω Output Buffer 50Ω 317 Ω 3.3V 30 pF OUTPUT 5 pF Including jig and scope 351 Ω 1.5V Figure 1 Figure 2 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 IS61SP25616 IS61SP25618 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol fMAX(3) tKC(3) tKH tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tWS(3) tCES(3) tAVS(3) tAH(3) tSH(3) tWH(3) tCEH(3) tAVH(3) Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -166 Min. Max. — 166 6 — 2.4 — 2.4 — — 3.5 3 — 0 — 1.5 3.5 — 3.5 0 — 0 — 2 3.5 2 — 2 — 2 — 2 — 2 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ISSI -150 Min. Max. — 150 6.7 — 2.6 — 2.6 — — 3.8 3 — 0 — 1.5 3.5 — 3.5 0 — 0 — 2 3.5 2 — 2 — 2 — 2 — 2 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — -133 Min. Max. — 133 7.5 — 2.8 — 2.8 — — 4 3 — 0 — 1.5 3.5 — 3.8 0 — 0 — 2 3.8 2 — 2 — 2 — 2 — 2 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — -5 Min. — 10 3 3 — 3 0 1.5 — 0 0 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 Max. 100 — — — 5 — — 3.5 5 — — 5 — — — — — — — — — — ® Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 9 IS61SP25616 IS61SP25618 READ/WRITE CYCLE TIMING tKC ISSI tKH tKL ® CLK tSS tSH ADSP is blocked by CE inactive tSH ADSP tSS ADSC initiate read ADSC tAVS tAVH Suspend Burst ADV tAS tAH A17-A0 RD1 tWS tWH RD2 RD3 GW tWS tWH BWE BW2-BW1 tCES tCEH CE Masks ADSP CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a 2a 2b 2c 2d 3a tKQHZ DATAIN High-Z Pipelined Read Single Read Burst Read Unselected 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 IS61SP25616 IS61SP25618 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -166 ISSI Min. 6 2.4 2.4 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 Max. — — — — — — — — — — — — — — — -150 Min. 6.7 2.6 2.6 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 Max. — — — — — — — — — — — — — — — -133 Min. 7.5 2.8 2.8 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 -5 Max. — — — — — — — — — — — — — — — Min. 10 4 4 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 Max. — — — — — — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® Symbol tKC(1) tKH(1) tKL(1) tAS(1) tSS(1) tWS(1) tDS(1) tCES(1) tAVS(1) tAH(1) tSH(1) tDH(1) tWH(1) tCEH(1) tAVH(1) Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Note: 1. Tested with load in Figure 1. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 11 IS61SP25616 IS61SP25618 WRITE CYCLE TIMING tKC ISSI tKH tKL ® CLK tSS tSH ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A17-A0 WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BW2-BW1 tCES tCEH WR1 WR2 CE Masks ADSP WR3 CE tCES tCEH CE2 and CE2 only sampled with ADSP or ADSC Unselected with CE2 CE2 tCES tCEH CE2 OE DATAOUT High-Z tDS tDH BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a DATAIN High-Z 1a Single Write Burst Write Write Unselected 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 IS61SP25616 IS61SP25618 ISSI -166 Min. 6 2.4 2.4 — 1.5 0 1.5 — 0 0 2 2 2 2 0.5 0.5 0.5 2 2 ® SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC(3) tKH(3) tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tCES(3) tAH(3) tSH(3) tCEH(3) tZZS tZZREC Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery Max. — — — 3.5 — — 3.5 3.5 — — 3.5 — — — — — — — — -150 Min. 6.7 2.6 2.6 — 1.5 0 1.5 — 0 0 2 2 2 2 0.5 0.5 0.5 2 2 Max. — — — 3.8 — — 3.5 3.5 — — 3.5 — — — — — — — — -133 Min. 7.5 2.8 2.8 — 1.5 0 1.5 — 0 0 2 2 2 2 0.5 0.5 0.5 2 2 -5 Max. — — — 4 — — 3.5 3.9 — — 3.8 — — — — — — — — Min. 10 4 4 — 2.5 0 1.5 — 0 0 2 2 2 2 0.5 0.5 0.5 2 2 Max. — — — 5 — — 3.5 5 — — 5 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 13 IS61SP25616 IS61SP25618 SNOOZE AND RECOVERY CYCLE TIMING tKC ISSI tSH tKH tKL ® CLK tSS ADSP ADSC ADV tAS tAH A17-A0 RD1 RD2 GW BWE BW2-BW1 tCES tCEH CE tCES tCEH CE2 tCES tCEH CE2 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ tZZS tZZREC DATAIN ZZ High-Z Single Read Snooze with Data Retention Read 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 IS61SP25616 IS61SP25618 ISSI ORDERING INFORMATION Commercial Range: 0°C to +70°C Package TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA Speed 166 MHz 150 MHz 133 MHz 5 ns Order Part Number IS61SP25618-166TQ IS61SP25618-166B IS61SP25618-150TQ IS61SP25618-150B IS61SP25618-133TQ IS61SP25618-133B IS61SP25618-5TQ IS61SP25618-5B Package TQFP PBGA TQFP PBGA TQFP PBGA TQFP PBGA ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed 166 MHz 150 MHz 133 MHz 5 ns Order Part Number IS61SP25616-166TQ IS61SP25616-166B IS61SP25616-150TQ IS61SP25616-150B IS61SP25616-133TQ IS61SP25616-133B IS61SP25616-5TQ IS61SP25616-5B Industrial Range: –40°C to +85°C Speed 150 MHz 133 MHz 5 ns Order Part Number IS61SP25616-150TQI IS61SP25616-133TQI IS61SP25616-5TQI Package TQFP TQFP TQFP Industrial Range: –40°C to +85°C Speed 150 MHz 133 MHz 5 ns Order Part Number IS61SP25618-150TQI IS61SP25618-133TQI IS61SP25618-5TQI Package TQFP TQFP TQFP ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 04/17/01 15