IS62C1024L-35T

IS62C1024L 128K x 8 LOW POWER CMOS STATIC RAM ISSI DECEMBER 2003 ® FEATURES • High-speed access time: 35, 70 ns • Low active power: 450 mW (typical) • Low standby power: 150 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V (±10%) power supply DESCRIPTION The ISSI IS62C1024L is a low power,131,072-word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C1024L is available in 32-pin plastic SOP and TSOP (type 1) packages. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 8 MEMORY ARRAY VDD GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 1 IS62C1024L PIN CONFIGURATION 32-Pin SOP ISSI PIN CONFIGURATION 32-Pin TSOP (Type 1) 32 31 30 29 VDD A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 ® NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 ISSI 28 6 62C1024L 27 26 7 8 9 10 11 12 13 14 15 16 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 WE CE2 A15 VDD NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A16 CE1 CE2 OE WE I/O0-I/O7 VDD GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output Power Ground OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD 5V ± 10% 5V ± 10% TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN VDD Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 IS62C1024L ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 1.5 20 Unit V °C W mA ISSI ® Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions VDD = Min., IOH = –1.0 mA VDD = Min., IOL = 2.1 mA Min. 2.4 — 2.2 –0.3 –2 –10 –2 –10 Max. — 0.4 VDD + 0.5 0.8 2 10 2 10 Unit V V V V µA µA GND ≤ VIN ≤ VDD GND ≤ VOUT ≤ VDD Com. Ind. Com. Ind. Notes: 1. VIL = –3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 3 IS62C1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC ISB1 Parameter VDD Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = fMAX VDD = Max., VIN = VIH or VIL, CE1 ≥ VIH, or CE2 ≤ VIL, f = 0 Com. Ind. Com. Ind. -35 ns Min. Max. — — — — — — 100 110 10 15 500 750 -70 ns Min. Max. — — — — — — 70 80 10 15 500 750 ISSI Unit mA mA ® ISB2 VDD = Max., Com. CE1 ≤ VDD – 0.2V, Ind. CE2 ≤ 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time (2) (2) -35 Min. Max. 35 — 3 — — — 0 0 3 3 0 — 35 — 35 35 10 — 10 — — 10 -70 Min. Max. 70 — 3 — — — 0 0 10 10 0 — 70 — 70 70 35 — 25 — — 25 Unit ns ns ns ns ns ns ns ns ns ns ns tRC tAA tOHA tACE1 tACE2 tDOE tLZOE tHZOE OE to Low-Z Output OE to High-Z Output CE1 to Low-Z Output CE2 to Low-Z Output CE1 or CE2 to High-Z Output tLZCE1(2) tLZCE2 tHZCE (2) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 IS62C1024L AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 5 ns 1.5V See Figures 1a and 1b ISSI ® AC TEST LOADS 480 Ω 5V 480 Ω 5V OUTPUT 100 pF Including jig and scope 255 Ω OUTPUT 5 pF Including jig and scope 255 Ω Figure 1a. Figure 1b. AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 5 IS62C1024L READ CYCLE NO. 2(1,3) ISSI tRC ® ADDRESS tAA tOHA OE tDOE tHZOE CE1 tACE1/tACE2 tLZOE CE2 tLZCE1/ tLZCE2 HIGH-Z tHZCE DATA VALID DOUT Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time (4) -35 Min. Max. 35 25 25 25 0 0 25 20 0 — 3 — — — — — — — — — 10 — -70 Min. Max. 70 60 60 60 0 0 50 30 0 — 5 — — — — — — — — — 25 — Unit ns ns ns ns ns ns ns ns ns ns ns tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE(2) tLZWE (2) WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 IS62C1024L AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ISSI ® ADDRESS tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE(4) tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2) tWC ADDRESS tSA tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE(4) WE tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 7 IS62C1024L DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 3.0V, CE1 ≥ VDD – 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Min. 2.0 — — 0 45 60 Typ. ISSI Max. 5.5 250 400 — — Unit V µA ns ns ® VDR IDR tSDR tRDR tRC DATA RETENTION WAVEFORM (CE1 Controlled) tSDR VDD 4.5V Data Retention Mode tRDR 2.2V VDR CE1 ≥ VDD - 0.2V CE1 GND DATA RETENTION WAVEFORM (CE2 Controlled) Data Retention Mode VDD 4.5V CE2 2.2V VDR 0.4V GND CE2 ≤ 0.2V tSDR tRDR 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 IS62C1024L ISSI Package Plastic SOP TSOP, Type 1 Plastic SOP TSOP, Type 1 ® ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 35 35 70 70 Order Part No. IS62C1024L-35Q IS62C1024L-35T IS62C1024L-70Q IS62C1024L-70T Industrial Range: –40°C to +85°C Speed (ns) 35 35 70 70 Order Part No. IS62C1024L-35QI IS62C1024L-35TI IS62C1024L-70QI IS62C1024L-70TI Package Plastic SOP TSOP, Type 1 Plastic SOP TSOP, Type 1 ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. E 11/26/03 9 PACKAGING INFORMATION 450-mil Plastic SOP Package Code: Q (32-pin) ISSI ® N E1 E 1 D SEATING PLANE S A e B L A1 α C MILLIMETERS Symbol No. Leads A A1 B C D E E1 e L α S Min. Max. 32 — 3.00 0.10 — 0.36 0.51 0.15 0.30 20.14 20.75 13.87 14.38 11.18 11.43 1.27 BSC 0.58 0.99 0° 10° — 0.86 INCHES Min. Max. — 0.118 0.004 — 0.014 0.020 0.006 0.012 0.793 0.817 0.546 0.566 0.440 0.450 0.050 BSC 0.023 0.039 0° 10° — 0.034 Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03 PACKAGING INFORMATION Plastic TSOP-Type I Package Code: T (32-pin) 1 ISSI ® E H N D SEATING PLANE S A e B L A1 α C MILLIMETERS Symbol No. Leads A A1 B C D E H e L α S Min. Max. 32 — 1.20 0.05 0.25 0.17 0.23 0.12 0.17 7.90 8.10 18.30 18.50 19.80 20.20 0.50 BSC 0.40 0.60 0° 8° 0.25 REF INCHES Min. Max. — 0.047 0.002 0.010 0.007 0.009 0.005 0.007 0.311 0.319 0.720 0.728 0.780 0.795 0.020 BSC 0.016 0.024 0° 8° 0.010 REF Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 06/13/03