IS62LV2568LL-70H

IS62LV2568LL 256K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM FEATURES • Access times of 70 and 85 ns • CMOS low power operation: — 120 mW (typical) operating — 6 µW (typical) standby • Low data retention voltage: 2V (min.) • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • TTL compatible inputs and outputs • Fully static operation: — No clock or refresh required • Single 2.5V to 3.0V power supply • Available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA ISSI DESCRIPTION ® APRIL 2000 The ISSI IS62LV2568LL is a low voltage, 262,144 words by 8 bits, CMOS SRAM. It is fabricated using ISSI’s low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV2568LL is available in 32-pin TSOP (Type I), STSOP (Type I), and 36-pin mini BGA. FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE1 CE2 OE WE CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 1 IS62LV2568LL PIN CONFIGURATION 36-pin mini BGA (B) 1 2 3 4 5 6 ISSI PIN DESCRIPTIONS A0-A17 CE1 CE2 OE WE Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Input/Output No Connection Power Ground ® A B C D E F G H A0 I/O4 I/O5 GND Vcc I/O6 I/O7 A9 A1 A2 CE2 WE NC A3 A4 A5 A6 A7 A8 I/O0 I/O1 Vcc GND I/O0-I/O7 NC Vcc GND NC OE A10 CE1 A11 A17 A16 A12 A15 A13 I/O2 I/O3 A14 32-Pin TSOP (Type I), STSOP (Type I) A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 IS62LV2568LL ISSI CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC ICC ICC X X H H L ® TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 2.5V to 3.0V 2.5V to 3.0V ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value –0.5 to Vcc + 0.5 –0.3 to +4.6 –40 to +85 –65 to +150 0.7 Unit V V °C °C W Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 3 IS62LV2568LL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage Test Conditions VCC = Min., IOH = –1.0 mA VCC = Min., IOL = 2.1 mA Min. 2.0 — 2.2 –0.3 –1 –1 ISSI Max. — 0.4 VCC + 0.3 0.4 1 1 V V V V µA µA ® Unit GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Note: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter I CC Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. -70 Min. Max. — — — — — — 30 35 0.4 1.0 5 5 -85 Min. Max. — — — — — — 25 30 0.4 1.0 5 5 Unit mA ISB1 VCC = Max., Com. VIN = VIH or VIL, Ind. CE1 ≥ VIH or CE2 ≤ VIL, f = 0 VCC = Max., f = 0 Com. CE1 ≥ VCC – 0.2V, Ind. CE2 ≤ 0.2V, or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V mA ISB2 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 IS62LV2568LL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -70 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time (2) ISSI -85 Max. — 70 — 70 70 35 25 — — — 25 Min. 85 — 15 — — — — 5 10 10 0 Max. — 85 — 85 85 45 25 — — — 25 Unit ns ns ns ns ns ns ns ns ns ns ns Min. 70 — 10 — — — — 5 10 10 0 ® tRC tAA tOHA tACE1 tACE2 tDOE tHZOE tLZOE (2) OE to High-Z Output OE to Low-Z Output CE1 to Low-Z Output CE2 to Low-Z Output CE1 or CE2 to High-Z Output tLZCE1(2) tLZCE2 tHZCE (2) (2) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V See Figures 1 and 2 AC TEST LOADS 3070 Ω 2.8V 2.8V 3070 Ω OUTPUT 30 pF Including jig and scope 3150 Ω OUTPUT 5 pF Including jig and scope 3150 Ω Figure 1 Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 5 IS62LV2568LL AC WAVEFORMS READ CYCLE NO. 1(1,2) ISSI ® tRC ADDRESS tAA tOHA tOHA DATA VALID DOUT READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE1 tACE1/tACE2 tLZOE CE2 tLZCE1/ tLZCE2 HIGH-Z tHZCE DATA VALID DOUT Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 IS62LV2568LL ISSI -70 -85 Max. — — — — — — — — — 33 — Min. 85 70 70 70 0 0 60 35 0 — 5 Max. — — — — — — — — — 25 — Unit ns ns ns ns ns ns ns ns ns ns ns Min. 70 65 65 65 0 0 60 30 0 — 5 ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time (4) tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE(2) tLZWE (2) WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW) tWC ADDRESS tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE(4) tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 7 IS62LV2568LL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ISSI ® ADDRESS OE tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE1, 2 tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE1, 2 tSA tHZWE HIGH-Z WE tLZWE DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 IS62LV2568LL DATA RETENTION SWITCHING CHARACTERISTICS Symbol VDR I DR t SDR t RDR Parameter Vcc for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vcc = 2.0V, CE1 ≥ Vcc – 0.2V See Data Retention Waveform See Data Retention Waveform Com. Ind. Min. 2.0 — — 0 t RC ISSI Max. 3.6 2 5 — — Unit V µA µA ns ns ® DATA RETENTION WAVEFORM (CE1 Controlled) tSDR VCC Data Retention Mode tRDR 3.0V 2.2V VDR CE1 ≥ VCC Ð 0.2V CE1 GND DATA RETENTION WAVEFORM (CE2 Controlled) Data Retention Mode VCC tSDR tRDR 3.0 CE2 2.2V VDR 0.4V GND CE2 ≤ 0.2V Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00 9 IS62LV2568LL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 70 IS62LV2568LL-70B IS62LV2568LL-70T IS62LV2568LL-70H IS62LV2568LL-85B IS62LV2568LL-85T IS62LV2568LL-85H Package mini BGA (6mm x 8mm) TSOP, Type I STSOP, Type I mini BGA (6mm x 8mm) TSOP, Type I STSOP, Type I ISSI ® 85 Industrial Range: –40°C to +85°C Speed (ns) Order Part No. 70 IS62LV2568LL-70BI IS62LV2568LL-70TI IS62LV2568LL-70HI IS62LV2568LL-85BI IS62LV2568LL-85TI IS62LV2568LL-85HI Package mini BGA (6mm x 8mm) TSOP, Type I STSOP, Type I mini BGA (6mm x 8mm) TSOP, Type I STSOP, Type I 85 ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 05/03/00