HE847701

King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES - Table of Contents 1. 2. 3. 4. 5. 6. 7. 7.1. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. General Description ___________________________________________________________________2 Features _____________________________________________________________________________2 Functional Block Diagram ______________________________________________________________3 Pin Description _______________________________________________________________________3 Pad Location _________________________________________________________________________6 LCD RAM Map ______________________________________________________________________8 LCD Power Supply ___________________________________________________________________11 LCDC Control register _____________________________________________________________14 Oscillators __________________________________________________________________________14 General Purpose I/O__________________________________________________________________16 Key Scan Circuit___________________________________________________________________17 Timer1 ___________________________________________________________________________19 Timer2 ___________________________________________________________________________20 Time Base Interrupt________________________________________________________________22 Watch Dog Timer __________________________________________________________________22 Digital-to-Analog Converter _________________________________________________________23 Pulse-Width Modulation ____________________________________________________________24 Absolute Maximum Rating __________________________________________________________25 Recommended Operating Conditions _________________________________________________25 AC/DC Characteristics _____________________________________________________________25 Application Circuit_________________________________________________________________27 Important Note ____________________________________________________________________28 Updated Record ___________________________________________________________________29 March 26, 2004 Page 1 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 1. General Description HE847701 is a member of 8-bit Micro-controller series developed by King Billion Electronics. Four LCD driver configurations, 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or 80 COM x 80 SEG are available by mask option. 24 LCD segment driver pins multiplexed with I/O pins to provide flexibility of wide variety of combinations to suit the needs of applications. The built-in LCD power supply is equipped with voltage charge-pump circuit to generate the high voltage required by the high duty LCD driver, bias voltage generating circuit and input voltage regulator circuit to supply stable LCD display effect over the wide battery life. The built-in OP comparator can be used with (light, voice, temperature, humility) sensor and used as battery low detection. 7-bit current-type D/A converter and PWM device provide the complete speech output mechanism. The 2M ROM Size can be used in the storage of speech, graphic, text, etc. It is ideal for applications such as Translator, Data Bank, Educational Toy, Digital Voice Recording System, etc. The instruction set of HE80000 series is easy to learn and simple to use. Only about thirty instructions with four-type addressing mode are provided. Most of instructions take only 3 oscillator clocks to execute. The processing power is enough to most of battery operation system. 2. Features Operation Voltage: System Clock: 2.4V ~ 3.6V DC ~ 8 MHz @ VDD=3.6V and VDD－VDD_RAM ≦0.3Volt. DC ~ 6 MHz @ VDD=2.4V and VDD－VDD_RAM ≦0.3Volt. Internal ROM: 2M Bytes (256 KB Program ROM + 1792 KB Data ROM) Internal RAM: 16K Bytes Dual Clock System: Fast clock: 32768 ~ 8M Hz (No Internal Clock) Slow clock: 32768 Hz Operation modes: Fast, Slow, Idle and Sleep modes. 24 ~ 48 bit bi-directional general purpose I/O port with push-pull or Open-Drain output type selectable for each I/O pin by mask option. 24 of them are multiplexed with LCD segment pins. Built-in 4x20 hardware keyboard scan circuit (multiplexed with LCD SEG pin) helps to reduce the pin counts as well as the firmware effort. Voltage Detector with two detecting thresholds. Four LCD configurations: 32 COM x 128 SEG, 48 COM x 112 SEG, 64 COM x 96 SEG or 80 COM x 80 SEG. All of LCD configurations are B TYPE. Built-in LCD power supply with input voltage regulator, voltage charge pump and bias voltage generating circuit. One 7-bit current-type DAC output. Single-ended Pulse Width Modulation circuit for alternative voice output. Built-in OP comparator. Two 16-bit timers and one Time-Base timer. Watch Dog Timer to prevent deadlock condition. Two external interrupts and three internal timer interrupts. Instruction set: 32 instructions with 4 addressing mode. March 26, 2004 Page 2 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 3. Functional Block Diagram SEG COM LCD Driver LCD Extender Interface LCD Power Supply I/O Port 8 Bit CPU 2 MB ROM 16 KB RAM Fast Clock OSC. Slow Clock OSC PWM FXI, FXO LFR, LDL SXI, SXO LVL[1..5], LCDGS, PWM TC1 TC2 TBI PRTC, PRTD, PRT10, PRT14, PRT15, PRT17 DAC VO, DAO SGKY[43..24] Key Scan WDT OP Amp OPO,OPIN, OPIP 4. Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SEG48 SEG47 SEG46 SEG45 SEG44 SGKY 43 SGKY 42 SGKY 41 SGKY 40 SGKY 39 SGKY 38 SGKY 37 SGKY 36 SGKY 35 SGKY 34 SGKY 33 SGKY 32 SGKY 31 SGKY 30 SGKY 29 SGKY 28 SGKY 27 SGKY 26 SGKY 25 SGKY 24 PRT147 PRT146 PRT145 PRT144 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 CMSG79 CMSG78 CMSG77 CMSG76 CMSG75 CMSG74 CMSG73 CMSG72 CMSG71 CMSG70 CMSG69 CMSG68 CMSG67 CMSG66 CMSG65 CMSG64 CMSG63 CMSG62 CMSG61 CMSG60 CMSG59 CMSG58 CMSG57 CMSG56 CMSG55 CMSG54 CMSG53 CMSG52 CMSG51 CMSG50 CMSG49 CMSG48 CMSG47 CMSG46 CMSG45 CMSG44 CMSG43 CMSG42 CMSG41 CMSG40 CMSG39 CMSG38 CMSG37 CMSG36 CMSG35 CMSG34 CMSG33 CMSG32 VDD_RAM H E847701 PRTC0 PRTC1 PRTC2 PRTC3 PRTC4 PRTC5 PRTC6 PRTC7 PWM GND_PWM PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 PRT100 PRT101 PRT102 PRT103 PRT104 PRT105 PRT106 PRT107 VDD SXI SXO 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 Pin # I/O Description 188~218 SEG[79..44] O LCD segment SEG[79..44] driver outputs. ,1~5 LCD segments share pads with key scan out SCNO[19..0]. The key scan function of SGKY[43..24] 6 ~ 25 O these pins can be disabled by mask option clearing MO_LCDKEY to ‘0’, then SGKY[43..24] function as LCD segment driver only. Setting MO_LCDKEY to ‘1’ Pin Name March 26, 2004 This specification is subject to change without notice. Please contact sales person for the latest version before use. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 PRT143 PRT142 PRT141 PRT140 PRT157 PRT156 PRT155 PRT154 PRT153 PRT152 PRT151 PRT150 PRT177 PRT176 PRT175 PRT174 PRT173 PRT172 PRT171 PRT170 COM31 COM30 COM29 COM28 COM27 COM26 COM25 C0M24 C0M23 C0M22 C0M21 C0M20 C0M19 C0M18 C0M17 C0M16 C0M15 C0M14 C0M13 C0M12 C0M11 C0M10 C0M9 C0M8 C0M7 C0M6 C0M5 C0M4 C0M3 COM2 COM1 COM0 LVL1 LVL2 LVL3 LVL4 LVL5 LCAP4A LCAP4B LCAP3A LCAP3B LCAP2A LCAP2B LCAP1A LCAP1B LCDGS LCDVX LCDVTB LFR LDL GND VO DAO OPIN OPIP OPO RSTP_N FXO FXI TSTP Page 3 of 29 V1.03 King Billion Electronics Co., Ltd 駿 Pin Name Pin # I/O 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES PRT14[7..0] 26 ~ 33 B/ O PRT15[7..0] 34 ~ 41 B/ O PRT17[7..0] 42 ~ 49 B/ O COM[31..0] LVL1 LVL2 LVL3 LVL4 LVL5 LCAP4A LCAP4B LCAP3A LCAP3B LCAP2A LCAP2B LCAP1A LCAP1B LCDGS LCDVX LCDVTB LFR LDL GND VO DAO OPIN OPIP OPO RSTP_N 50 ~ 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 O B B B B B B B B B B B B B B B B O O P O O I I O I Description will turn on the key scan function. 8-bit bi-directional I/O port 14 is shared with LCD segment pads SEG[23..16]. The function of the pad can be selected individually by mask options MO_LIO14[7..0]. (‘1’ for LCD and ‘0’ for I/O). The output type of I/O pad can also be selected by mask option MO_14PP[7..0] (1 for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, “1” must be outputted before reading. 8-bit bi-directional I/O port 15 is shared with LCD segment pads SEG[16..8]. The function of the pad can be selected individually by mask options MO_LIO15[7..0]. (‘1’ for LCD and ‘0’ for I/O). The output type of I/O pad can also be selected by mask option MO_15PP[7..0] (1 for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, “1” must be outputted before reading. 8-bit bi-directional I/O port 17 is shared with LCD segment pads SEG[7..0]. The function of the pad can be selected individually by mask options MO_LIO17[7..0]. (‘1’ for LCD and ‘0’ for I/O). The output type of I/O pad can also be selected by mask option MO_17PP[7..0] (1 for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, “1” must be outputted before reading. LCD COMMON Driver pads. LCD Bias Voltage 1 LCD Bias Voltage 2 LCD Bias Voltage 3 LCD Bias Voltage 4 LCD Bias Voltage 5 Charge Pump Capacitor Pin Charge Pump Capacitor Pin. Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin Charge Pump Capacitor Pin LCD Voltage setting. Adjust Resistor between LCDGS and LVL2 to set LVL5. Charge Pump Capacitor Pin Charge Pump Capacitor Pin LCD frame signal for interfacing with LCD segment extender KD80. LCD data load pin for interfacing with LCD segment extender KD80. Power ground Input. DAC Voice Output. Set the bit 1 and clear the bit 0 of VOC (DA = ‘1’ and OP = ‘0’) register to turn on DAC with VO output. Alternate output of DAC. Set both bit 1 and bit 0 of VOC register (DA = ‘1’ and OP = ‘1’) to turn on DAC with DAO output as well as OP comparator. Inverting input of OP Amp. Set the bit 0 of VOC register (OP = ‘1’) to turn on OP comparator. Non-inverting input of OP Amp. Output of OP Amp. System Reset input pin. Level trigger, active low on this pin will put the chip in reset state. March 26, 2004 Page 4 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 Pin Name FXO, FXI TSTP_P SXO, SXI VDD PRT10[7..0] Pin # I/O 107, 108 109 110, 111 112 O, B I O, I P 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 113~120 B PRTD[7..0] 121~128 B GND_PWM PWM 129 130 O O PRTC[7..0] 131 ~ 138 B VDD_RAM 139 P CMSG[32..79] 140~187 O Description External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for RC type and ‘1’ for crystal type). For RC type oscillator, one resistor need to be connected between FXI and GND. For crystal oscillator, one crystal need to be placed between FXI and FXO. Please refer to application circuit for details. Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for improving ESD, please connect this point with zero Ohm resistor to GND. External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type and ‘1’ for crystal oscillator. Positive power Input. 0.1 µF decoupling capacitors should be placed as close to IC VDD and GND pads as possible for best decoupling effect. 8-bit bi-directional I/O port 10. The output type of I/O pad can be selected by mask option MO_10PP[7..0] (‘1’ for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O pad as input pad, “1” must be outputted before reading. 8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, ‘1’ must be outputted before reading the pin. PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources. Dedicated Ground for PWM output. The PWM output can drive speaker or buzzer directly. Set the bit2 of VOC register as one to turn on PWM. Using VDD & PWM to drive output device. 8-bit bi-directional I/O port C. PRTC[7:4] is shared with Key Scan Dedicated Input SCNI[3:0]. The Key Scan function can be disabled by clearing MO_LCDKEY mask option to ‘0’. The output type of I/O pad can also be selected by mask option MO_CPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, ‘1’ must be outputted before reading the pin. Dedicated power input for RAM COM[32..79] pads are shared with SEG[127..80] outputs. The functions of the pads to be COM drivers or SEG drivers can be selected by mask option MO_COM[0]. Please refer to LCD driver configuration for details. I: Input, O: Output, B: Bidirectional, P: Power. March 26, 2004 Page 5 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 5. Pad Location Die Size: X= 9460 µm, Y=4150 µm, and substrate is connected to GND. Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SGKY[43] SGKY[42] SGKY[41] SGKY[40] SGKY[39] SGKY[38] SGKY[37] SGKY[36] SGKY[35] SGKY[34] SGKY[33] SGKY[32] SGKY[31] SGKY[30] SGKY[29] SGKY[28] SGKY[27] SGKY[26] SGKY[25] SGKY[24] X Coord. Y-Coord. Pin No. -4652.4 1615.02 110 -4652.4 1500.02 111 -4652.4 1385.02 112 -4652.4 1270.02 113 -4652.4 1155.02 114 -4652.4 1040.02 115 -4652.4 925.02 116 -4652.4 810.02 117 -4652.4 695.02 118 -4652.4 580.02 119 -4652.4 465.02 120 -4652.4 350.02 121 -4652.4 235.02 122 -4652.4 120.02 123 -4652.4 5.02 124 -4652.4 -109.98 125 -4652.4 -224.98 126 -4652.4 -339.98 127 -4652.4 -454.98 128 -4652.4 -569.98 129 -4652.4 -684.98 130 -4652.4 -799.98 131 -4652.4 -914.98 132 -4652.4 -1029.98 133 -4652.4 -1144.98 134 Pin name SXO SXI VDD PRT10[7] PRT10[6] PRT10[5] PRT10[4] PRT10[3] PRT10[2] PRT10[1] PRT10[0] PRTD[7] PRTD[6] PRTD[5] PRTD[4] PRTD[3] PRTD[2] PRTD[1] PRTD[0] GND_PWM PWM PRTC[7] PRTC[6] PRTC[5] PRTC[4] X Coord. Y-Coord. 4637.6 -1693.22 4637.6 -1578.22 4637.6 -1458.22 4637.6 -1343.22 4637.6 -1228.22 4637.6 -1113.22 4637.6 -998.22 4637.6 -883.22 4637.6 -768.22 4637.6 -653.22 4637.6 -538.22 4637.6 -423.22 4637.6 -308.22 4637.6 -193.22 4637.6 -78.22 4637.6 36.79 4637.6 151.79 4637.6 266.79 4637.6 381.79 4637.6 496.79 4637.6 621.74 4637.6 744.24 4637.6 859.24 4637.6 974.24 4637.6 1089.24 March 26, 2004 Page 6 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 Pin No. Pin name 26 PRT14[7] 27 PRT14[6] 28 PRT14[5] 29 PRT14[4] 30 PRT14[3] 31 PRT14[2] 32 PRT14[1] 33 PRT14[0] 34 PRT15[7] 35 PRT15[6] 36 PRT15[5] 37 PRT15[4] 38 PRT15[3] 39 PRT15[2] 40 PRT15[1] 41 PRT15[0] 42 PRT17[7] 43 PRT17[6] 44 PRT17[5] 45 PRT17[4] 46 PRT17[3] 47 PRT17[2] 48 PRT17[1] 49 PRT17[0] 50 COM[31] 51 COM[30] 52 COM[29] 53 COM[28] 54 COM[27] 55 COM[26] 56 COM[25] 57 COM[24] 58 COM[23] 59 COM[22] 60 COM[21] 61 COM[20] 62 COM[19] 63 COM[18] 64 COM[17] 65 COM[16] 66 COM[15] 67 COM[14] 68 COM[13] 69 COM[12] 70 COM[11] 71 COM[10] 72 COM[9] 73 COM[8] 74 COM[7] 75 COM[6] 76 COM[5] 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES X Coord. Y-Coord. 4637.6 1204.24 4637.6 1319.24 4637.6 1434.24 4637.6 1549.24 4630.6 1997.5 4477.6 1997.5 4362.6 1997.5 4247.6 1997.5 4132.6 1997.5 4017.6 1997.5 3902.6 1997.5 3787.6 1997.5 3672.6 1997.5 3557.6 1997.5 3442.6 1997.5 3327.6 1997.5 3212.6 1997.5 3097.6 1997.5 2982.6 1997.5 2867.6 1997.5 2752.6 1997.5 2637.6 1997.5 2522.6 1997.5 2407.6 1997.5 2292.6 1997.5 2177.6 1997.5 2062.6 1997.5 1947.6 1997.5 1832.6 1997.5 1717.6 1997.5 1602.6 1997.5 1487.6 1997.5 1372.6 1997.5 1257.6 1997.5 1142.6 1997.5 1027.6 1997.5 912.6 1997.5 797.6 1997.5 682.6 1997.5 567.6 1997.5 452.6 1997.5 337.6 1997.5 222.6 1997.5 107.6 1997.5 -7.4 1997.5 -122.4 1997.5 -237.4 1997.5 -352.4 1997.5 -467.4 1997.5 -602.4 1997.5 -717.4 1997.5 X Coord. Y-Coord. Pin No. -4652.4 -1259.98 135 -4652.4 -1374.98 136 -4652.4 -1489.98 137 -4652.4 -1604.98 138 -4505.17 -1997.5 139 -4390.17 -1997.5 140 -4259.9 -1997.5 141 -4144.9 -1997.5 142 -4029.9 -1997.5 143 -3914.9 -1997.5 144 -3799.9 -1997.5 145 -3684.9 -1997.5 146 -3569.9 -1997.5 147 -3454.9 -1997.5 148 -3339.9 -1997.5 149 -3224.9 -1997.5 150 -3109.9 -1997.5 151 -2994.9 -1997.5 152 -2879.9 -1997.5 153 -2764.9 -1997.5 154 -2649.9 -1997.5 155 -2534.9 -1997.5 156 -2419.9 -1997.5 157 -2304.9 -1997.5 158 -2189.9 -1997.5 159 -2074.9 -1997.5 160 -1959.9 -1997.5 161 -1844.9 -1997.5 162 -1729.9 -1997.5 163 -1614.9 -1997.5 164 -1499.9 -1997.5 165 -1384.9 -1997.5 166 -1269.9 -1997.5 167 -1154.9 -1997.5 168 -1039.9 -1997.5 169 -924.9 -1997.5 170 -809.9 -1997.5 171 -694.9 -1997.5 172 -579.9 -1997.5 173 -444.9 -1997.5 174 -329.9 -1997.5 175 -214.9 -1997.5 176 -99.9 -1997.5 177 15.1 -1997.5 178 130.1 -1997.5 179 245.1 -1997.5 180 360.1 -1997.5 181 475.1 -1997.5 182 590.1 -1997.5 183 705.1 -1997.5 184 820.1 -1997.5 185 Pin name PRTC[3] PRTC[2] PRTC[1] PRTC[0] VDD_RAM CMSG[32] CMSG[33] CMSG[34] CMSG[35] CMSG[36] CMSG[37] CMSG[38] CMSG[39] CMSG[40] CMSG[41] CMSG[42] CMSG[43] CMSG[44] CMSG[45] CMSG[46] CMSG[47] CMSG[48] CMSG[49] CMSG[50] CMSG[51] CMSG[52] CMSG[53] CMSG[54] CMSG[55] CMSG[56] CMSG[57] CMSG[58] CMSG[59] CMSG[60] CMSG[61] CMSG[62] CMSG[63] CMSG[64] CMSG[65] CMSG[66] CMSG[67] CMSG[68] CMSG[69] CMSG[70] CMSG[71] CMSG[72] CMSG[73] CMSG[74] CMSG[75] CMSG[76] CMSG[77] March 26, 2004 Page 7 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 Pin No. 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Pin name COM[4] COM[3] COM[2] COM[1] COM[0] LVL1 LVL2 LVL3 LVL4 LVL5 LCAP4A LCAP4B LCAP3A LCAP3B LCAP2A LCAP2B LCAP1A LCAP1B LCDGS LCDVX LCDVTB LFR LDL GND:G VO DAO OPIN OPIP OPO RSTP_N FXO FXI TSTP_P 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES X Coord. Y-Coord. -832.4 1997.5 -947.4 1997.5 -1062.4 1997.5 -1177.4 1997.5 -1292.4 1997.5 -1407.4 1997.5 -1522.4 1997.5 -1637.4 1997.5 -1752.4 1997.5 -1867.4 1997.5 -1982.4 1997.5 -2097.4 1997.5 -2212.4 1997.5 -2327.4 1997.5 -2442.4 1997.5 -2557.4 1997.5 -2672.4 1997.5 -2787.4 1997.5 -2902.4 1997.5 -3017.4 1997.5 -3132.4 1997.5 -3247.4 1997.5 -3362.4 1997.5 -3477.4 1997.5 -3592.4 1997.5 -3707.4 1997.5 -3822.4 1997.5 -3937.4 1997.5 -4052.4 1997.5 -4167.4 1997.5 -4282.4 1997.5 -4397.4 1997.5 -4512.4 1997.5 X Coord. Y-Coord. Pin No. 935.1 -1997.5 186 1050.1 -1997.5 187 1165.1 -1997.5 188 1280.1 -1997.5 189 1395.1 -1997.5 190 1510.1 -1997.5 191 1625.1 -1997.5 192 1740.1 -1997.5 193 1855.1 -1997.5 194 1970.1 -1997.5 195 2085.1 -1997.5 196 2200.1 -1997.5 197 2315.1 -1997.5 198 2430.1 -1997.5 199 2545.1 -1997.5 200 2660.1 -1997.5 201 2775.1 -1997.5 202 2890.1 -1997.5 203 3005.1 -1997.5 204 3120.1 -1997.5 205 3235.1 -1997.5 206 3352.34 -1997.5 207 3467.34 -1997.5 208 3585.1 -1997.5 209 3700.1 -1997.5 210 3815.1 -1997.5 211 3930.1 -1997.5 212 4045.1 -1997.5 213 4160.1 -1997.5 214 4275.1 -1997.5 215 4390.1 -1997.5 216 4505.1 -1997.5 217 4620.1 -1997.5 218 Pin name CMSG[78] CMSG[79] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] 6. LCD RAM Map There are 4 LCD configurations as determined by mask option MO_COM[1..0]. The functions of CMSG[79..32] are different in each configuration as listed in the following table. MO_COM[1..0] Configuration CMSG[79..64] CMSG[63..48] CMSG[47..32] 00 32 x 128 SEG[80..95] SEG[96..111] SEG[112..127] 01 48 x 112 SEG[80..95] SEG[96..111] COM[47..32] 10 64 x 96 SEG[80..95] COM[63..48] COM[47..32] 11 80 x 80 COM[79..64] COM[63..48] COM[47..32] March 26, 2004 Page 8 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 COMXSEG C MSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 CMSG64 CMSG65 CMSG66 CMSG67 CMSG68 CMSG69 CMSG70 CMSG71 CMSG72 CMSG73 CMSG74 CMSG75 CMSG76 CMSG77 CMSG78 CMSG79 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 32X128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 48X112 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 64X96 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 80X80 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 The RAM Maps of all four different LCD configurations are as the following: 32 COM: Page 7 COM0 COM1 : COM15 COM16 : COM30 COM31 Page 6 COM0 COM1 : COM15 COM16 SEG [7:0] 7E0H 7E1H : 7EFH 7F0H : 7FEH 7FFH SEG [71:64] 6E0H 6E1H : 6EFH 6F0H SEG [15:8] 7C0H 7C1H : 7CFH 7D0H : 7DEH 7DFH SEG [79:72] 6C0H 6C1H : 6CFH 6D0H SEG [23:16] 7A0H 7A1H : 7AFH 7B0H : 7BEH 7BFH SEG [87:80] 6A0H 6A1H : 6AFH 6B0H SEG [31:24] 780H 781H : 78FH 790H : 79EH 79FH SEG [95:88] 680H 681H : 68FH 690H Page 9 of 29 SEG SEG SEG SEG [39:32] [47:40] [55:48] [63:56] 760H 740H 720H 700H 761H 741H 721H 701H : : : : 76FH 74FH 72FH 70FH 770H 750H 730H 710H : : : : 77EH 75EH 73EH 71EH 77FH 75FH 73FH 71FH SEG SEG SEG SEG [103:96] [111:104] [119:112] [127:120] 660H 640H 620H 600H 661H 641H 621H 601H : : : : 66FH 64FH 62FH 60FH 670H 650H 630H 610H V1.03 March 26, 2004 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 : COM30 COM31 48 COM: Page 7,6 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM46 COM47 Page 6, 5, 4 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM46 COM47 64 COM: Page 7,6 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM47 COM48 : COM62 COM63 March 26, 2004 : 6FEH 6FFH SEG[7:0] 7C0H 7C1H : 7CFH 7D0H : 7DFH 7E0H : 7EEH 7EFH SEG [63:56] 600H 601H : 60FH 610H : 61FH 620H : 62EH 62FH SEG[7:0] 7C0H 7C1H : 7CFH 7D0H : 7DFH 7E0H : 7EFH 7F0H : 7FEH 7FFH : 6DEH 6DFH 億 電 子 股 份 有 限 公 司 : 65EH 65FH : 6BEH 6BFH : 69EH 69FH : 67EH 67FH HE847701 HE80000 SERIES : 63EH 63FH : 61EH 61FH SEG[15:8] SEG[23:16] SEG[31:24] SEG[39:32] SEG[47:40] SEG[55:48] 780H 740H 700H 6C0H 680H 640H 781H 741H 701H 6C1H 681H 641h : : : : : : 78FH 74FH 70FH 6CFH 68FH 64FH 790H 750H 710H 6D0H 690H 650H : : : : : : 79FH 75FH 71FH 6DFH 69FH 65FH 7A0H 760H 720H 6E0H 6A0H 660H : : : : : : 7AEH 76EH 72EH 6EEH 6AEH 66EH 7AFH 76FH 72FH 6EFH 6AFH 66FH SEG [71:64] 5C0H 5C1H : 5CFH 5D0H : 5DFH 5E0H : 5EEH 5EFH SEG [79:72] 580H 581H : 58FH 590H : 59FH 5A0H : 5AEH 5AFH SEG [87:80] 540H 541h : 54FH 550H : 55FH 560H : 56EH 56FH SEG [95:88] 500H 501H : 50FH 510H : 51FH 520H : 52EH 52FH SEG [103:96] 4C0H 4C1H : 4CFH 4D0H : 4DFH 4E0H : 4EEH 4EFH SEG[39:32] 6C0H 6C1H : 6CFH 6D0H : 6DFH 6E0H : 6EFH 6F0H : 6FEH 6FFH SEG [111:104] 480H 481H : 48FH 490H : 49FH 4A0H : 4AEH 4AFH SEG[47:40] 680H 681H : 68FH 690H : 69FH 6A0H : 6AFH 6B0H : 6BEH 6BFH V1.03 SEG[15:8] 780H 781H : 78FH 790H : 79FH 7A0H : 7AFH 7B0H : 7BEH 7BFH SEG[23:16] 740H 741H : 74FH 750H : 75FH 760H : 76FH 770H : 77EH 77FH Page 10 of 29 SEG[31:24] 700H 701H : 70FH 710H : 71FH 720H : 72FH 730H : 73EH 73FH This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 Page 6, 5 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM47 COM48 : COM62 COM63 80 COM: Page 7:3 COM0 COM1 : COM15 COM16 : COM31 COM32 : COM47 COM48 : COM62 COM63 : COM78 COM79 SEG[55:48] 640H 641H : 64FH 650H : 65FH 660H : 66FH 670H : 67EH 67FH SEG [15:8] 700H 701H : 70FH 710H : 71FH 720H : 72FH 730H : 73FH 740H : 74EH 74FH 億 電 子 股 份 有 限 公 司 SEG[63:56] 600H 601H : 60FH 610H : 61FH 620H : 62FH 630H : 63EH 63FH SEG[71:64] 5C0H 5C1H : 5CFH 5D0H : 5DFH 5E0H : 5EFH 5F0H : 5FEH 5FFH SEG[79:72] 580H 581H : 58FH 590H : 59FH 5A0H : 5AFH 5B0H : 5BEH 5BFH HE847701 HE80000 SERIES SEG[87:80] 540H 541H : 54FH 550H : 55FH 560H : 56FH 570H : 57EH 57FH SEG[95:88] 500H 501H : 50FH 510H : 51FH 520H : 52FH 530H : 53EH 53FH SEG [7:0] 780H 781H : 78FH 790H : 79FH 7A0H : 7AFH 7B0H : 7BFH 7C0H : 7CEH 7CFH SEG SEG SEG SEG SEG SEG SEG SEG [23:16] [31:24] [39:32] [47:40] [55:48] [63:56] [71:64] [79:72] 680H 600H 580H 500H 480H 400H 380H 300H 681H 601H 581H 501H 481H 401H 381H 301H : : : : : : : : 68FH 60FH 58FH 50FH 48FH 40FH 38FH 30FH 690H 610H 590H 510H 490H 410H 390H 310H : : : : : : : : 69FH 61FH 59FH 51FH 49FH 41FH 39FH 31FH 6A0H 620H 5A0H 520H 4A0H 420H 3A0H 320H : : : : : : : : 6AFH 62FH 5AFH 52FH 4AFH 42FH 3AFH 32FH 6B0H 630H 5B0H 530H 4B0H 430H 3B0H 330H : : : : : : : : 6BFH 63FH 5BFH 53FH 4BFH 43FH 3BFH 33FH 6C0H 640H 5C0H 540H 4C0H 440H 3C0H 340H : : : : : : : : 6CEH 64EH 5CEH 54EH 4CEH 44EH 3CEH 34EH 6CFH 64FH 5CFH 54FH 4CFH 44FH 3CFH 34FH 7. LCD Power Supply The built-in LCD power supply is equipped with input voltage regulator, voltage charge pump and bias voltage generating circuit with active buffer instead of passive resistor voltage dividing network. The input voltage is regulated to LVL2 using the internally generated reference voltage. LVL2 can be adjusted by resistor between LCDGS and LVL2. LVL2 adjustment guideline: First, the level of VDD must be 0.3 volt higher than LVL2 even at the end of battery life for the regulator to function properly. For example, if the VDD is expected to drop to 2.2 volts when battery is low, then the level of LVL2 can only be set at 1.9 volts max. March 26, 2004 Page 11 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES Voltage charge pump: The LVL2 is then pumped to LVL5 based on the bias setting of MO_LBSR[3..0]. The formula for LVL5 is: LVL5 = LVL2 / 2 x (1/Bias) The potential difference between bias voltages LVL1 ~ LVL5 is determined by the bias settings, too. Voltage Difference Ratio LVL5 1 1 3 ~ 6.5 1 1 LVL4 LVL3 LVL2 LVL1 For example, if the bias setting is 1/7 bias and LVL2 is 2 volts, the LVL5 will be pumped to 7 volts when the load is light. Bias Min. VDD LVL2 2.70 2.40 2.60 2.30 2.50 2.20 2.40 2.10 2.30 2.00 2.20 1.90 2.10 1.80 2.00 1.70 5.0 6.00 5.75 5.50 5.25 5.00 4.75 4.50 4.25 5.5 6.60 6.33 6.05 5.78 5.50 5.23 4.95 4.68 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 LVL5 = LCD Panel Operating Voltage 7.20 7.80 8.40 6.90 7.48 8.05 6.60 7.15 7.70 8.25 6.30 6.83 7.35 7.88 8.40 6.00 6.50 7.00 7.50 8.00 8.50 5.70 6.18 6.65 7.13 7.60 8.08 8.55 5.40 5.85 6.30 6.75 7.20 7.65 8.10 8.55 5.10 5.53 5.95 6.38 6.80 7.23 7.65 8.08 8.5 6.0 Please note that external connections of charge pump capacitors must be made according to the bias setting, too. Please use the following figure as reference when designing application circuit and LVL5 must be lower than 8.5 volts to prevent chip from breaking down. March 26, 2004 Page 12 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 For bias: 5, 5.5, 6 4.7uF 4.7uF 1uF 1uF 4.7uF LVL1 LVL2 LVL3 LVL4 LVL5 LCAP4A 1uF LCAP4B LCAP3A 1uF LCAP3B LCAP2A LCAP2B LCAP1A LCAP1B LCDGS 1uF R LCDVX LCAPVTB 1uF R 1uF 1uF 1uF 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES LVL1 LVL2 LVL3 LVL4 LVL5 LCAP4A 1uF LCAP4B LCAP3A 1uF LCAP3B LCAP2A 1uF LCAP2B LCAP1A 1uF LCAP1B LCDGS For bias: 6.5, 7, 7.5, 8 4.7uF 4.7uF 1uF 1uF 4.7uF LVL1 LVL2 LVL3 LVL4 LVL5 LCAP4A LCAP4B LCAP3A LCAP3B LCAP2A LCAP2B LCAP1A LCAP1B LCDGS LCDVX LCAPVTB For bias: 8.5, 9, 9.5, 10 4.7uF 4.7uF 1uF 1uF 4.7uF 1uF R LCDVX LCAPVTB Different duties require different bias settings. There is some theoretical correspondence between the Duty and Bias Setting. However, it is better to use it as starting point and adjust it with real LCD panel connected to it to determine the final setting. The theoretic relationship between the duty and bias setting as following: Duty Cycle Normal Bias Alternative Bias 32 duty 1/7 1/7.5 48 duty 1/8 1/7.5, 1/8.5 64 duty 1/9 1/8.5, 1/9.5 80 duty 1/10 1/9.5, 1/10.5 The bias setting is made by mask option MO_LBSR[3..0]. MO_LBSR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bias Setting undefined 1/5 1/5.5 1/6 1/6.5 1/7 1/7.5 1/8 1/8.5 1/9 1/9.5 1/10 1/10.5 1/11 1/11.5 1/12 March 26, 2004 Page 13 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 7.1. LCDC Control register The gray scale of the LCD driver can be adjusted by GRAY field of LCD. The LCD panel can be blanked by setting the BLANK field of LCDC register. LCD driver can be totally turned off by clearing LCDE bit of LCDC. LCDC Field Reset Field GRAY bit 7 bit 6 bit 5 bit 4 bit 3 GRAY bit 2 bit 1 BLANK 1 bit 0 LCDE 0 Value 000 111 BLANK 0 1 LCDE 0 1 Function LCD is darkest. LCD is lightest. normal display LCD display blanked. The COM signals of LCD driver output inactive levels (LVL4 and LVL1) while SEG signals output normal display patterns. LCD driver disabled, LCD driver has no output signal. LCD driver Enabled Please note that LCD driver must be turned off before the MCU goes into sleep mode. In other words, user must clear the bit 0 (LCDE bit) of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep mode. Large current might happen if the procedure is not followed. Please note that LCD driver uses slow clock as clock source. The LCD display would not display normally if it worked in Fast clock only mode as the LCD refresh action would be too fast. 8. Oscillators The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to choose from. So that system designer can select oscillator types based on the cost target, timing accuracy requirements etc. Crystal, Resonator or the RC oscillator can be used as fast clock source, components should be placed as close to the pins as possible. The type of oscillator used is selected by mask option MO_FXTAL. MO_FXTAL Fast clock type 0 RC Oscillator. 1 Crystal Oscillator. F XI FXI 22p R 3579545Hz 22p FXO Crystal Osc. RC Osc. March 26, 2004 Page 14 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES The RC oscillator has a built-in capacitor. An external resistor is needed to connect from FXI to GND to determine the oscillation frequency. The capacitance of internal RC oscillator is selected by mask option MO_RCAP[2..0]. MO_RCAP[2..0] Internal RC Cap. OSC. (pF) 000 2 001 4 010 7 011 14 100 20 101 40 110 50 111 60 The following table shows the combinations of R and C, and the resulting frequency. Please note that oscillation frequency in the table only represents oscillation frequencies of certain samples. The actual oscillation frequency may vary up to ±15% from lot to lot due to process parameter variations. User must take this into consideration when using this chip in applications. Ring Oscillator Frequency Table R(K ohm )\C (pF) 30.20 19.92 9.98 40 0.8 1.2 2.3 20 1.5 2.2 4.0 14 2.0 2.8 5.1 7 3.0 4.4 7.5 4 4.0 5.6 9.4 2 5.0 MHz 7.0 MHz 11.4 MHz Two types of oscillator, crystal and RC, can be used as slow clock by mask option MO_SXTAL. If used for time keeping function or other applications that required the accurate timing, crystal oscillator is recommended. If the timing accuracy is not important, then RC type oscillator can be used to reduce cost. MO_SXTAL 0 1 Slow clock type R/C oscillator Crystal oscillator SXI SXI SXO Crystal Osc. SXO RC Osc. With two clock sources available, the system can switch among operation modes of Fast, Slow, Idle, and Sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of application such as power saving, etc. March 26, 2004 Page 15 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 OP1 Field Mode Reset OP2 Field Mode Reset Bit 7 DRDY R/W 1 Bit 7 IDLE R/W 0 億 電 子 股 份 有 限 公 司 Bit 1 Z R/W Bit 6 STOP R/W 0 Bit 6 PNWK R Bit 5 SLOW R/W 0 Bit 5 TCWK R Bit 4 INTE R/W 0 Bit 4 TBE R/W 0 Bit 3 T2E R/W 0 Bit 3 W Bit 2 T1E R/W 0 HE847701 HE80000 SERIES Bit 0 C R/W Bit 0 W - Bit 2 Bit 1 TBS[3..0] W W - If the dual clock mode is used, the LCD display, Timer1 and Timer Base will derive its clock source from slow clock while the other blocks will operate with the fast clock. 9. General Purpose I/O There are three dedicated general purpose I/O port, PRTC, PRTD and PRT10, while PRT14, PRT15 and PRT17 are multiplexed with LCD segment driver pins. All the I/O Ports are bi-directional and of nontri-state output structure. The output has weak sourcing (50 µA) and stronger sinking (1 mA) capability and each can be configured as push-pull or open-drain output structure individually by mask option. When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a floating pad could cause more power consumption since the noise could interfere with the circuit and cause the input to toggle. A ‘1’ needs to be written to port first before reading the input data from the I/O pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path between pull-up and external circuit. The input port has built-in Schmidt trigger to prevent it from chattering. Hysteresis level of Schmidt trigger is 1/3*VDD. VDD VDD DOUT Q LATCH Q' MO_?PP PAD DIN SCHMIDT Trigger input March 26, 2004 Page 16 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES As pads of PRT14, PRT15 and PRT17 are shared with LCD segment driver, the function of the pads is determined by mask options. LIO17=0 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 LIO15=0 PRT150 PRT151 PRT152 PRT153 PRT154 PRT155 PRT156 PRT157 PRT150 PRT151 PRT152 PRT153 PRT154 PRT155 PRT156 PRT157 LIO14=0 PRT140 PRT141 PRT142 PRT143 PRT144 PRT145 PRT146 PRT147 PRT140 PRT141 PRT142 PRT143 PRT144 PRT145 PRT146 PRT147 LIO17=1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 LIO15=1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 LIO14=1 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to LCD display setting and pin assignment features. MO_LIO?[…] MO_?PP[...] I/O Port LCD Pin 0 0 Open-drain output -0 1 Push-pull output -1 0 -xx 1 1 -LCD Display --: Function not available. xx: Displayable, but may have abnormal leakage current, do not use. 10. Key Scan Circuit The built-in 4x20 hardware keyboard scan circuit helps to reduce the pin counts where application requires large key matrix and high LCD pixel count as well as the firmware effort. As key-scan pins are shared with LCD segment and PRTC4 ~ PRTC7 pins, it is advisable to put resistors between segment pins and key matrix to avoid shorting the segment pins when two or more keys in the same row are pressed simultaneously. Two key can be detected simultaneously and the first detected key code is stored in KEY0 register and the second in KEY1 register respectively. The key code for each key location is listed in the following table. Key Loc SCNI0 SCNI1 SCNI2 SCNI3 SCNO0 0x80 0xA0 0xC0 0xE0 SCNO1 0x81 0xA1 0xC1 0xE1 March 26, 2004 Page 17 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 股 份 有 限 公 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 司 SCNO2 SCNO3 SCNO4 SCNO5 SCNO6 SCNO7 SCNO8 SCNO9 SCNO10 SCNO11 SCNO12 SCNO13 SCNO14 SCNO15 SCNO16 SCNO17 SCNO18 SCNO19 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 HE847701 HE80000 SERIES KEY0 0x22 KEY1 0x23 BIT7 R BIT7 R BIT6 BIT5 Row Index BIT6 BIT5 Row Index BIT4 BIT3 BIT2 BIT1 Column Index BIT2 BIT1 Column Index BIT0 BIT4 BIT3 BIT0 The bit 7 of KEY0 and KEY1 is repeat indicator when the same key is scanned for the second time, the R bit will be cleared to indicate the key is not released yet. The key-scan function can be turned on/off by mask option MO_LCDKEY. MO_LCDKEY 0 1 SGKY[43..24] Function as SEG only as SEG as well as KEY_SCAN The pulse width of key-scan signal can be selected by mask options MO_SNCK[1..0]. MO_SNCK[1..0] 00 01 10 11 Key Scan Pulse Width 0.5 sck 1 sck 1.5 sck 2 sck The strength of key-scan signal can also be selected by mask options MO_SNCK[1..0]. MO_SCDRV[1..0] 00 01 10 March 26, 2004 Key Scan Signal Strength weakest Page 18 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 11 億 電 子 股 份 有 限 公 司 strongest HE847701 HE80000 SERIES SCNO0 SCNO1 SCNO2 SCNO3 SCNO17 SCNO18 SCNO19 SCNI0 SCNI1 SCNI2 SCNI3 SGKY 24 SGKY 25 SGKY 26 SGKY 27 : SGKY 41 SGKY 42 SGKY 43 47K PRTC4 PRTC5 PRTC6 PRTC7 47K 47K 47K .... 47K 47K 47K 11. Timer1 The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt will be generated when the counter underflows - counts down to FFFFH. And the counter will be automatically reloaded with the value of T1H and T1L. The clock source of Timer1 is derived from slow clock “SCK” at dual clock or slow clock only mode. And it comes from the fast clock “FCK” at fast clock only mode. Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be set before enabling Timer1. March 26, 2004 Page 19 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES The contents of T1H and T1L almost loaded into Timer1 immediately when Timer1 is turned on after reset. T1H T1L Auto reload when Timer1 underflow "Timer1 Counter" decreases 1 No Count TO 0xFFFFh Start Timer1 Interrupt Request. Yes T1_INT The Timer1 related control registers are list as below: Register Address Field Bit position Mode Description 0x02 TC1_IER 2 R/W 0: TC1 interrupt is disabled. (default) IER 1: TC1 interrupt is enabled. 0x03 T1L[7:0] 7~0 W Low byte of TC1 pre-load value T1L 0x04 T1H[7:0] 7~0 W High byte of TC1 pre-load value T1H 0x09 TC1E 2 R/W 0: TC1 is disabled. (default) OP1 1: TC1 is enabled. 12. Timer2 Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock “Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU. The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded March 26, 2004 Page 20 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 with the value of T2H and T2L. 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value should be set before enabling Timer2. The contents of T2H and T2L almost loaded into Timer2 immediately when Timer2 is turned on after reset. T2H T2L Auto reload when Timer2 underflow "Timer2 Counter" decreases 1 No Count TO 0xFFFFh Yes Start Timer2 Interrupt Request. T2_INT The Timer2 related control registers are list as below: Register Address Field Bit position Mode Description 0x02 TC2_IER 1 R/W 0: TC2 interrupt is disabled. (default) IER 1: TC2 interrupt is enabled. 0x05 T2L[7:0] 7~0 W Low byte of TC2 pre-load value T2L 0x06 T2H[7:0] 7~0 W High byte of TC2 pre-load value T2H 0x09 TC2E 3 R/W 0: TC2 is disabled. (default) OP1 1: TC2 is enabled. March 26, 2004 Page 21 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 13. Time Base Interrupt The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is determined by dividing slow clock with a factor selected in OP2[3..0]. TBE (Time Base Enable) bit controls enable or disable of the circuit. OP2 Field Mode Reset Bit 7 IDLE R/W 0 Bit 6 PNWK R Bit 5 TCWK R Bit 4 TBE R/W 0 Bit 3 W Bit 2 Bit 1 TBS[3..0] W W Bit 0 W - TBE Function 0 Disable Time Base 1 Enable Time Base For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table. TBS[3..0] Interrupt Frequency 0000 16.384 KHz 0001 8.192 KHz 0010 4.096 KHz 0011 2.048 KHz 0100 1.024 KHz 0101 512 Hz 0110 256 Hz 0111 128 Hz 1000 64 Hz 1001 32 Hz 1010 16 Hz 1011 8 Hz 1100 4 Hz 1101 2 Hz 1110 1 Hz 1111 0.5 Hz 14. Watch Dog Timer Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by abnormal hardware activities or program execution. WDT needs to be enabled in Mask Option. MO_WDTE Function 0 WDT disable 1 WDT enable To use WDT function, “CLRWDT” instruction needs to be executed in every possible program path when the program runs normally in order to clears the WDT counter before it overflows, so that the March 26, 2004 Page 22 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES program can operate normally. When abnormal conditions happen to cause the MCU to divert from normal path, the WDT counter will not be cleared and reset signal will be generated. WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1 clock has stopped.) 15. Digital-to-Analog Converter The Digital-to-Analog converter (DAC) converts the 7-bit unsigned speech data written to PWMC to proportional current output. PWMC register DA & PWM Data Control Bit 7 0 1 Bit 6 Bit 4 Bit 3 Bit 2 DA and PWM output value PWM O/P driver Bit 5 Bit 1 Bit 0 PWME There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by VOC register when it is enabled. The VO output is primarily intended for speech generation, although it is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to function as an Analog-to-Digital Converter as required in applications such as speech recording, speech recognition or sensor interfaces. OPO OP + 1 PWMC[DATA] DAC 0 OPIP OPIN DAO VO R VOC[DAC] VOC[OP] The DAC is enabled by DAC bit of VOC register. Please note that the DAC bit of VOC register will be automatically cleared when the system enter Idle or Sleep mode. So it needs to be set again when returning to Normal mode. VOC VOC register Initial Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 0 PWM Bit 1 0 DAC Bit 0 0 OP Bit Name Value 1 DAC 1 March 26, 2004 Function description DA Enable V1.03 Page 23 of 29 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 0 子 股 份 有 限 公 司 DA Disable HE847701 HE80000 SERIES The output current of the DAC is programmable by mask option MO_DACISEL: MO_DACISEL[1:0] DAC output current 00 0.375 mA 01 0.75 mA 10 1.5 mA 11 3 mA 16. Pulse-Width Modulation The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to proportional duty cycle of PWM output. PWM module shares the PWMC data register with Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is enabled, it generates signal with duty ratio in proportion to the DA value. DA = 0x20 DA = 0x80 DA = 0xE0 1 subframe The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of VOC is ‘0’, PWME bit and output drivers settings are both cleared. To use PWM for voice output, PWM bit has to be set to ‘1’ first, then set PWME bit and enable output driver by setting the driver number. If PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear. The Fast Clock is gated through PWME bit of PWMC command register to provide the clock source of PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct PWM signal in Slow clock only mode. When the program enters into Sleep mode or Idle mode, it will automatically turn off all voice outputs by clearing VOC[2..1] to ”00”. To activate voice output again when returning to Normal Mode, the VOC register needs to be set again. The PWM output volume can be adjusted by command register PWMC[6..4]. The bit 6 and 5 control 2 time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the internal drivers, the sound level of PWM output can be turned up and down. Please note that this adjustment apply only to PWM, but not DA output. March 26, 2004 Page 24 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 PWM output driver selection PWMC[6..4] Number of Driver 000 off 001 1 010 2 011 3 100 2 101 3 110 4 111 5 HE847701 HE80000 SERIES 17. Absolute Maximum Rating Item Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Sym. Rating Vdd -0.5V ~ 4.0V Vin -0.5V ~ Vdd+0.5V Vo -0.5V ~ Vdd+0.5V Top 00C ~ 700C Tst -500C ~ 1000C Condition 18. Recommended Operating Conditions Item Supply Voltage Input Voltage Operating Frequency Operating Temperature Storage Temperature Rating 2.4V ~ 3.6V 0.9 Vdd ~ Vdd 0.0V ~ 0.1Vdd 8MHz Fmax 6MHz 0 Top 0 C ~ 700C Tst -500C ~ 1000C Sym. Vdd Vih Vil Condition Vdd =3.0V Vdd =2.4V 19. Parameters AC/DC Characteristics Symbol Min. Typ. Max. Unit Condition Testing Condition : TEMP=25℃, VDD=3V±10% Power consumption Normal mode current Slow mode Current Idle mode Current Sleep mode Current Additional Current if LCD ON I/O specification Input High Voltage Input Low Voltage Input Hysteresis Width IFAST ISLOW IIDLE ISLEEP ILCD VIH VIL VHYS 0.8 1 15 10 1.5 25 20 1 mA µA µA µA µA VDD VDD VDD 2M external R/C fast clock 32768 Hz slow clock with LCD disabled 32768 Hz slow clock with LCD disabled 150 220 1/7 bias, no load on SEG and COM pins Input Pins Input Pins I/O, RSTP_N Threshold = 2/3xVDD 0.2 1/3 March 26, 2004 Page 25 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES Output Source Current Output Sink Current Input Low Current Input Low Current PWM and DAC PWM Output Current DAC Output Current Notes: 1. 2. IOH IOL1 IIL1 IIL2 50 1.0 20 100 10 6 4 2.5 14 8 5 3 µA mA µA µA mA mA mA mA (Input from low to high), Threshold = 1/3xVDD (Input from high to low) Output drive high*1, VOL=2.0V Output drive low, VOL=0.4V RSTP_N, VIL = GND, Pull high Internally I/O, VIL=GND, if pull high Internally by user PWM *2 With 32Ω Loading With 64Ω Loading With 100Ω Loading VO, DAO@ VDD=3V,VO=0~2V, Data = 7F IPWM IoVO The “Output Source Current” specification is applicable only to the Push-Pull I/O type. This specification indicates only one PWM driving capability, and there are totally five built-in drivers, user can multiply the actual number of driver to get the actual current. (IPWM x N; where N = 0, 1, 2, 3, 4, 5) March 26, 2004 Page 26 of 29 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 20. Application Circuit BUZZER VDD 1 3.0V + 47uF 0.1uF PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 PRT100 PRT101 PRT102 PRT103 PRT104 PRT105 PRT106 PRT107 PRTC0 PRTC1 PRTC2 PRTC3 PRTC4 PRTC5 PRTC6 PRTC7 PWM Y1 SXI SXO 33p SXI 33p SXO FXI 32768Hz 22p 4MHz Y2 22p FXO 47K 2 VDD R 0.1uF 47K 47K VDD 0.1uF 139 140 VDD_RAM 141 CMSG32 142 CMSG33 143 CMSG34 144 CMSG35 145 CMSG36 146 CMSG37 147 CMSG38 148 CMSG39 149 CMSG40 150 CMSG41 151 CMSG42 152 CMSG43 153 CMSG44 154 CMSG45 155 CMSG46 156 CMSG47 157 CMSG48 158 CMSG49 159 CMSG50 160 CMSG51 161 CMSG52 162 CMSG53 163 CMSG54 164 CMSG55 165 CMSG56 166 CMSG57 167 CMSG58 168 CMSG59 169 CMSG60 170 CMSG61 171 CMSG62 172 CMSG63 173 CMSG64 174 CMSG65 175 CMSG66 176 CMSG67 177 CMSG68 178 CMSG69 179 CMSG70 180 CMSG71 181 CMSG72 182 CMSG73 183 CMSG74 184 CMSG75 185 CMSG76 186 CMSG77 187 CMSG78 188 CMSG79 189 SEG79 190 SEG78 191 SEG77 192 SEG76 193 SEG75 194 SEG74 195 SEG73 196 SEG72 197 SEG71 198 SEG70 199 SEG69 200 SEG68 201 SEG67 202 SEG66 203 SEG65 204 SEG64 205 SEG63 206 SEG62 207 SEG61 208 SEG60 209 SEG59 210 SEG58 211 SEG57 212 SEG56 213 SEG55 214 SEG54 215 SEG53 216 SEG52 217 SEG51 218 SEG50 SEG49 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 SEG48 SEG47 SEG46 SEG45 SEG44 SGKY43 SGKY42 SGKY41 SGKY40 SGKY39 SGKY38 SGKY37 SGKY36 SGKY35 SGKY34 SGKY33 SGKY32 SGKY31 SGKY30 SGKY29 SGKY28 SGKY27 SGKY26 SGKY25 SGKY24 PRT147 PRT146 PRT145 PRT144 STBN DCN RWN REN LDL LFR LVL2 LVL3 LVL5 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 March 26, 2004 Page 27 of 29 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 1 2 3 4 5 6 7 8 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 V1.03 This specification is subject to change without notice. Please contact sales person for the latest version before use. This application assumes 80 COMX80 SEG configuration, and 80 SEG Extender KDS80. CMSG32 CMSG33 CMSG34 CMSG35 CMSG36 CMSG37 CMSG38 CMSG39 CMSG40 CMSG41 CMSG42 CMSG43 CMSG44 CMSG45 CMSG46 CMSG47 CMSG48 CMSG49 CMSG50 CMSG51 CMSG52 CMSG53 CMSG54 CMSG55 CMSG56 CMSG57 CMSG58 CMSG59 CMSG60 CMSG61 CMSG62 CMSG63 CMSG64 CMSG65 CMSG66 CMSG67 CMSG68 CMSG69 CMSG70 CMSG71 CMSG72 CMSG73 CMSG74 CMSG75 CMSG76 CMSG77 CMSG78 CMSG79 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 TSTP FXI FXO RSTP_N OPO OPIP OPIN DAO VO GND LDL LFR LCDVTB LCDVX LCDGS LCAP1B LCAP1A LCAP2B LCAP2A LCAP3B LCAP3A LCAP4B LCAP4A LVL5 LVL4 LVL3 LVL2 LVL1 COM0 COM1 COM2 C0M3 C0M4 C0M5 C0M6 C0M7 C0M8 C0M9 C0M10 C0M11 C0M12 C0M13 C0M14 C0M15 C0M16 C0M17 C0M18 C0M19 C0M20 C0M21 C0M22 C0M23 C0M24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 PRT170 PRT171 PRT172 PRT173 PRT174 PRT175 PRT176 PRT177 PRT150 PRT151 PRT152 PRT153 PRT154 PRT155 PRT156 PRT157 PRT140 PRT141 PRT142 PRT143 HE847701 109 FXI 108 FXO 107 RST 106 0 OPO 105 OPIP 104 OPIN 103 DAO 102 VO 101 100 LDL 99 LFR 98 LCDVTB 97 LCDVX 96 LCDGS 95 LCAP1B 94 LCAP1A 93 LCAP2B 92 LCAP2A 91 LCAP3B 90 LCAP3A 89 LCAP4B 88 LCAP4A 87 LVL5 86 LVL4 85 LVL3 84 LVL2 83 LVL1 82 COM0 81 COM1 80 COM2 79 COM3 78 COM4 77 COM5 76 COM6 75 COM7 74 COM8 73 COM9 72 COM10 71 COM11 70 COM12 69 COM13 68 COM14 67 COM15 66 COM16 65 COM17 64 COM18 63 COM19 62 COM20 61 COM21 60 COM22 59 COM23 58 COM24 57 COM25 56 COM26 55 COM27 54 COM28 53 COM29 52 COM30 51 COM31 50 PRT170 49 PRT171 48 PRT172 47 PRT173 46 PRT174 45 PRT175 44 PRT176 43 PRT177 42 PRT150 41 PRT151 40 PRT152 39 PRT153 38 PRT154 37 PRT155 36 PRT156 35 PRT157 34 PRT140 33 PRT141 32 PRT142 31 PRT143 30 PRTC0 PRTC1 PRTC2 PRTC3 PRTC4 PRTC5 PRTC6 PRTC7 PWM GND_PWM PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 PRT100 PRT101 PRT102 PRT103 PRT104 PRT105 PRT106 PRT107 VDD SXI SXO 47K .... 47K 300K 1uF 1uF 1uF 1uF 4.7uF PRTC4 PRTC5 PRTC6 SCNI2 PRTC7 SCNI3 1uF 1uF 4.7uF SCNI0 SCNI1 4.7uF SCNO17 SCNO18 SCNO19 SCNO0 SCNO1 SCNO2 SCNO3 SGKY24 SGKY25 SGKY26 SGKY27 : SGKY41 SGKY42 SGKY43 58 57 56 55 54 53 52 51 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 47K 47K KDS80 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG141 SEG140 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 VDD RES_N RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 GND STBN D_CN R_WN REN LDL LFR LVL2 LVL3 LVL5 LVP SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 RES RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 VDD SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 PRT147 PRT146 PRT145 PRT144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 King Billion Electronics Co., Ltd 駿 億 電 子 股 份 有 限 公 司 HE847701 HE80000 SERIES 21. Important Note 1. For accessing any address large than 64KB, users must update TPP first, TPH then TPL. Only by this order, the pre-charge circuit of ROM will work correctly. 5us waiting is necessary before LDV instruction is executed since Data ROM is a low speed ROM. Users can not emulate accessing delay with ICE. So 5us delay should be added by firmware. LCD driving circuit must be turned off before MCU goes into sleep mode. Please bond the TSTP_P, RSTP_N and PRTD[7:0] with test points on PCB, which can be soldered and probed. Connect TSTP_P pin with zero ohm resistor to GND (or copper wire which can be cut easily on PCB) for good ESD protection. So that IC testing can be done on PCB, if necessary, by removing the 0-ohm resistor and driving TSTP_P pin to high. LV5 must small than 8.5 Volt. Otherwise IC may breakdown. Users must call the library “swap_page” in the file swappage.asm of AN029. The real IC register is different from ICE4.x or ICE5.x. This subroutine make sure that users can run on both real IC and ICE for page swapping. The program of swappage.asm as following: .area swapping_variable(data) _mapreg1:: .ds 1 ;store page register(R1Bh) _mapreg2:: .ds 1 ;store page register(R1Ch) .area swapping_page(code,pag0) ;====================================================== ;swap page function ;====================================================== 2. 3. 4. 5. swap_page:: lda #10h sta _mapreg1 lda #00h ; P1E_O[2]