KK74HC4052A

TECHNICAL DATA KK74HC4052A Analog Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS The KK74HC4052A utilise silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is high, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LS/ALS TTL outputs. • Fast Switching and Propagation Speeds • Low Crosstalk Between Switches • Diode Protection on All Inputs/Outputs • Analog Power Supply Range (VCC-VEE) = 2.0 to 12.0 V • Digital (Control) Power Supply Range (VCC-GND) = 2.0 to 6.0 V • Low Noise 16 1 16 1 D SUFFIX S O IC ORDERING INFORMATION KK74HC4052AN Plastic DIP KK74HC4052AD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Double-Pole, 4-Position Plus Common Off FUNCTION TABLE Control Inputs Enable B L L L PIN 16 =VCC PIN 7 = VEE PIN 8 = GND L L L H H Select A L H L H X Y0 Y1 Y2 Y3 X0 X1 X2 X3 None ON Channels H X H = high level L = low level X = don’t care 1 KK74HC4052A MAXIMUM RATINGS* Symbol VCC VEE VIS VIN I PD Tstg TL * Parameter Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) DC Input Current Into or Out of Any Pin Power Dissipation in Still Air, Plastic DIP+ SO Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SO Package) Value -0.5 to +7.0 -0.5 to +14.0 -7.0 to +0.5 VEE - 0.5 to VCC+0.5 -1.5 to VCC +1.5 ±25 750 500 -65 to +150 260 Unit V V V V mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SO Package: - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VEE VIS VIN VIO TA tr, tf * Parameter Positive Supply Voltage (Referenced to GND) (Referenced to VEE) Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch Operating Temperature, All Package Types Input Rise and Fall Time (Channel Select or Enable Inputs) (Figure 5) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 2.0 - 6.0 VEE GND -55 0 0 0 Max 6.0 12.0 GND VCC VCC 1.2 +125 1000 500 400 Unit V V V V V °C ns * For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i. e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range indicated in the Recommended Operating Conditions.. Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. 2 KK74HC4052A DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE=GND, Except Where Noted VCC Symbol VIH Parameter Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Maximum Low -Level Input Voltage, Channel-Select or Enable Inputs Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Test Conditions RON = Per Spec V 2.0 4.5 6.0 2.0 4.5 6.0 6.0 Guaranteed Limit -55 °C to 25° C 1.5 3.15 4.2 0.3 0.9 1.2 ±0.1 ≤85 °C 1.5 3.15 4.2 0.3 0.9 1.2 ±1.0 ≤125 °C 1.5 3.15 4.2 0.3 0.9 1.2 ±1.0 Unit V VIL RON = Per Spec V IIN VIN=VCC or GND, VEE=-6.0 V µA ICC Channel Select = VCC or GND Enable = VCC or GND VIS = VCC or GND VEE = GND VIO= 0 V VEE = -6.0 V µA 6.0 6.0 2 8 20 80 40 160 DC ELECTRICAL CHARACTERISTICS Analog Section VCC Symbol RON Parameter Maximum “ON” Resistance Test Conditions VIN=VIL or VIH VIS = VCC to VEE IS ≤ 2.0 mA VIN=VIL or VIH VIS = VCC or VEE (Endpoints) IS ≤ 2.0 mA ∆RON Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Maximum Off- Channel Leakage Current, Any One Channel Maximum Off- Channel Leakage Current, Common Channel ION Maximum On- Channel Leakage Current, Channel to Channel VIN=VIL or VIH VIS = 1/2 (VCC- VEE) IS ≤ 2.0 mA VIN=VIL or VIH VIO = VCC- VEE Switch Off VIN=VIL or VIH VIO= VCC- VEE Switch Off VIN=VIL or VIH Switch to Switch = VCC- VEE V 4.5 4.5 6.0 4.5 4.5 6.0 4.5 4.5 6.0 6.0 VEE V 0.0 -4.5 -6.0 0.0 -4.5 -6.0 0.0 -4.5 -6.0 -6.0 Guaranteed Limit 25 °C to -55°C 190 120 100 150 100 80 30 12 10 0.1 ≤85 °C 240 150 125 190 125 100 35 15 12 0.5 ≤125 °C 280 170 140 230 140 115 40 18 14 1.0 Ω Unit Ω IOFF µA 6.0 -6.0 0.1 1.0 2.0 6.0 -6.0 0.1 1.0 2.0 µA 3 KK74HC4052A AC ELECTRICAL CHARACTERISTICS(CL=50pF, Input tr=tf=6.0 ns) VCC Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Channel-Select to Analog Output (Figures 1 and 2) Maximum Propagation Delay , Analog Input to Analog Output (Figures 3 and 4) Maximum Propagation Delay , Enable to Analog Output (Figures 5 and 6) Maximum Propagation Delay , Enable to Analog Output (Figures 5 and 6) Maximum Propagation Delay, Channel-Select to Analog Input (Figures 5 and 6) Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance Analog I/O Common O/I Feedthrough Power Dissipation Capacitance (Per Package) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC All Switches Off 80 1.0 80 1.0 80 1.0 V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 °C to -55°C 370 74 63 60 12 10 290 58 49 345 69 59 370 74 63 10 35 ≤85°C 465 93 79 75 15 13 364 73 62 435 87 74 465 93 79 10 35 ≤125°C 550 110 94 90 18 15 430 86 73 515 103 87 550 110 94 10 35 Unit ns tPLH, tPHL ns tPLZ, tPHZ ns tPZL, tPZH ns tPLZ, tPHZ, tPZL, tPZH CIN CI/O ns pF pF Typical @25°C,VCC=5.0 V, VEE=0 V 80 pF 4 KK74HC4052A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) Symbol BW Parameter Maximum OnChannel Bandwidth or Minimum Frequency Response Off-Channel Feedthrough Isolation Test Conditions fin =1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads -3 dB RL =50 Ω, CL=10 pF fin = Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL =600 Ω, CL=50 pF VCC V VEE V Limit 25 ° C MHz 2.25 4.50 6.00 -2.25 -4.50 -6.00 95 95 95 dB 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -50 -50 -50 -40 -40 -40 mVpp Unit KDoff fin = 1.0 MHz, RL =50 Ω, CL=10 pF VAO/I Feedthrough Noise, Channel Select Input to Common O/I fin ≤ 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS= 0 A Enable = GND RL =600 Ω, CL=50 pF 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 25 105 135 35 145 190 dB RL =10 Ω, CL=10 pF KDon Crosstalk Between Any Two Switches fin= Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL =600 Ω, CL=50 pF 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -50 -50 -50 -60 -60 -60 % fin = 1 MHz, RL =50 Ω, CL=10 pF THD Total Harmonic Distortion fin= 1 kHz, RL =10 kΩ, CL=50 pF THD = THDMeasured - THDSource VIS =4.0 VPP sine wave VIS =8.0 VPP sine wave VIS =11.0 VPP sine wave 2.25 4.50 6.00 -2.25 -4.50 -6.00 0.10 0.08 0.05 5 KK74HC4052A * Includes all probe and jig capacitance. Figure 1. Switching Waveforms Figure 2. Test Set-UP, Channel Select to Analog Out * Includes all probe and jig capacitance. Figure 3. Switching Waveforms Figure 4. Test Set-UP, Analog In to Analog Out Figure 5. Switching Waveforms Figure 6. Test Set-UP, Enable to Analog Out 6 KK74HC4052A EXPANDED LOGIC DIAGRAM 7 KK74HC4052A N S UFFIX PLAS TIC DIP (MS - 0 0 1 BB) A Dimens ion, mm 16 9 B Symbol A MIN 18.67 6.1 MAX 19.69 7.11 5.33 1 8 B C F L D F 0.36 1.14 2.54 7.62 0° 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLAN E G H H J N G D 0.25 (0.010) M T K M J K L M N 10° 3.81 8.26 0.36 NOTES : 1. Dimen s io n s “A ”, “B” d o n o t in clu d e mo ld flas h o r p ro tru s io n s . Maximu m mo ld flas h o r p ro tru s io n s 0.25 mm (0.010) p er s id e. D S UFFIX S OIC (MS - 0 1 2 AC) Dimens ion, mm A 16 9 Symbol A MIN 9.8 3.8 1.35 0.33 0.4 1.27 5.72 0° 0.1 0.19 5.8 0.25 MAX 10 4 1.75 0.51 1.27 H B P B C 1 G 8 C R x 45 D F G -TD 0.25 (0.010) M T C M K SEAT ING PLAN E J F M H J K M P R 8° 0.25 0.25 6.2 0.5 NOTES : 1. Dimen s io ns A an d B d o n o t in clud e mo ld flas h o r p rotru s ion . 2. M aximu m mo ld flas h o r p ro tru s io n 0.15 mm (0.006) p er s id e fo r A ; fo r B ‑ 0.25 mm (0.010) p er s id e. 8