ML145146

ML145146 4–Bit Data Bus Input PLL Frequency Synthesizer INTERFACES WITH DUAL–MODULUS PRESCALERS Legacy Device: Motorola MC145146-2 The ML145146 is programmed by a 4–bit input, with strobe and address lines. The device features consist of a reference oscillator, 12–bit programmable reference divider, digital phase detector, 10–bit programmable divide–by–N counter, 7–bit divide–by–A counter, and the necessary latch circuitry for accepting the 4–bit input data. • Operating Temperature Range: TA – 40 to +85°C • Low Power Consumption Through the Use of CMOS Technology • 3.0 to 9.0 V Supply Range • Programmable Reference Divider for Values Between 3 and 4095 • Dual–Modulus 4–Bit Data Bus Programming • ÷ N Range = 3 to 1023, ÷ A Range= 0 to 127 • “Linearized” Digital Phase Detector Enhances Transfer Function Linearity • Two Error Signal Options: Single–Ended (Three–State) Double–Ended P DIP 20 = RP PLASTIC DIP CASE 738 1 20 20 SOG 20 W = -6P SOG PACKAGE CASE 751D 1 CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE P DIP 20 MC145146P2 ML145146RP SOG 20W MC145146DW2 ML145146-6P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. PIN ASSIGNMENT D1 D0 fin 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D2 D3 fR φR φV fV MC LD ST A2 BLOCK DIAGRAM VSS PDout OSCin OSCout D0 D1 D2 D3 A2 A1 A0 ST 12–BIT ÷ R COUNTER L5 L6 L7 LOCK DETECT VDD fR OSCin OSCout LD A0 A1 PHASE DETECTOR A PDout fV LATCH CONTROL CIRCUITRY LATCHES L2 fin L3 L4 L0 L1 PHASE DETECTOR B φV φR 10–BIT ÷ N COUNTER 7–BIT ÷ A COUNTER CONTROL LOGIC MODULUS CONTROL (MC) Page 1 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 2 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 3 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 4 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. Page 5 of 12 www.lansdale.com Issue 0 ML145146 LANSDALE Semiconductor, Inc. PIN DESCRIPTIONS INPUT PINS D0 - D3 Data Inputs (Pins 2, 1, 20, 19) Information at these inputs is transferred to the internal latches when the ST input is in the high state. D3 (Pin 19) is the most significant bit. f in Frequency Input (Pin 3) Input to ÷N portion of synthesizer f in is typically derived from loop VCO and is AC coupled into Pin 3. For larger amplitude signals (standard CMOS – logic levels) DC coupling may be used. OSCin/OSCout Reference Oscillator Input/Output (Pins 7 and 8) These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as input for an externally–generated reference signal. This signal is typically AC coupled to OSCin, but for larger amplitude signals (standard CMOS–logic levels) DC coupling may also be used. In the external reference mode, no connection is required to OSCout. A0 - A2 Address Inputs (Pins 9, 10, 11) A0, A1 and A2 are used to define which latch receives the information on the data input lines. The addresses refer to the following latches. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Selected Latch 0 Latch 1 Latch 2 Latch 3 Latch 4 Latch 5 Latch 6 Latch 7 Function ÷ A Bits ÷ A Bits ÷ N Bits ÷ N Bits ÷ N Bits Reference Bits Reference Bits Reference Bits D0 0 4 0 4 8 0 4 8 D1 1 5 1 5 9 1 5 9 D2 2 6 2 5 — 2 6 10 D3 3 — 3 7 — 3 7 11 ST Strobe Transfer (Pin 12) The rising edge of strobe transfers data into the addressed latch. The falling edge of strobe latches data into the latch. This pin should normally be held low to avoid loading latches with invalid data. OUTPUT PINS PDout Single–ended Phase Detector Output (Pin 5) Three–state output of phase detector for use as loop error signal. Frequency fV>fR or fV Leading: Negative Pulses Frequency fV