LFSC3GA25KLUTSEP1F256C

LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features ■ High Performance FPGA Fabric • 15K to 115K four input Look-up Tables (LUT4s) • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks ■ 4 to 32 High Speed SERDES and flexiPCS™ (per Device) • Performance ranging from 600Mbps to 3.8Gbps • Excellent Rx jitter tolerance (0.8UI at 3.125Gbps) • Low Tx jitter (0.25UI typical at 3.125Gbps) • Built-in Pre-emphasis and equalization • Low power (typically 105mW per channel) • Embedded Physical Coding Sublayer (PCS) provides pre-engineered implementation for the following standards: – GbE, XAUI, PCI Express, SONET, Serial RapidIO, 1G Fibre Channel, 2G Fibre Channel – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM – 500MHz performance • Additional 240K to 1.8Mbits distributed RAM ■ sysCLOCK™ Network • Eight analog PLLs per device – Frequency range from 15MHz to 1GHz – Spread spectrum support • 12 DLLs per device with direct control of I/O delay – Frequency range from 100MHz to 700MHz • Extensive clocking network – 700MHz primary and 325 MHz secondary clocks – 1GHz I/O-connected edge clocks • Precision Clock Divider – Phase matched x2 and x4 division of incoming clocks • Dynamic Clock Select (DCS) – Glitch free clock MUX ■ 2Gbps High Performance PURESPEED™ I/O • Supports the following performance bandwidths – Differential I/O up to 2Gbps DDR (1GHz Clock) – Single-ended memory interfaces up to 800Mbps • 144 Tap programmable Input Delay (INDEL) block on every I/O dynamically aligns data to clock for robust performance – Dynamic bit Adaptive Input Logic (AIL) monitoring and control circuitry per pin that automatically ensures proper set-up and hold – Dynamic bus: uses control bus from DLL – Static per bit • Electrical standards supported: – LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL – SSTL 3/2/18 I, II; HSTL 18/15 I, II – PCI, PCI-X – LVDS, Mini-LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS, Hypertransport • Programmable On Die Termination (ODT) – Includes Thevenin Equivalent and low power VTT termination options ■ Masked Array for Cost Optimization (MACO™) Blocks • On-chip structured ASIC Blocks provide preengineered IP for low power, low cost system level integration ■ High Performance System Bus • Ties FPGA elements together with a standard bus framework – Connects to peripheral user interfaces for run-time dynamic configuration ■ System Level Support • IEEE standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer • IEEE Standard 1532 in-system configuration • 1.2V and 1.0V operation • Onboard oscillator for initialization and general use • Embedded PowerPC microprocessor interface • Low cost wire-bond and high pin count flip-chip packaging • Low cost SPI Flash RAM configuration ■ Memory Intensive FPGA • sysMEM™ embedded Block RAM © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1-1 DS1004 Introduction_01.6 Lattice Semiconductor Table 1-1. LatticeSC Family Selection Guide Device LUT4s (K) sysMEM Blocks (18Kb) Embedded Memory (Mbits) Max. Distributed Memory (Mbits) Number of 3.8Gbps SERDES (Max.) DLLs Analog PLLs MACO Blocks 256-ball fpBGA (17 x 17mm) 900-ball fpBGA (31 x 31mm) 1020-ball fcBGA (33 x 33mm) 1152-ball fcBGA (35 x 35mm) 1704-ball fcBGA (42.5 x 42.5mm) SC15 15 56 1.03 0.24 8 12 8 4 139/4 300/8 378/8 476/16 SC25 25 104 1.92 0.41 16 12 8 6 Introduction LatticeSC/M Family Data Sheet SC40 40 216 3.98 0.65 16 12 8 10 SC80 80 308 5.68 1.28 32 12 8 10 SC115 115 424 7.8 1.84 32 12 8 12 Package I/O/SERDES Combinations (1mm ball pitch) 562/16 604/16 660/16 904/32 660/16 942/32 Note: The information in this preliminary data sheet is by definition not final and subject to change. Please consult the Lattice website and your local Lattice sales manager to ensure you have the latest information regarding the specifications for these products as you make critical design decisions. The LatticeSCM devices add MACO-enabled IP functionality to the base LatticeSC devices. Table 1-2 shows the type and number of each pre-engineered IP core. Table 1-2. LatticeSCM Family Device flexiMAC Blocks • 1GbE Mode • 10GbE Mode • PCI Express Mode SPI4.2 Blocks Memory Controller Blocks • DDR/DDR2 DRAM Mode • QDR II/II+ SRAM Mode • RLDRAM I • RLDRAM II CIO/SIO Low Speed CDR Blocks PCI Express LTSSM (PHY) Blocks SCM15 1 1 SCM25 2 2 SCM40 2 2 SCM80 2 2 SCM115 4 2 1 2 2 2 2 0 1 0 0 2 2 2 2 2 2 Note: See each IP core user’s guide for more information about support for specific LatticeSCM devices. Introduction The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-speed SERDES, high-performance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a state of the art technology to provide one of the highest performing FPGAs in the industry. This family of devices includes features to meet the needs of today’s communication network systems. These features include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, HyperTransport, SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. The devices in this family feature clock multiply, divide and phase shift PLLs, numerous DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs. High speed, high bandwidth I/O make this family ideal for high throughput systems. 1-2 Lattice Semiconductor Introduction LatticeSC/M Family Data Sheet The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the LatticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and backannotates it into the design for timing verification. Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeSC family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. Innovative high-performance FPGA architecture, high-speed SERDES with PCS support, sysMEM embedded memory and high performance I/O are combined in the LatticeSC to provide excellent performance for today’s leading edge systems designs. Table 1-3 details the performance of several common functions implemented within the LatticeSC. Table1-3. Speed Performance for Typical Functions1 Functions 32-bit Address Decoder 64-bit Address Decoder 32:1 Multiplexer 64-bit Adder (ripple) 32x8 Distributed Single Port (SP) RAM 64-bit Counter (up or down counter, non-loadable) True Dual-Port 1024x18 bits FIFO Port A: x36 bits, B: x9 bits Performance (MHz)2 539 517 779 353 768 369 372 375 1. For additional information, see Typical Building BLock Function Performance table in this data sheet. 2. Advance information (-7 speed grade). 1-3 LatticeSC/M Family Data Sheet Architecture June 2008 Data Sheet DS1004 Architecture Overview The LatticeSC architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR). The upper left and upper right corners of the devices contain SERDES blocks and their associated PCS blocks, as show in Figure 2-1. Top left and top right corner of the device contain blocks of SERDES. Each block of SERDES contains four channels (quad). Each channel contains a single serializer and de-serializer, synchronization and word alignment logic. The SERDES quad connects with the Physical Coding Sub-layer (PCS) blocks that contain logic to simultaneously perform alignment, coding, de-coding and other functions. The SERDES quad block has separate supply, ground and reference voltage pins. The PICs contain logic to facilitate the conditioning of signals to and from the I/O before they leave or enter the FPGA fabric. The block provides DDR and shift register capabilities that act as a gearbox between high speed I/O and the FPGA fabric. The blocks also contain programmable Adaptive Input Logic that adjusts the delay applied to signals as they enter the device to optimize setup and hold times and ensure robust performance. sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM, ROM or FIFO. These blocks have dedicated logic to simplify the implementation of FIFOs. The PFU, PIC and EBR blocks are arranged in a two-dimensional grid with rows and columns as shown in Figure 2-1. These blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. The corners contain the sysCLOCK Analog Phase Locked Loop (PLL) and Delay Locked Loop (DLL) Blocks. The PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. The LatticeSC architecture provides eight analog PLLs per device and 12 DLLs. The DLLs provide a simple delay capability and can also be used to calibrate other delays within the device. Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™ port which allows for serial or parallel device configuration. The system bus simplifies the connections of the external microprocessor to the device for tasks such as SERDES and PCS configuration or interface to the general FPGA logic. The LatticeSC devices use 1.2V as their core voltage operation with 1.0V operation also possible. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 2-1 DS1004 Architecture_01.9 Lattice Semiconductor Figure 2-1. Simplified Block Diagram (Top Level) Quad SERDES Architecture LatticeSC/M Family Data Sheet Quad SERDES sysCLOCK Analog PLLs Physical Coding Sublayer (PCS) sysCLOCK DLLs Programmable I/O Cell (PIC) includes PURESPEED I/O Interface Structured ASIC Block (MACO) Each PIC contains four Programmable I/Os (PIO) Programmable Function Unit (PFU) sysMEM Embedded Block RAM (EBR) Three PICs per four PFUs sysCLOCK Analog PLLs sysCLOCK DLLs 2-2 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet PFU Blocks The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnections to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block. Figure 2-2. PFU Diagram From Routing LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY LUT4 & CARRY Slice 0 Slice 1 Slice 2 Slice 3 D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch D FF/ Latch To Routing Slice Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and some associated logic that allows the LUTs to be combined to implement 5, 6, 7 and 8 Input LUTs (LUT5, LUT6, LUT7 and LUT8). There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks. There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated with each slice. 2-3 Lattice Semiconductor Figure 2-3. Slice Diagram FCO from Slice/PFU, FCI into Different Slice/PFU Architecture LatticeSC/M Family Data Sheet Slice OFX1 A1 B1 C1 D1 CO F1 F D LUT4 & CARRY CI Q1 FF/ Latch To Routing From Routing M1 M0 LUT Expansion Mux OFX0 A0 B0 C0 D0 CO LUT4 & CARRY CI F OFX0 D F0 Q0 FF/ Latch Control Signals selected and inverted per slice in routing CE CLK LSR Note: some interslice signals not shown. FCI into Slice/PFU, FCO from Different Slice/PFU Table 2-1. Slice Signal Descriptions Function Input Input Input Input Input Input Input Input Output Output Output Output Output Type Data signal Data signal Multi-purpose Multi-purpose Control signal Control signal Control signal Inter-PFU signal Data signals Data signals Data signals Data signals Inter-PFU signal Signal Names A0, B0, C0, D0 Inputs to LUT4 A1, B1, C1, D1 Inputs to LUT4 M0 M1 CE LSR CLK FCI F0, F1 Q0, Q1 OFX0 OFX1 FCO Multipurpose Input Multipurpose Input Clock Enable Local Set/Reset System Clock Fast Carry In1 LUT4 output register bypass signals Register Outputs Output of a LUT5 MUX Output of a LUT6, LUT7, LUT82 MUX depending on the slice For the right most PFU the fast carry chain output2 Description 1. See Figure 2-2 for connection details. 2. Requires two PFUs. 2-4 Lattice Semiconductor Modes of Operation Architecture LatticeSC/M Family Data Sheet Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. Table 2-2 lists the modes and the capability of the Slice blocks. Table 2-2. Slice Modes Logic PFU Slice LUT 4x2 or LUT 5x1 Ripple 2-bit Arithmetic Unit RAM SPR 16x2 DPR 16x2 ROM ROM 16x2 Logic Mode In this mode, the LUTs in each Slice are configured as combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices in the PFU. Ripple Mode Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice: • • • • • Addition 2-bit Subtraction 2-bit Up counter 2-bit Down counter 2-bit Comparator functions of A and B inputs - A greater-than-or-equal-to B - A not-equal-to B - A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. RAM Mode In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combination of LUTs and Slices, a variety of different memories can be constructed. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the software will construct these using distributed memory primitives that represent the capabilities of the Slice. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Dual port memories involve the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the readonly port. For more information on RAM mode, please see details of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required For Implementing Distributed RAM SPR16x2 Number of Slices 1 DPR16x2 2 Note: SPR = Single Port RAM, DPR = Dual Port RAM ROM Mode The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accomplished through the programming interface during configuration. 2-5 Lattice Semiconductor PFU Modes of Operation Architecture LatticeSC/M Family Data Sheet Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the functionality possible at the PFU level. Table 2-4. PFU Modes of Operation Logic LUT 4x8 or MUX 2x1 x 8 LUT 5x4 or MUX 4x1 x 4 LUT 6x2 or MUX 8x1 x 2 LUT 7x1 or MUX 16x1 x 1 Ripple 2-bit Add x 4 2-bit Sub x 4 2-bit Counter x 4 2-bit Comp x 4 RAM SPR 16x2 x 4 DPR 16x2 x 2 SPR 16x4 x 2 DPR 16x4 x 1 SPR 16x8 x 1 ROM ROM 16x1 x 8 ROM 16x2 x 4 ROM 16x4 x 2 ROM 16x8 x1 Routing There are many resources provided in the LatticeSC devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU) resources. The x1 and x2 connections provide fast and efficient connections in horizontal, vertical and diagonal directions. All connections are buffered to ensure high-speed operation even with long high-fanout connections. The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysCLOCK Network The LatticeSC devices have three distinct clock networks for use in distributing high-performance clocks within the device: primary clocks, secondary clocks and edge clocks. In addition to these dedicated clock networks, users are free to route clocks within the device using the general purpose routing. Figure 2-4 shows the clock resources available to each slice. Figure 2-4. Slice Clock Selection Primary Clock Secondary Clock Routing GND 12 6 Clock to Slice Note: GND is available to switch off the network. Primary Clock Sources LatticeSC devices have a wide variety of primary clock sources available. Primary clocks sources consists of the following: • Primary clock input pins • Edge clock input pins • Two outputs per DLL 2-6 Lattice Semiconductor • • • • Two outputs per PLL Clock divider outputs Digital Clock Select (DCS) block outputs Three outputs per SERDES quad Architecture LatticeSC/M Family Data Sheet Figure 2-5 shows the arrangement of the primary clock sources. Figure 2-5. Clock Sources Edge Clock PIOs Primary/ Edge Clock PIOs PLL PLL PLL SERDES DCS DCS SERDES PLL DLL Primary/ Edge Clock PIOs DLL Clock Dividers (3 per SERDES Channel) (3 per SERDES Channel) DLL DLL Primary/ Edge Clock PIOs 4 Edge Clock PIOs Edge Clock PIOs DCS DCS Primary Clock Sources DCS 24 24 DCS Primary/ Edge Clock PIOs Clock Dividers DLL DLL DLL DLL Clock Dividers DLL DLL Primary/ Edge Clock PIOs 8 DLL DLL PLL PLL Clock Dividers DCS DCS Clock Dividers PLL PLL Edge Clock PIOs Primary/ Edge Clock PIOs Edge Clock PIOs Primary/ Edge Clock PIOs Primary Clock Routing The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6 shows this clock routing. 2-7 Lattice Semiconductor Figure 2-6. Per Quadrant Clock Selection Architecture LatticeSC/M Family Data Sheet 12 feedlines per quadrants times 4 + Clock Sources 60 Primary 12 feedlines from upper and lower half From Local Routing 60 GND From Local Routing 60 GND From Local Routing 60 GND 3 3 3 12 Primary Clock per Quadrants 12 Primary Clocks Note: GND is available to switch off the network. Secondary Clocks In addition to the primary clock network and edge clocks the LatticeSC devices also contain a secondary clock network. Built of X6 style routing elements this secondary clock network is ideal for routing slower speed clock and control signals throughout the device preserving high-speed clock networks for the most timing critical signals. Edge Clocks LatticeSC devices have a number of high-speed edge clocks that are intended for use with the PIOs in the implementation of high-speed interfaces. There are eight edge clocks per bank for the top and bottom of the device. The left and right sides have eight edge clocks per side for both banks located on that side. Figure 2-7 shows the arrangement of edge clocks. Edge clock resources can be driven from a variety of sources. Edge clock resources can be driven from: • • • • • Edge clock PIOs in the same bank Primary clock PIOs in the same bank Routing Adjacent PLLs and DLLs ELSR output from the clock divider 2-8 Lattice Semiconductor Figure 2-7. Edge Clock Resources Bank 1 SERDES Architecture LatticeSC/M Family Data Sheet SERDES Edge clock Bank 7 Bank 6 Bank 5 Bank 2 Bank 3 Bank 4 Precision Clock Divider Each set of edge clocks has four high-speed dividers associated with it. These are intended for generating a slower speed system clock from the high-speed edge clock. The block operates in a DIV2 or DIV4 mode and maintains a known phase relationship between the divided down clock and high-speed clock based on the release of its reset signal. The clock dividers can be fed from selected PIOs, PLLs and routing. The clock divider outputs serve as primary clock sources. This circuit also generates an edge local set/reset (ELSR) signal which is fed to the PIOs via the edge clock network and is used for the rest of the I/O gearing logic. Figure 2-8. Clock Divider Circuit Divided clock S/R S/R S/R S/R Clock derived from selected PIOs, PLLs and routing LSR ELSR Register chain to synchronize LSR to clock input Dynamic Clock Select (DCS) The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is 2-9 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-9 illustrates the DCS Block diagram. Figure 2-9. DCS Block Diagram CLK0 CLK1 SEL DCS DCSOUT Figure 2-10 shows timing waveforms for one of the DCS operating modes. The DCS block can be programmed to other modes. For more information on the DCS, please see details of additional technical documentation at the end of this data sheet. Figure 2-10. DCS Waveforms CLK0 CLK1 SEL DCSOUT Clock Boosting There are programmable delays available in the clock signal paths in the PFU, PIC and EBR blocks. These allow setup and clock-to-output times to be traded to meet critical timing without slowing the system clock. If this feature is enabled then the design tool automatically uses these delays to improve timing performance. Global Set/Reset There is a global set/reset (GSR) network on the device that is distributed to all FFs, PLLs, DLLs and other blocks on the device. This GSR network can operate in two modes: a) asynchronous - no clock is required to get into or out of the reset state. b) synchronous - The global GSR net is synchronized to a user selected clock. In this mode it continues to be asynchronous to get into the reset state, but is synchronous to get out of the reset state. This allows all registers on the device to become operational in the same clock period. The synchronous GSR goes out of reset in two cycles from the clock edge where the setup time of the FF was met (not from the GSR being released). sysCLOCK Phase Locked Loops (PLLs) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider and two clock output dividers. The input divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. 2-10 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet The setup and hold times of the device can be improved by programming a delay in the feedback or input path of the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically. The Phase Select block can modify the phase of the clock signal if desired. The Spread Spectrum block supports the modulation of the PLL output frequency. This reduces the peak energy in the fundamental and its harmonics providing for lower EMI (Electro Magnetic Interference). The sysCLOCK PLL can be configured at power-up and then, if desired, reconfigured dynamically through the serial memory interface bus which connects with the on-chip system bus. For example, the user can select inputs, loop filters, divider setting, delay settings and phase shift settings. The user can also directly access the SMI bus through the routing. The PLL clock input, from pin or routing, feeds into an input divider. There are four sources of feedback signal to the feedback divider: from the clock net, directly from the voltage controlled oscillator (VCO) output, from the routing or from an external pin. The signal from the input clock divider and the feedback divider are passed through the programmable delay before entering the phase frequency detector (PFD) unit. The output of this PFD is used to control the voltage controlled oscillator. There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the sysCLOCK PLL diagram. Figure 2-11. PLL Diagram CLKOP CLKI Div Prog Delay PFD CLKFB Div Prog Delay Div VCO/ Loop Filter Phase Adjust Prog Delay Div CLKOS RSTN Optional Internal Feedback From PFD LOCK For more information on the PLL, please see details of additional technical documentation at the end of this data sheet. Spread Spectrum Clocking (SSC) The PLL supports spread spectrum clocking to reduce peak EMI by using “down-spread” modulation. The spread spectrum operation will vary the output frequency (at 30KHz to 500KHz) in a range that is between its nominal value, down to a frequency that is a programmable 1%, 2%, or 3% lower than normal. Digital Locked Loop (DLLs) In addition to PLLs, the LatticeSC devices have up to 12 DLLs per device. DLLs assist in the management of clocks and strobes. DLLs are well suited to applications where the clock may be stopped or transferring jitter from input to output is important, for example forward clocked interfaces. PLLs are good for applications requiring the lowest output jitter or jitter filtering. All DLL outputs are routed as primary/edge clock sources. The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the outputs from the tapped delay line. The CLKOS has optional fine phase shift and divider blocks to allow this output to be further modified, if required. The fine phase shift block allows the CLKOS output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. LOCK output signal is asserted when the DLL is locked. The ALU HOLD signal setting allows users to freeze the DLL at its current delay setting. 2-11 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet There is a Digital Control (DCNTL) bus available from the DLL block. This Digital Control bus is available to the delay lines in the PIC blocks in the adjacent banks. The UDDCNTL signal allows the user to latch the current value on the digital control bus. Figure 2-12 shows the DLL block diagram of the DLL inputs and outputs. The output of the phase frequency detector controls an arithmetic logic unit (ALU) to add or subtract one delay tap. The digital output of this ALU is used to control the delay value of the delay chain and this digital code is transmitted via the DCNTL bus. The sysCLOCK DLL can be configured at power-up, then, if desired, reconfigured dynamically through the Serial Memory Interface bus which interfaces with the on-chip Microprocessor Interface (MPI) bus. In addition, users can drive the SMI interface from routing if desired. The user can configure the DLL for many common functions such as clock injection match and single delay cell. Lattice provides primitives in its design for time reference delay (DDR memory) and clock injection delay removal. Figure 2-12. DLL Diagram CLKI PFD CLKFB ALU ALUHOLD Delay Chain Phase Adj Duty50 CLKOP CLKOS Phase Adj Duty50 LOCK UDDCNTL RSTN DCNTL Gen DCNTL PLL/DLL Cascading The LatticeSC devices have been designed to allow certain combinations of PLL and DLL cascading. The allowable combinations are as follows: • • • • PLL to PLL PLL to DLL DLL to DLL DLL to PLL DLLs are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applications to utilize the unique benefits of both DLL and PLLs. When cascading the DLL to the PLL, the DLL can be used to drive the PLL to create fine phase shifts of an input clock signal. Figure 2-13 shows a shift of all outputs for CLKOP and CLKOS out in time. 2-12 Lattice Semiconductor Figure 2-13. DLL to PLL Architecture LatticeSC/M Family Data Sheet CLKOP CLKI DLL CLKOS PLL CLKOS SMI Bus Figure 2-14 shows a shift of only CLKOP out in time. Figure 2-14. PLL to DLL CLKI PLL CLKOP DLL CLKOS SMI Bus Figure 2-15 shows a shift of only CLKOS out in time. Figure 2-15. PLL to DLL CLKI PLL CLKOS DLL CLKOS SMI Bus For further information on the DLL, please see details of additional technical documentation at the end of this data sheet. sysMEM Memory Block The sysMEM block can implement single port, true dual port, pseudo dual port or FIFO memories. Dedicated FIFO support logic allows the LatticeSC devices to efficiently implement FIFOs without consuming LUTs or routing resources for flag generation. Each block can be used in a variety of depths and widths as shown in Table 2-5. Memory with ranges from x1 to x18 in all modes: single port, pseudo-dual port and FIFO also providing x36. 2-13 Lattice Semiconductor Table 2-5. sysMEM Block Configurations Memory Mode Architecture LatticeSC/M Family Data Sheet Configurations 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 Single Port True Dual Port Pseudo Dual Port FIFO Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port. RAM Initialization and ROM Operation If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the output. A clock is required even in asynchronous read mode. The EBR memory supports two forms of write behavior for dual port operation: 1. Normal — data on the output appears only during a read cycle. During a write cycle, the data (at the current address) does not appear on the output. 2. Write Through — a copy of the input data appears at the output of the same port. FIFO Configuration The FIFO has a write port with Data-in, WCE, WE and WCLK signals. There is a separate read port with Data-out, RCE, RE and RCLK signals. The FIFO internally generates Almost Full, Full, Almost Empty, and Empty Flags. The Full and Almost Full flags are registered with WCLK. The Empty and Almost Empty flags are registered with RCLK. 2-14 Lattice Semiconductor EBR Asynchronous Reset Architecture LatticeSC/M Family Data Sheet EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the low-to-high transition of the reset, as shown in Figure 2-16. Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram Reset Clock Clock Enable If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge. If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device Wake Up must occur before the release of the device I/Os becoming active. These instructions apply to all EBR RAM, ROM, FIFO and shift register implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-16. The reset timing rules apply to the RPReset input vs. the RE input and the RST input vs. the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. For the EBR shift register mode, the GSR signal is always enabled and the local RESET pin is always asynchronous. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. For more information about on-chip memory, see TN1094, On-Chip Memory Usage Guide for LatticeSC Devices. Programmable I/O Cells (PIC) Each PIC contains four PIOs connected to their respective PURESPEED I/O Buffer which are then connected to the PADs as shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to PURESPEED I/O buffer, and receives input (DI) from the buffer. The PIO contains advanced capabilities to allow the support of speeds up to 2Gbps. These include dedicated shift and DDR logic and adaptive input logic. The dedicated resources simplify the design of robust interfaces. 2-15 Lattice Semiconductor Figure 2-17. PIC Diagram PIO A TD Tristate Register Block IOLT0 DO Architecture LatticeSC/M Family Data Sheet TO OPOS0 ONEG0 OPOS1 ONEG1 OPOS2 ONEG2 OPOS3 ONEG3 PADA "T" Output Register Block DO PURESPEED I/O Buffer INCK INDD INFF IPOS0 INEG0 IPOS1 INEG1 IPOS2 INEG2 IPOS3 INEG3 RUNAIL LOCK CLK CE LSR GSRN ELSR ECLK HCLKOUT LCLKOUT CEO LSRO GSR LSRO HCLKIN LCLKIN DI DI Input Register Block (including delay and AIL elements*) Control Muxes Update Block POS Update NEG Update UPDATE PIO B PIO C PIO D *AIL only on A or C pads located on the left, right and bottom of the device. PADB “C” PADC “T” PADD “C” The A/B PIOs on the left and the right of the device can be paired to form a differentiated driver. The A/B and C/D PIOs on all sides of the device can be paired to form differential receivers. Either A or C PIOs on all sides except the one on top also provide a connection to an adaptive input logic capability that facilitates the implementation of 2-16 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet high-speed interfaces in the LatticeSC devices. Figure 2-18 shows how differential receivers and drivers are arranged between PIOs. Figure 2-18. Differential Drivers and Receivers PIO A PIO B PIO C PIO D *Differential Driver only available on right and left of the device. PADA "T" PADB "C" PADC "T" PADD "C" PIO The PIO contains five blocks: an input register block, output register block, tristate register block, update block, and a control logic block. These blocks contain registers for both single data rate (SDR), double data rate (DDR), and shift register operation along with the necessary clock and selection logic. Input Register Block The input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. Figure 2-20 show the diagram of the input register block. The signal from the PURESPEED I/O buffer (DI) enters the input register block and can be used for three purposes, as a source for the combinatorial (INDD) and clock outputs (INCK), the input into the SDR register/latch block and the input to the delay block. The output of the delay block can be used as combinatorial (INDD) and clock (INCK) outputs, an input to the DDR/Shift Register Block or an input into the SDR register block. Input SDR Register/Latch Block The SDR register/latch block has a latch and a register/latch that can be used in a variety of combinations to provide a registered or latched output (INFF). The latch operates off high-speed input clocks and latches data on the positive going edge. The register/latch operates off the low-speed input clock and registers/latches data on the positive going edge. Both the latch and the register/latch have a clock enable input that is driven by the input clock enable. In addition both have a variety of programmable options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over CE) and Global Set Reset GSR enable or disable. The register and latch LSR inputs are driven from LSRI, which is generated from the PIO control MUX. The GSR inputs are driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on a PIO basis. Input Delay Block The delay block uses 144 tapped delay lines to obtain coarse and fine delay resolution. These delays can be adjusted during configuration or automatically via DLL or AIL blocks. The Adaptive Input Logic (AIL) uses this delay block to adjust automatically the delay in the data path to ensure that it has sufficient setup and hold time. The delay line in this block matches the delay line that is used in the 12 on-chip DLLs. The delay line can be set via configuration bits or driven from a calibration bus that allows the setting to be controlled either from one of the onchip DLLs or user logic. Controlling the delay from one of the on-chip DLLs allow the delay to be calibrated to the DLL clock and hence compensated for the variations in process, voltage and temperature. 2-17 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet Adaptive Input Logic (AIL) Overview The Adaptive Input Logic (AIL) provides the ability of the input logic to dynamically find a solution by monitoring multiple samples of the input data. The input data signal from the input buffer is run through a delay chain. Data, transitions, jitter, noise are all contained inside of the delay chain. The AIL will then search the delay chain for a clean sampling point for data. Once found the AIL will monitor and walk with the data dynamically. This novel approach of using a delay chain to create multiple copies of the data provides a lower power solution than oversampling data with a higher speed clock. Figure 2-19 provides a high level view of the AIL methodology. Figure 2-19. LatticeSC AIL Delay of Input Data Waveform Input Data Signal Delay Chain AIL Acquisition Window The AIL slides the acquisition window through the delay chain searching for stable data based solely on data transitions. A specific training pattern is not required to perform this bit alignment, simply data transitions. The size of the acquisition window is user-selectable allowing the AIL to operate over the full range of the PURESPEED I/O range. Based on dynamic user control the AIL can either continuously adjust the window location based on data edge detection or it can be locked to a specific delay. The AIL operates on single data and double data rate interfaces and is available on most FPGA input pins on the LatticeSC device and all buffer types. The AIL block is low power using only 0.003 mW/MHz typical (6 mW @ 2 Gbps) for PRBS 27 data. Multiple AIL inputs can be used to create a bus with a FPGA circuit to realign the bus to a common clock cycle. The FPGA circuit to realign the bus is required and is provided by Lattice as a reference design. For more information on the LatticeSC AIL please refer to the LatticeSC AIL User’s Guide. Input DDR/Shift Block The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the high-speed clock and the associated transfer to the low-speed clock domain. It functions as a gearbox allowing high-speed incoming data to be passed into the FPGA fabric. Each PIO supports DDR and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. The PIOs A and C on the left, right and bottom of the device also contain an optional Adaptive Input Logic (AIL) element. This logic automatically aligns incoming data with the clock allowing for easy design of high-speed interfaces. Figure 2-21 shows a simplified block diagram of the shift register block. The shift block in conjunction with the update and clock divider blocks automatically handles the hand off between the low-speed and high-speed clock domains. 2-18 Lattice Semiconductor Figure 2-20. Input Register Block1 CLKENABLE Architecture LatticeSC/M Family Data Sheet CLKDISABLE INDD INCK SDR Register/Latch Block INFF D-Type/ Latch Latch To Routing DI (from PURESPEED I/O Buffer) Delay Block Optional Adaptive Input Logic2 DDR/Shift Register Block • DDR • DDR + half clock • DDR + shift x1 • DDR + shift x2 • DDR + shift x43 • Shift x1 • Shift x2 • Shift x43 IPOS0 IPOS1 INEG0 INEG1 LCLKIN (ECLK/SCLK) HCLKIN (ECLK/SCLK) LOCK RUNAIL DCNTL[0:8] (From DLL) 1. UPDATE, Set and Reset not shown for clarity 2. Adaptive input logic is only available in selected PIO 3. By four shift modes utilize DDR/shift register block from paired PIO. 4. CLKDISABLE is used to block the transitions on the DQS pin during post-amble. Its main use is to disable DQS (typically found in DDR memory interfaces) or other clock signals. It can also be used to disable any/all input signals to save power. 2-19 Lattice Semiconductor Figure 2-21. Input DDR/Shift Register Block From paired PIO for wide muxing To paired PIO for wide muxing Architecture LatticeSC/M Family Data Sheet Bypass used for DDR Data Input (From Delay Block) IPOS0 (Can act as IPOS2 when paired) IPOS1 (Can act as IPOS3 when paired) HCLKIN LCLKIN POS Update NEG Update Bypass used for DDR INEG0 (Can act as INEG2 when paired) Used for DDR with Half Clock Transfer INEG1 (Can act as INEG3 when paired) From paired PIO for wide muxing To paired PIO for wide muxing Output Register Block The output register block provides the ability to register signals from the core of the device before they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of registers for DDR and shift register operation. The output signal (DO) can be derived directly from one of the inputs (bypass mode), the SDR register or the DDR/shift register block. Figure 2-22 shows the diagram of the Output Register Block. Output SDR Register/Latch Block The SDR register operates on the positive edge of the high-speed clock. It has clock enable that is driven by the clock enable output signal generated by the control MUX. In addition it has a variety of programmable options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over CE) and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control MUX. The GSR inputs is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on a PIO basis. Output DDR/Shift Block The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing low-speed parallel data from the FPGA fabric be output as a higher speed serial stream. Each PIO supports DDR and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. Figure 2-22 shows a simplified block diagram of the shift register block. 2-20 Lattice Semiconductor Figure 2-22. Output Register Block1 Architecture LatticeSC/M Family Data Sheet To Tri-state Block SDR Register From Routing OPOS0 ONEG0 OPOS1 ONEG1 DDR/Shift Register Block • DDR • DDR + half clock • DDR + shift x2 • DDR + shift x42 • Shift x2 • Shift x42 DO (to PURESPEED I/O Buffer) From LCLKOUT Control HCLKOUT MUX Notes: 1. CE, Update, Set and Reset not shown for clarity. 2. By four shift modes utilizes DDR/Shift register block from paired PIO. 3. DDR/Shift register block shared with tristate block. Figure 2-23. Output/Tristate DDR/Shift Register Block Bypass Used for DDR/DDRX Modes From paired PIO ( x4 shift modes) To paired PIO (x4 shift modes) OPOS0 (Can act as OPOS2 when paired) Shift x2 / x4 Output OPOS1 (Can act as OPOS3 when paired) LCLKOUT HCLKOUT POS Update NEG Update From paired PIO ( x4 shift modes) To paired PIO (x4 shift modes) TSDDR/DDRX ODDR/DDR/ X2/X4 Bypass Used for DDR/DDRX Modes ONEG0 (Can act as ONEG2 when paired) ONEG1 (Can act as ONEG3 when paired) 2-21 Lattice Semiconductor Tristate Register Block Architecture LatticeSC/M Family Data Sheet The tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of three registers for DDR and shift register operation. The output signal tri-state control signal (TO) can be derived directly from one of the inputs (bypass mode), the SDR shift register, the DDR registers or the data associated with the buffer (for open drain emulation). Figure 2-24 shows the diagram of the Tristate Register Block. Tristate SDR Register/Latch Block The SDR register operates on the positive edge of the high-speed clock. In it has a variety of programmable options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control MUX. The GSR input is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on a PIO basis. Tristate DDR/Shift Register Block The DDR/Shift block is shared with the output block allowing DDR support using the high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing low–speed parallel data from the FPGA fabric to provide a high-speed tri-state control stream. There is a special mode for DDR-II memory interfaces where the termination is controlled by the output tristate signal. During WRITE cycle when the FPGA is driving the lines, the parallel terminations are turned off. During READ cycle when the FPGA is receiving data, the parallel terminations are turned on. Figure 2-24. Tristate Register Block1 TD VCC GND From Routing From Control MUX OPOS1 ONEG1 LCLKOUT HCLKOUT DDR/Shift Register Block2 • DDR • DDR + half clock TO (To PURESPEED I/O Buffer) Notes: 1. CE, Update, Set and Reset not shown for clarity. 2. DDR/Shift Register Block shared with output register block. From Output I/O Architecture Rules Table 2-6 shows the PIO usage for x1, x2, x4 gearing. The checkmarks in the columns show the specific PIOs that are used for each gearing mode. When using x2 or x4 gearing, any PIO which is not used for gearing can still be used as an output. 2-22 Lattice Semiconductor Table 2-6. Input/Output/Tristate Gearing Resource Rules Input/Output Logic PIO A B C D x1 ✓ ✓ ✓ ✓ x2 ✓ ✓ x4 ✓ No I/O Logic Architecture LatticeSC/M Family Data Sheet Tri-State/Bidi x1 ✓ ✓ ✓ ✓ x2/x4 N/A N/A N/A N/A No I/O Logic No I/O Logic No I/O Logic No I/O Logic Note: Pin can still be used without I/O logic. Control Logic Block The control logic block allows the modification of control signals selected by the routing before they are used in the PIO. It can optionally invert all signals passing through it except the Global Set/Reset. Global Set/Reset can be enabled or disabled. It can route either the edge clock or the clock to the high-speed clock nets. The clock provided to the PIO by routing is used as the slow-speed clocks. In addition this block contains delays that can be inserted in the clock nets to enable Lattice’s unique cycle boosting capability. Update Block The update block is used to generate the POS update and NEG update signals used by the DDR/Shift register blocks within the PIO. Note the update block is only required in shift modes. This is required in order to do the high speed to low speed handoff. One of these update signals is also selected and output from the PIC as the signal UPDATE. It consists of a shift chain that operates off either the high-speed input or output clock. The values of each register in the chain are set or reset depending on the desired mode of operation. The set/reset signal is generated from either the edge reset ELSR or the local reset LSR. These signals are optionally inverted by the Control Logic Block and provided to the update block as ELSRUP and LSRUP. The Lattice design tools automatically configure and connect the update block when one of the DDR or shift register primitives is used. Figure 2-25. Update Block ÷1/2/4 HCLKUP ESLRUP LSRUP POS Update NEG Update UPDATE LCLKUP PURESPEED I/O Buffer Each I/O is associated with a flexible buffer referred to as PURESPEED I/O buffer. These buffers are arranged around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL. The availability of programmable on-chip termination for both input and output use, further enhances the utility of these buffers. 2-23 Lattice Semiconductor PURESPEED I/O Buffer Banks Architecture LatticeSC/M Family Data Sheet LatticeSC devices have seven PURESPEED I/O buffer banks; each is capable of supporting multiple I/O standards. Each PURESPEED I/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allowing each bank to be completely independent from each other. Figure 2-26 shows the seven banks and their associated supplies. Table 2-7 lists the maximum number of I/Os per bank for the whole LatticeSC family. In the LatticeSC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI33 and PCIX33) are powered using VCCIO. In addition to the bank VCCIO supplies, the LatticeSC devices have a VCC core logic power supply, and a VCCAUX supply that power all differential and referenced buffers. VCCAUX also powers a predriver of single-ended output buffers to enhance buffer performance. Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the referenced input buffers. In the LatticeSC devices any I/O pin in a bank can be configured to be a dedicated reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages. Differential drivers have user selectable internal or external bias. External bias is brought in by the VREF1 pin in the bank. External bias for differential buffers is needed for applications that requires tighter than standard output common mode range. Since a bank can have only one external bias circuit for differential drivers, LVDS and RSDS differential outputs can be mixed in a bank but not with HYPT (HyperTransport). If a differential driver is configured in a bank, one pin in that bank becomes a DIFFR pin. This DIFFR pin must be connected to ground via an external 1K +/-1% ohm resistor. Note that differential drivers are not supported in banks 1, 4 and 5. In addition, there are dedicated Terminating Supply (VTT) pins to be used as terminating voltage for one of the two ways to perform parallel terminations. These VTT pins are available in banks 2-7, these pins are not available in some packages. When VTT termination is not required, or used to provide the common mode termination voltage (VCMT), these pins can be left unconnected on the device. If the internal or external VCMT function for differential input termination is used, the VTT pins should be unconnected and allowed to float. There are further restrictions on the use of VTT pins, for additional details refer to technical information at the end of this data sheet. 2-24 Lattice Semiconductor Figure 2-26. LatticeSC Banks VREF2[1] VREF1[1] VCCIO1 GND Architecture LatticeSC/M Family Data Sheet SERDES SERDES Bank 1 VCCIO7 VREF1[7] VTT7 VREF2[7] GND VCCIO2 VREF1[2] VTT2 VREF2[2] GND Bank 2 VTT6 VREF2[6] GND Bank 6 VCCIO6 VREF1[6] Bank 7 VCCIO3 VREF1[3] VTT[3] VREF2[3] GND Bank 3 Bank 4 Bank 5 VCCIO5 VREF1[5] VTT5 VREF2[5] VCCIO4 VREF1[4] VTT4 VREF2[4] GND Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family Device Bank1 Bank2 Bank3 Bank4 Bank5 Bank6 Bank7 LFSC/M15 104 28 60 72 72 60 28 LFSC/M25 80 36 84 100 100 84 36 LFSC/M40 136 60 96 124 124 96 60 LFSC/M80 80 96 132 184 184 132 96 LFSC/M115 136 136 156 208 208 156 136 Note: Not all the I/Os of the Banks are available in all the packages The LatticeSC devices contain three types of PURESPEED I/O buffers: 1. Left and Right Sides (Banks 2, 3, 6 and 7) These buffers can support LVCMOS standards up to 2.5V. A differential output driver (for LVDS, RSDS, and HYPT) is provided on all primary PIO pairs (A and B) and differential receivers are available on all pairs. Complimentary drivers are available. Adaptive input logic is available on PIOs A or C. 2. Top Side (Bank 1) These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential receivers are provided on all PIO pairs but differential drivers for LVDS, RSDS, and HYPT are not available. Adaptive input logic is not available on this side. Complimentary output drivers are available. 2-25 GND Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet 3. Bottom Side (Banks 4 and 5) These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential receivers are provided on all PIO pairs but true HLVDS, RSDS, and HYPT differential drivers are not available. Adaptive input logic is available on PIOs A or C. Table 2-8 lists the standards supported by each side. Table 2-8. I/O Standards Supported by Different Banks Description I/O Buffer Type Output Standards Supported Top Side Banks 1 Single-ended, Differential Receiver LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II SSTL33_ I, II HSTL15_I, II, III1, IV1 HSTL18_I, II,III1, IV1 SSTL18D_I, II SSTL25D_I, II SSTL33D_I, II HSTL15D_I, II HSTL18D_I, II PCI33 PCIX15 PCIX33 AGP1X33 AGP2X33 MLVDS/BLVDS GTL2, GTL+2 Single-ended, Differential Single-ended, Differential LVDS/MLVDS/BLVDS/ LVPECL No Right Side Banks 2-3 Bottom Side Banks 4-5 Left Side Banks 6-7 Single-ended, Differential Receiver and Driver LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II HSTL15_I,III HSTL18_I,II,III PCIX15 SSTL18D_I, II SSTL25D_I, II HSTL15D_I, II HSTL18D_I, II LVDS/RSDS/HYPT Mini-LVDS MLVDS/BLVDS GTL2, GTL+2 Single-ended, Differen- Single-ended, tial Receiver and Driver Differential Receiver LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II HSTL15_I,III HSTL18_I,II,III PCIX15 SSTL18D_I, II SSTL25D_I, II HSTL15D_I, II HSTL18D_I, II LVDS/RSDS/HYPT Mini-LVDS MLVDS/BLVDS GTL2, GTL+2 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18_I, II SSTL25_ I, II SSTL33_ I, II HSTL15_I, II, III1, IV1 HSTL18_I, II,III1, IV1 SSTL18D_I, II SSTL25D_I, II SSTL33D_I, II HSTL15D_I, II HSTL18D_I, II PCI33 PCIX15 PCIX33 AGP1X33 AGP2X33 MLVDS/BLVDS GTL2, GTL+2 Single-ended, Differential Single-ended, Differential LVDS/MLVDS/BLVDS/ LVPECL Yes Input Standards Supported Clock Inputs Differential Output Support via Emulation AIL Support Single-ended, Differential Single-ended, Differential MLVDS/BLVDS/ LVPECL Yes Single-ended, Differential Single-ended, Differential MLVDS/BLVDS/ LVPECL Yes 1. Input only. 2. Input only. Outputs supported by bussing multiple outputs together. Supported Standards The LatticeSC PURESPEED I/O buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP-2X33. Differential standards supported include LVDS, RSDS, BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. Tables 12 and 13 show the I/O standards (together with their supply and reference voltages) supported by the LatticeSC devices. The tables also provide the available internal termination schemes. For further information on utilizing the PURESPEED I/O buffer to support a variety of standards please see details of additional technical documentation at the end of this data sheet. 2-26 Lattice Semiconductor Table 2-9. Supported Input Standards Input Standard Single Ended Interfaces LVTTL333 LVCMOS 33, 25, 18, 15, 12 PCI33, PCIX33, AGP1X333 PCIX15 AGP2X33 HSTL18_I, II HSTL18_III, IV HSTL15_I, II HSTL15_III, IV SSTL33_I, II SSTL25_I, II SSTL18_I, II GTL+, GTL Differential Interfaces SSTL18D_I, II SSTL25D_I, II SSTL33D_I, II HSTL15D_I, II HSTL18D_I, II LVDS Mini-LVDS BLVDS25 MLVDS25 HYPT (Hyper Transport) RSDS LVPECL33 — — — — — — — — — — — — 1.82 2.52 3.3 1.5 2 3 Architecture LatticeSC/M Family Data Sheet VREF (Nom.) — — — 0.75 1.32 0.9 1.08 0.75 0.9 1.5 1.25 0.9 1.0 / 0.8 VCCIO1 (Nom.) 3.3 3.3 1.5 — 1.8 2 2 On-chip Termination None None None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None / VCCIO: 50 None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None / VCCIO: 50 None None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None / VCCIO: 50 None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None / Diff: 120, 150, 220, 420/ Diff to VCMT: 120, 150, 220, 420 / VCCIO / 2: 50, 60/ VTT: 60, 75, 120, 210 None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 None / Diff: 120, 150 / Diff to VCMT: 120, 150 None None None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 None / Diff: 120, 150, 220, 240/ Diff to VCMT: 120, 150, 220, 240 3.3/2.5/1.8/1.5/1.2 None 1.82 1.5 2 1.52 3.3 2.52 1.82 1.5 / 1.22 1.82 — — — — — — ≤2.5 1. When not specified VCCIO can be set anywhere in the valid operating range. 2. VCCIO needed for on-chip termination to VCCIO/2 or VCCIO only. VCCIO is not specified for off-chip termination or VTT termination. 3. All ratioed input buffers and dedicated pin input buffers include hysteresis with a typical value of 50mV. 2-27 Lattice Semiconductor Table 2-10. Supported Output Standards4 Output Standard Single-ended Interfaces LVTTL/D1 LVCMOS33/D1 LVCMOS25/D LVCMOS15/D PCIX15 PCI33, PCIX33, AGP1X33, AGP2X33 HSTL18_I HSTL18_II HSTL15_I HSTL15_II SSTL33_I SSTL33_II SSTL25_I SSTL25_II SSTL18_ I SSTL18_II Differential Interfaces SSTL18D_I SSTL25D_I SSTL18D_II, SSTL25D_II SSTL33D_I, II HSTL15D_I, HSTL18D_I HST15D_II, HSTL18D_II LVDS Mini-LVDS BLVDS25 MLVDS25 LVPECL33 RSDS 1. 2. 3. 4. 3 1, 2 Architecture LatticeSC/M Family Data Sheet Drive 8mA, 16mA, 24mA 8mA, 16mA, 24mA 4mA, 8mA, 12mA, 16mA, 4mA, 8mA, 12mA, 16mA, 4mA, 8mA, 12mA, 16mA, 2mA, 4mA, 8mA, 12mA N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A VCCIO (Nom) 3.3 3.3 2.5 1.8 1.5 1.2 1.5 3.3 1.8 1.8 1.5 1.5 3.3 3.3 2.5 2.5 1.8 1.8 None. None On-chip Output Termination None, series: 25, 33, 50, 100 None, series: 25, 33, 50, 100 None, series: 25, 33, 50, 100 None, series: 25, 33, 50, 100 None None None, series: 50 None, series: 25, series + parallel to VCCIO/2: 25 + 60 None, series: 50 None, series: 25, series + parallel to VCCIO/2: 25 + 60 None None None, series: 50 None, series: 33, series + parallel to VCCIO/2: 33+ 60 None, series: 33 None, series: 33, series + parallel to VCCIO/2: 33+ 60 None, series: 33 None, series: 50 None, series: 33, series + parallel to VCCIO/2: 33+ 60 None None, series: 50 None, series: 25, series + parallel to VCCIO/2: 25 + 60 None None None None None None None LVCMOS18/D1, 2 1, 2 LVCMOS12/D1, 2 N/A N/A N/A N/A N/A N/A 2mA, 3.5mA, 4mA, 6mA 3.5mA, 4mA, 6mA N/A N/A N/A 3.5mA, 4mA, 6mA 2mA, 3.5mA, 4mA, 6mA 1.8 2.5 1.2/2.5/3.3 3.3 1.5/1.8 1.5/1.8 N/A N/A N/A N/A 3.3 N/A N/A HYPT (Hyper Transport) D refers to open drain capability. User can select either drive current or driver impedances but not both. Emulated with external resistors. No GTL or GTL+ support. 2-28 Lattice Semiconductor PCI Clamp Architecture LatticeSC/M Family Data Sheet A programmable PCI clamp is available on the top and bottom banks of the device. The PCI clamp can be turned “ON” or “OFF” on each pin independently. The PCI clamp is used when implementing a 3.3V PCI interface. The PCI Specification, Revision 2.2 requires the use of clamping diodes for 3.3V operation. For more information on the PCI interface, please refer to the PCI Specification, Revision 2.2. Programmable Slew Rate Control All output and bidirectional buffers have an optional programmable output slew rate control that can be configured for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling edges. Programmable Termination Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both. The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and hence improving performance. Utilizing this feature also has the benefit of reducing the number of discrete components required on the circuit board. The termination schemes can be split into two categories single-ended and differential. Single Ended Termination Single Ended Outputs: The SC devices support a number of different terminations for single ended outputs: • • • • Series Parallel to VCCIO or GND Parallel to VCCIO/2 Parallel to VCCIO/2 combined with series Figure 2-27 shows the single ended output schemes that are supported. The nominal values of the termination resistors are shown in Table 2-10. 2-29 Lattice Semiconductor Figure 2-27. Output Termination Schemes Termination Type Series termination (controlled output impedance) Architecture LatticeSC/M Family Data Sheet Discrete Off-Chip Solution Zo Zo ON-chip OFF-chip Lattice On-Chip Solution Zo Zo ON-chip OFF-chip VCCIO or GND VCCIO or GND Zo Parallel termination to VCCIO, or parallel driving end Zo Zo ON-chip OFF-chip Zo ON-chip OFF-chip VCCIO VCCIO/2 Zo 2Zo Zo Zo 2Zo ON-chip OFF-chip GND ON-chip VCCIO/2 OFF-chip VCCIO/2 Zo Rs Zo ON-chip OFF-chip ON-chip OFF-chip Zo Parallel termination to VCCIO/2 driving end Combined series + parallel termination to VCCIO/2 at driving end (only series termination moved on-chip) Rs Zo VCCIO/2 VCCIO 2Zo Rs Combined series + parallel to VCCIO/2 driving end ON-chip Rs Zo Zo Zo 2Zo OFF-chip GND ON-chip OFF-chip 2-30 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet Single Ended Inputs: The SC devices support a number of different termination schemes for single ended inputs: • Parallel to VCCIO or GND • Parallel to VCCIO/2 • Parallel to VTT Figure 2-28 shows the single ended input schemes that are supported. The nominal values of the termination resistors are shown in Table 2-9. Figure 2-28. Input Termination Schemes Termination Type Discrete Off-Chip Solution VCCIO or GND Lattice On-Chip Solution VCCIO or GND Zo Zo Parallel termination to to VCCIO, or parallel to GND receiving end Zo Zo OFF-chip ON-chip OFF-chip ON-chip VCCIO2 2Zo Zo VCCIO Parallel termination to VCCIO/2 receiving end Zo 2Zo GND Zo OFF-chip ON-chip OFF-chip ON-chip VTT Zo VTT Zo Zo Parallel termination to VTT at receiving end Zo OFF-chip ON-chip OFF-chip ON-chip In many situations designers can chose whether to use Thevenin or parallel to VTT termination. The Thevenin approach has the benefit of not requiring a termination voltage to be applied to the device. The parallel to VTT approach consumes less power. VTT Termination Resources Each I/O bank, except bank 1, has a number of VTT pins that must be connected if VTT is used. Note VTT pins can sink or source current and the power supply they are connected to must be able to handle the relatively high currents associated with the termination circuits. Note: VTT is not available in all package styles. On-chip parallel termination to VTT is supported at the receiving end only. On-chip parallel output termination to VTT is not supported. The VTT internal bus is also connected to the internal VCMT node. Thus in one bank designers can implement either VTT termination or VCMT termination for differential inputs. DDRII/RLDRAMII Termination Support The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination to VTT be turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required circuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet. 2-31 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet Differential Input Termination The LatticeSC device allows two types of differential termination. The first is a single resistor across the differential inputs. The second is a center-tapped system where each input is terminated to the on-chip termination bus VCMT. The VCMT bus is DC-coupled through an internal capacitor to ground. Figure 2-29 shows the differential termination schemes and Table 2-9 shows the nominal values of the termination resistors. Figure 2-29. Differential Termination Scheme Termination Type Discrete Off-Chip Solution Lattice On-Chip Solution Zo 2Zo Zo Differential termination + Zo 2Zo + - Zo OFF-chip ON-chip OFF-chip ON-chip Zo Zo Zo Zo Differential and common mode termination GND Zo Zo OFF-chip + Zo ON-chip OFF-chip VCMT Zo GND + - ON-chip Calibration There are two calibration sources that are associated with the termination scheme used in the LatticeSC devices: • DIFFR – This pin occurs in each bank that supports differential drivers and must be connected through a 1K+/-1% resistor to ground if differential outputs are used. Note that differential drivers are not supported in banks 1, 4 and 5. • XRES – There is one of these pins per device. It is used for several functions including calibrating on-chip termination. This pin should always be connected through a 1K+/-1% resistor to ground. The LatticeSC devices support two modes of calibration: • Continuous – In this mode the SC devices continually calibrate the termination resistances. Calibration happens several times a second. Using this mode ensures that termination resistances remain calibrated as the silicon junction temperature changes. • User Request – In this mode the calibration circuit operates continuously. However, the termination resistor values are only updated on the assertion of the calibration_update signal available to the core logic. For more information on calibration, refer to the details of additional technical documentation at the end of this data sheet. Hot Socketing The LatticeSC devices have been carefully designed to ensure predictable behavior during power-up and powerdown. To ensure proper power sequencing, care must be taken during power-up and power-down as described below. During power-up and power-down sequences, the I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within specified limits, 2-32 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many multiple power supply and hot-swap applications. The maximum current during hot socketing is 4mA. See Hot Socketing Specifications in Chapter 3 of this data sheet. Power-Up Requirements To prevent high power supply and input pin currents, each VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies must have a monotonic ramp up time of 75 ms or less to reach its minimum operating voltage. Apart from VCC and VCC12, which have an additional requirement, and VCCIO and VCCAUX, which also have an additional requirement, the VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies can ramp up in any order, with no restriction on the time between them. However, the ramp time for each must be 75 ms or less. Configuration of the device will not proceed until the last power supply has reached its minimum operating voltage. Additional Requirement for VCC and VCC12: VCC12 must always be higher than VCC. This condition must be maintained at ALL times, including during powerup and power-down. Note that for 1.2V only operation, it is advisable to source both of these supplies from the same power supply. Additional Requirement for VCCIO and VCCAUX: If any VCCIOs are 1.2/1.5/1.8V, then VCCAUX MUST be applied before them. If any VCCIO is 1.2/1.5/1.8V and is powered up before VCCAUX, then when VCCAUX is powered up, it may drag VCCIO up with it as it crosses through the VCCIO value. (Note: If the VCCIO supply is capable of sinking current, as well as the more usual sourcing capability, this behavior is eliminated. However, the amount of current that the supply needs to sink is unknown and is likely to be in the hundreds of milliamps range). Power-Down Requirements To prevent high power supply and input pin currents, power must be removed monotonically from either VCC or VCCAUX (and must reach the power-down trip point of 0.5V for VCC, 0.95V for VCCAUX) before power is removed monotonically from VCC12, any of the VCCIOs, or VCCJ. Note that VCC12 can be removed at the same time as VCC, but it cannot be removed earlier. In many applications, VCC and VCC12 will be sourced from the same power supply and so will be removed together. For systems where disturbance of the user pins is a don't care condition, the power supplies can be removed in any order as long as they power down monotonically within 200ms of each other. Additionally, if any banks have VCCIO=3.3V nominal (potentially banks 1, 4, 5) then VCCIO for those banks must not be lower than VCCAUX during power-down. The normal variation in ramp-up times of power supplies and voltage regulators is not a concern here. Note: The SERDES power supplies are NOT included in these requirements and have no specific sequencing requirements. However, when using the SERDES with VDDIB or VDDOB that is greater than 1.2V (1.5V nominal for example), the SERDES should not be left in a steady state condition with the 1.5V power applied and the 1.2V power not applied. Both the 1.2V and 1.5V power should be applied to the SERDES at nominally the same time. The normal variation in the ramp-up times of power supplies and voltage regulators is not a concern here. SERDES Power Supply Sequencing Requirements When using the SERDES with 1.5V VDDIB or VDDOB supplies, the SERDES should not be left in a steady state condition with the 1.5V power applied and the 1.2V power not applied. Both the 1.2V and the 1.5V power should be applied to the SERDES at nominally the same time. The normal variation in ramp-up times of power supples and voltage regulators is not a concern. Additional Requirement for SERDES Power Supply All VCC12 pins need to be connected on all devices independent of functionality used on the device. This analog supply is used by both the RX and TX portions of the SERDES and is used to control the core SERDES logic regardless of the SERDES being used in the design. VDDIB and VDDOB are used as supplies for the terminations on the CML input and output buffers. If a particular channel is not used, these can be UNCONNECTED (floating). 2-33 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet VDDAX25 needs to be connected independent of the use of the SERDES. This supply is used to control the SERDES CML I/O regardless of the SERDES being used in the design. Supported Source Synchronous Interfaces The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify the implementation of Source Synchronous interfaces. Table 2-11 lists Source Synchronous and DDR/QDR standards supported in the LatticeSC. For additional detail refer to technical information at the end of the data sheet. Table 2-11. Source Synchronous Standards Table1 Source Synchronous Standard RapidIO HyperTransport2 SPI4.2 (POS-PHY4)/NPSI SFI4/XSBI XGMII CSIX QDRII/QDRII+ memory interface DDR memory interface DDRII memory interface RLDRAM memory interface Clocking DDR DDR DDR DDR SDR DDR SDR DDR DDR DDR DDR Speeds (MHz) 500 800 500 334 667 156.25 250 300 240 333 400 Data Rate (Mbps) 1000 1600 1000 667 312 250 600 480 667 800 1. Memory width is dependent on the system design and limited by the number of I/Os in the device. 2. Tested using non-coupled, six-inch traces fed directly into an edge clock resource. flexiPCS™ (Physical Coding Sublayer Block) flexiPCS Functionality The LatticeSC family combines a high-performance FPGA fabric, high-performance I/Os and large embedded RAM in a single industry leading architecture. LatticeSC devices also feature up to 32 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The flexiPCS logic can be configured to support numerous industry standard high-speed data transfer protocols. Each channel of flexiPCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial data transfers at data rates up to 3.8 Gbps. The PCS logic in each channel can be configured to support an array of popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X specification), 1.02 or 2.04 Gbps Fibre Channel, PCI-Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface. Protocols requiring data rates above 3.8 Gbps can be accommodated by dedicating either one pair or all four channels in one flexiPCS quad block to one data link. One quad can support full-duplex serial data transfers at data rates up to 15.2 Gbps. A single flexiPCS quad can be configured to support 10Gb Ethernet (with a fully compliant XAUI interface), 10Gb Fibre Channel, and x4 PCI-Express and 4x RapidIO. The flexiPCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic which can also be geared to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Each SERDES pin can be DC coupled independently and can allow for both high-speed and low-speed operation down to DC rates on the same SERDES pin, as required by some Serial Digital Video applications. The ispLEVER design tools from Lattice support all modes of the flexiPCS. Most modes are dedicated to applications associated with a specific industry standard data protocol. Other more general purpose modes allow a user to 2-34 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet define their own operation. With ispLEVER, the user can define the mode for each quad in a design. Nine modes are currently supported by the ispLEVER design flow: • • • • • • • • • 8-bit SERDES Only 10-bit SERDES Only SONET (STS-12/STS-48) Gigabit Ethernet Fibre Channel XAUI Serial RapidIO PCI-Express Generic 8b10b flexiPCS Quad The flexiPCS logic is arranged in quads containing logic for four independent full-duplex data channels. Each device in the LatticeSC family has up to eight quads of flexiPCS logic. The LatticeSC Family Selection Guide table on the first page of this data sheet contains the number of flexiPCS channels present on the chip. Note that in some packages (particularly lower pin count packages), not all channels from all quads on a given device may be bonded to package pins. Each quad supports up to four channels of full-duplex data and can be programmed into any one of several protocol based modes. Each quad requires its own reference clock which can be sourced externally or from the FPGA logic. The user can utilize between one and four channels in a quad, depending on the application. Figure 2-30 shows an example of four flexiPCS quads in a LatticeSC device. Quads are labeled according to the address of their software controlled registers. Figure 2-30. LatticeSC flexiPCS flexiPCS Quad 360 High Speed Serial Data flexiPCS Quad 361 High Speed Serial Data flexiPCS Quad 3E1 High Speed Serial Data flexiPCS Quad 3E0 High Speed Serial Data SERDES Interface Channel 0 PCS Logic Channel 1 PCS Logic Channel 2 PCS Logic Channel 3 PCS Logic Channel 0 PCS Logic SERDES Interface Channel 1 PCS Logic Channel 2 PCS Logic Channel 3 PCS Logic FPGA Logic I/Os Channel 3 PCS Logic SERDES Interface Channel 2 PCS Logic Channel 1 PCS Logic Channel 0 PCS Logic SERDES Interface Channel 3 PCS Logic Channel 2 PCS Logic Channel 1 PCS Logic Channel 0 PCS Logic F PGA Logic I/Os FPGA Logic flexiPCS Quad 360 PCS/FPGA Interface flexiPCS Quad 361 PCS/FPGA Interface flexiPCS Quad 3E1 PCS/FPGA Interface flexiPCS Quad 3E0 PCS/FPGA Interface F PGA Logic I/Os FPGA Logic I/Os 2-35 Lattice Semiconductor Architecture LatticeSC/M Family Data Sheet Since each quad has its own reference clock, different quads can support different standards on the same chip. This feature makes the LatticeSC family of devices ideal for bridging between different standards. flexiPCS quads are not dedicated solely to industry standard protocols. Each quad (and each channel within a quad) can be programmed for many user defined data manipulation modes. For example, modes governing userdefined word alignment and multi-channel alignment can be programmed for non-standard protocol applications. For more information on the functions and use of the flexiPCS, refer to the LatticeSC flexiPCS Data Sheet. System Bus Each LatticeSC device connects the FPGA elements with a standardized bus framework referred to as a System Bus. Multiple bus masters optimize system performance by sharing resources between different bus masters such as the MPI and configuration logic. The wide data bus configuration of 32 bits with 4-bit parity supports high-bandwidth, data intensive applications. There are two types of interfaces on the System Bus, master and slave. A master interface has the ability to perform actions on the bus, such as writes and reads to and from a specific address. A slave interface responds to the actions of a master by accepting data and address on a write and providing data on a read. The System Bus has a memory map which describes each of the slave peripherals that is connected on the bus. Using the addresses listed in the memory map, a master interface can access each of the slave peripherals on the System Bus. Any and all peripherals on the System Bus can be used at the same time. Table 2-12 list all of the available user peripherals on the System Bus after device power-up. Table 2-12. System Bus User Peripherals Peripheral Micro Processor Interface User Master Interface User Slave Interface Serial Management Interface (PLL, DLL, User Logic) Physical Coding Sublayer Direct FPGA Access Name MPI UMI USI SMI PCS DFA Interface Type Master Master Slave Slave Slave Slave The peripherals listed in Table 2-12 can be added when the System Bus module is created using Module IP/Manager (ispLEVER Module/IP Manager). Figure 2-31 also lists the existing peripherals on the System Bus. The gray boxes are available only during configuration. Refer to Lattice technical note TN1080, LatticeSC sysCONFIG Usage Guide, for configuration options. The Status and Config box refers to internal System Bus registers. This document presents all the interfaces listed in Table 2-12 in detail to help the user utilize the desired functions of the System Bus. 2-36 Lattice Semiconductor Figure 2-31. LatticeSC System Bus Interfaces DFA (Direct Access from MPI) SMI (PLL, DLL, USER LOGIC) CONFIG (MASTER) Architecture LatticeSC/M Family Data Sheet STATUS and CONFIG (SYS REG) USI (SLAVE) System Bus MPI (MASTER) PCS (LEFT, RIGHT and INTER-QUAD) (SLAVE) EBR INIT (WRITE) UMI (MASTER) Several interfaces exist between the System Bus and other FPGA elements. The MPI interface acts as a bridge between the external microprocessor bus and System Bus. The MPI may work in an independent clock domain from the System Bus if the System Bus clock is not sourced from the external microprocessor clock. Pipelined operation allows high-speed memory interface to the EBR and peripheral access without the requirement for additional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of the nature of the transfers. Details for the majority of the peripherals can be found in the associated technical documentation, see details at the end of this data sheet. Additional details of the MPI are provided below. Microprocessor Interface (MPI) The LatticeSC family devices have a dedicated synchronous MPI function block. The MPI is programmable to operate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration and read-back of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. The control portion of the MPI is available following power-up of the FPGA if the mode pins specify MPI mode, even if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus can be 1-, 2-, or 4-bit. In configuration mode the data and parity bus width are related to the state of the M[0:3] mode pins. For post-configuration use, the MPI must be included in the configuration bit stream by using an MPI library element in your design from the ispLEVER primitive library, or by setting the bit of the MPI configuration control register prior to the start of configuration. The user can also enable and disable the parity bus through the configuration bit stream. These pads can be used as general I/O when they are not needed for MPI use. The MPI block also provides the capability to interface directly to the FPGA fabric with a databus after configuration.The bus protocol is still handled by the MPI block but the direct FPGA access allows high-speed block data transfers such as DMA transactions. Figure 2-32 shows one of the ways a PowerPC is connected to MPI. 2-37 Lattice Semiconductor Figure 2-32. PowerPCI and MPI Schematic PowerPC TSZ[0:1] RETRY TEA BURST 1, 2, 4 DP[0:m] 8, 16, 32 D[0:n] A[14:31] CLKOUT RD/WR TA BDIP IRQx TS D[0:n] PPC_A[14:31] MPI_CLK MPI_RW MPI_ACK MPI_BDIP MPI_IRQ MPI_STRB CS0 CS1 DP[0:m] DOUT CCLK Architecture LatticeSC/M Family Data Sheet LatticeSC FPGA MPI_TSZ[0:1] MPI_RTRY MPI_TEA MPI_BURST To DaisyChained Devices DONE INIT HDC LDC Bus Controller Configuration and Testing The following section describes the configuration and testing features of the LatticeSC family of devices. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeSC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can operate with LVCMOS33, 25 and 18 standards. For additional detail refer to technical information at the end of the data sheet. Device Configuration All LatticeSC devices contain three possible ports that can be used for device configuration. The serial port, which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial configuration. The MPI port supports 8-bit, 16-bit or 32-bit configuration. The serial port supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System Configuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for general purpose I/O. All I/Os for the sysCONFIG and MPI ports are in I/O bank #1. On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a configuration port is selected, that port is locked and another configuration port cannot be activated until the next re-initialization sequence. For additional detail refer to technical information at the end of the data sheet. 2-38 Lattice Semiconductor Internal Logic Analyzer Capability (ispTRACY) Architecture LatticeSC/M Family Data Sheet All LatticeSC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile time. For additional detail refer to technical information at the end of the data sheet. Temperature Sensing Lattice provides a way to monitor the die temperature by using a temperature-sensing diode that is designed into every LatticeSC device. The difference in VBE of the diode at two different forward currents varies with temperature. This relationship is shown in Figure 2-33. The accuracy of the temperature-sensing diode is typically +/- 10°C. On packages that include PROBE_GND, the most accurate measurements will occur between the TEMP pin and the PROBE_GND pin. On packages that do not include PROBE_GND, measurements should be made between the TEMP pin and board ground. This temperature-sensing diode is designed to work with an external temperature sensor such as the Maxim 1617A. The Maxim 1617A is configured to measure difference in VBE (of the temperature-sensing diode) at 10µA and at 100µA. This difference in VBE voltage varies with temperature at approximately 1.64 mV/°C. A typical device with a 85°C junction temperature will measure approximately 593mV. For additional detail refer to the temperaturesensing diode technical note, TN1115. Figure 2-33. Sensing Diode Typical Characteristics 0.88 0.80 0.75 0.70 Voltage 0.65 0.65 0.55 0.50 -50 -25 0 25 50 75 100 Junction Temperature (°C) 125 VBE difference increases with temperature 100μA 10μA Oscillator Every LatticeSC device has an internal CMOS oscillator, which is used as a master serial clock for configuration and is also available as a potential general purpose clock (MCK) for the FPGA core. There is a K divider (divide by 2/4/8/16/32/64/128) available with this oscillator to get lower MCK frequencies. This clock is available as a general purpose clock signal to the software routing tool. For additional detail refer to technical information at the end of the data sheet. 2-39 Lattice Semiconductor Density Shifting Architecture LatticeSC/M Family Data Sheet The LatticeSC family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. However, the exact details of the final resource utilization will impact the likely success in each case. 2-40 LatticeSC/M Family Data Sheet DC and Switching Characteristics June 2008 Data Sheet DS1004 Absolute Maximum Ratings Supply Voltage VCC, VCC12, VDDIB, VDDOB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.6V Supply Voltage VCCAUX, VDDAX25, VTT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V Supply Voltage VCCJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Supply Voltage VCCIO (Banks 1, 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Supply Voltage VCCIO (Banks 2, 3, 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V Input or I/O Tristate Voltage Applied (Banks 1, 4, 5) . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V Input or I/O Tristate Voltage Applied (Banks 2, 3, 6, 7) . . . . . . . . . . . . . . . . -0.5 to 2.75V Storage Temperature (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temperature Under Bias (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Notes: 1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with the Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Undershoot and overshoot of -2V to (VIHMAX +2) volts is permitted for a duration of H, H -> L) 30pF LVCMOS 1.8 = VCCIO/2 LVCMOS 1.5 = VCCIO/2 LVCMOS 1.2 = VCCIO/2 LVCMOS 2.5 I/O (Z -> H) LVCMOS 2.5 I/O (Z -> L) LVCMOS 2.5 I/O (H -> Z) LVCMOS 2.5 I/O (L -> Z) 30pF VCCIO/2 VCCIO/2 VOH - 0.15 VOL + 0.15 VT — — — — — VOL VOH VOL VOH Note: Output test conditions for all other interfaces are determined by the respective standards. 3-30 LatticeSC/M Family Data Sheet Pinout Information January 2008 Data Sheet DS1004 Signal Descriptions Signal Name General Purpose [Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top). [Row/Column Number] indicates the PIC row or the column of the device on which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify Row Number. When Edge is L (Left) or R (Right), only need to specify Column Number. P[Edge] [Row/Column Number*]_[A/B/C/D] I/O [A/B/C/D] indicates the PIO within the PIC to which the pad is connected. Some of these user programmable pins are shared with special function pins. These pin when not used as special purpose pins can be programmed as I/Os for user logic. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration. VREF1_x, VREF2_x NC Non-SERDES Power Supplies VCCIOx VCC12 1 I/O Description — — The reference supply pins for I/O bank x. Any I/O pin in a bank can be assigned as a reference supply pin, but software defaults use designated pin. No connect. NC pins should not be connected to any active signals, VCC or GND. VCCIO - The power supply pins for I/O bank x. Dedicated pins. 1.2V supply for configuration logic, PLLs and SERDES Rx, Tx and PLL. All VCC12 pins must be connected. As VCC12 supplies power for analog circuitry, VCC12 should be quiet and isolated from noisy digital board supplies. Termination voltage for bank x. When VTT termination is not required, or used to provide the common mode termination voltage (VCMT), these pins can be left unconnected on the device. VCMT function is not used in the bank. If the internal or external VCMT function for differential input termination is used, the VTT pins should be unconnected and allowed to float. GND - Ground. Dedicated pins. All grounds must be electrically connected at the board level. VCC - The power supply pins for core logic. Dedicated pins (1.2V/ 1.0V). VCCAUX - Auxiliary power supply pin - powers all differential and referenced input buffers. Dedicated pins (2.5V). VCCJ - The power supply pin for JTAG Test Access Port. VCC signal - Connected to internal VCC node. Can be used for feedback to control an external board power converter. Can be unconnected if not used. — — VTT_x — GND VCC VCCAUX VCCJ PROBE_VCC — — — — — © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 4-1 DS1004 Pinouts_01.8 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Signal Descriptions (Cont.) Signal Name PROBE_GND I/O — Description GND signal - Connected to internal VSS node. Can be used for feedback to control an external board power converter. Can be unconnected if not used. PLL feedback input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the PLL is located in: ULC (upper left), URC (upper right), LLC (lower left) and LRC (lower right). [T, C] indicates whether input is true or complement. [A, B] indicates PLL reference within the corner. DLL feedback input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the DLL is located in: ULC (upper left), URC (upper right), LLC (lower left) and LRC (lower right). [T/C] indicates whether input is true or complement. [C, D, E, F] indicates DLL reference within a corner. Note: E and F are only available on the lower corners. PLL reference clock input. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the PLL is located in: ULC (upper left corner), URC (upper right corner), LLC (lower left corner) and LRC (lower right corner). [T, C] indicates whether input is true or complement.[A, B] indicates PLL reference within the corner. DLL reference clock inputs. Pull-ups are enabled on input pins during configuration. [LOC] indicates the corner the DLL is located in: ULC (upper left corner), URC (upper right corner), LLC (lower left corner) and LRC (lower right corner). [T/C] indicates whether input is true or complement. [C, D, E, F] indicates DLL reference within a corner. Note: E and F are only available on the lower corners. PCKLxy_[0:3] can drive primary clocks, edge clocks, and CLKDIVs. PCLKxy_[4:7] can only drive edge clocks. General clock inputs. x indicates whether T (true) or C (complement). y indicates the I/O bank the clock is associated with. z indicates the clock number within a bank. I I Test Mode Select input, used to control the 1149.1 state machine. Test Clock input pin, used to clock the 1149.1 state machine. Test Data in pin, used to load data into device using 1149.1 state machine. After power-up, this TAP port can be activated for configuration by sending appropriate command. (Note: once a configuration port is selected it is locked. Another configuration port cannot be selected until the power-up sequence). Output pin -Test Data out pin used to shift data out of device using 1149.1. Mode pins used to specify configuration modes values latched on rising edge of INITN. Open Drain pin - Indicates the FPGA is ready to be configured. During configuration, a pull-up is enabled that will pull the I/O above 1.5V. Initiates configuration sequence when asserted low. This pin always has an active pull-up. Open Drain pin - Indicates that the configuration sequence is complete, and the startup sequence is in progress. Configuration Clock for configuring an FPGA in sysCONFIG mode. PLL and Clock Functions (Used as user-programmable I/O pins when not in use for PLL, DLL or clock pins.) [LOC]_PLL[T, C]_FB_[A/B] I [LOC]_DLL[T, C]_FB_[C, D, E, F] I [LOC]_PLL[T, C]_IN[A/B] I [LOC]_DLL[T, C]_IN[C, D, E, F] PCLKxy_z Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.) TMS TCK TDI I TDO O Configuration Pads (Dedicated pins. Used during sysCONFIG.) M[3:0] INITN PROGRAMN DONE CCLK I I/O I I/O I/O 4-2 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Signal Descriptions (Cont.) Signal Name RESETN I/O Description Reset. (Also sent to general routing). During configuration it resets the configuration state machine. After configuration this pin can perform the global set/reset (GSR) functions or can be used as a general input pin. O I MPI Interrupt request active low signal is controlled by system bus interrupt controller and may be sourced from any bus error or MPI configuration error. It can be connected to one of MPC860 IRQ pins. Tristates all I/O. High During Configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. For SPI modes, this pin is used to download the read command and initial read address into the Flash memory device on the falling edge of SCK. This pin will be connected to SI of the memory. If the SPI mode is used, the 8-bit instruction code 0x03 will be downloaded followed by a 24-bit starting address of 0x000000 or a non-zero stat address for partial reconfiguration. If the SPIX mode has been selected, the 8-bit instruction captured on D[7:0] at power-up will be shifted in and followed by a 32-bit starting address of 0x000000. Low During Configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete. LDCN/SCS O For SPI modes, this is an active low chip select for Flash memories. It will go active after INITN goes high but before SCK begins. During power up LDCN will be low. Once INITN goes high, LDCN will go high for 100ns-200ns after which time it will go back low and configuration can begin. During the 100ns-200ns period, the read instruction will be latched for SPIX mode. Serial data output that can drive the D0/DIN of daisy-chained slave devices. The data-stream from this output will propagate preamble bits of the bitstream to daisy-chained devices. Data out on DOUT changes on the rising edge of CCLK. During daisy-chaining configuration, QOUT is the serial data output that can drive the D0/DIN of daisy-chained slave devices that do not propagate preamble bits. Data out on QOUT changes on the rising edge of CCLK. During parallel-chaining configuration, active low CEON enables the cascaded slave device to receive bitstream data. RDN WRN I I Used in the asynchronous peripheral configuration mode. A low on RDN changes D[7:3] into status outputs. WRN and RDN should not be used simultaneously. If they are, the write strobe overrides. When the FPGA is selected, a low on the write strobe, WRN, loads the data on D[7:0] inputs into an internal data buffer. Used in the asynchronous peripheral, slave parallel and MPI modes. The FPGA is selected when CS0N is low and CS1 is high. During configuration, a pull-up is enabled on both except with MPI DMA access control. In master parallel mode, A[21:0] is an output and will address the configuration EPROMs up to 4 MB space. For MPI configuration mode, A[17:0] will be the MPI address MPI_ADDR[31:14], A[19:18] will be the transfer size and A[21:20] will be the burst mode and burst in process. CFGIRQN TSALLN Configuration Pads (User I/O if not used. Used during sysCONFIG.) HDC/SI O DOUT O QOUT/CEON O CS0N CS1 I A[21:0] I/O 4-3 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Signal Descriptions (Cont.) Signal Name I/O Description In parallel configuration modes, D[7:0] receives configuration data, and each pin is pull-up enabled. For slave serial mode, D0 is the data input. D[7:3] is the output internal status for peripheral mode when RDN is low. D[7:0] is also the first byte of MPI data pins. In MPI configuration mode, MPI selectable data bus width from 8 and 16-bit. Driven by a bus master in a write transaction. Driven by MPI in a read transaction. DP[m:0] I/O MPI selectable parity data bus width from 1, 2, and 3-bit DP[0] for D[7:0], DP[1] for D[15:8], and DP[2] for D[23:16]. During configuration in peripheral mode, high on BUSYN indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D[7] in asynchronous peripheral mode. During configuration in slave parallel mode, low on BUSYN inhibits the external host from sending new data. The output is used by slave parallel and master serial modes only for decompression. BUSYN/RCLK/SCK O During configuration in master parallel and master byte modes, RCLK is a read clock output signal to an external memory. The RCLK frequency is the same as CCLK when used with uncompressed bitstreams. RCLK will be 1/8 the frequency of CCLK when the bitstream is compressed. During configuration in SPI modes, SCK is generated by the device and connected to the CLK input of the FLASH memory. MPI Interface (Dedicated pin) MPI_IRQ_N MPI Interface (User I/O if MPI is not used.) MPI chip select pins, active low on MPI_CS0N while active high on MPI_CS1. Both have to be active during the whole transfer data phase. During transfer address phase, both can be inactive so that the decoding for them from address can be slow. If they are active during address phase, one cycle can be saved for sync read. This is the PowerPC bus clock. It can be a source of the clock for embedded system bus. If MPI_CLK is used as system bus clock, MPI will be set into sync mode by default. All of the operation on PowerPC side of MPI are synchronized to the rising edge of this clock. Driven by a bus master to indicate the data transfer size for the transaction. 01 for byte, 10 for half-word, and 00 for word. Driven high indicates that a read access is in progress. Driven low indicates that a write access is in process. Driven active low indicates that a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. Active low “Burst Data in Process” is driven by a PowerPC processor. Asserted indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. O MPI Interrupt request active low signal is controlled by system bus interrupt controller and may be sourced from any bus error or MPI configuration error. It can be connected to one of MPC860 IRQ pins. D[n:0] I/O MPI_CS0N MPI_CS1 I MPI_CLK I MPI_TSIZ[1:0] MPI_WR_N MPI_BURST I I I MPI_BDIP I 4-4 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Signal Descriptions (Cont.) Signal Name MPI_STRBN MPI_ADDR[31:14] MPI_DAT[n:0] MPI_PAR[m:0] MPI_TA MPI_TEA MPI_RETRY Multi-chip Alignment (User I/O if not used.) MCA_DONE_OUT MCA_DONE_IN MCA_CLK_P[1:2]_OUT MCA_CLK_P[1:2]_IN TEMP Miscellaneous Dedicated Pins XRES — External reference resistor between this pin and ground. The reference resistor is used to calibrate the programmable terminating resistors used in the I/Os. Dedicated pin. Value: 1K ± 1% ohm. Only used if a differential driver is used in a bank. This DIFFRx must be connected to ground via an external 1K ±1% ohm resistor for all banks that have a differential driver. High-speed input (positive) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. High-speed input (negative) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. High-speed output (positive) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. High-speed output (negative) channel x on left [L] or right [R] side of device. PCS quad is defined in the dual function name column of the Logic Signal Connection table. Ref clock input (positive), aux channel on left [L] or right [R] side of device. Ref clock input (negative), aux channel on left [L] or right [R] side of device. O I O I — Multi-chip alignment done output (to second MCA chip) Multi-chip alignment done input (from second MCA chip) Multi-chip alignment clock [1:2] output (sourced by MCA master chip) Multi-chip alignment clock [1:2] input (from MCA master chip Temperature sensing diode pin. Dedicated pin. Accuracy is typically +/- 10°C. I/O I I I/O I/O O O O Description Driven active low indicates the start of a transaction on the PowerPC bus. MPI will strobe the address bus at next rising edge of clock. Address bus driven by a PowerPC bus master. Only 18-bit width is needed. It has to be the least significant bit of the PowerPC 32-bit address A[31:14]. Selectable data bus width from 8, and 16-bit. Driven by a bus master in a write transaction. Driven by MPI in a read transaction. Selectable parity bus width from 1, 2, and 3-bit. MPI_DP[0] for MPI_D[7:0], MPI_DP[1] for MPI_D[15:8] and MPI_DP[2] for MPI_D[23:16]. Transfer acknowledge. Driven active low indicates that MPI received the data on the write cycle or returned data on the read cycle. Transfer Error Acknowledge. Driven active low indicates that MPI detects a bus error on the internal system bus for current transaction. Active low MPI Retry requests the MPC860 to relinquish the bus and retry the cycle. DIFFRx SERDES Block (Dedicated Pins) [A:D]_HDINPx_[L/R] — I [A:D]_HDINNx_[L/R] I [A:D]_HDOUTPx_[L/R] O [A:D]_HDOUTNx_[L/R] [A:D]_REFCLKP_[L/R] [A:D]_REFCLKN_[L/R] O I I 4-5 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Signal Descriptions (Cont.) Signal Name I/O Description Calibration resistor to be placed between this pin and either ground or RESPN_[ULC/URC]. RESPN_[ULC/URC] is available on select packages. If available, connection of calibration resistor between RESP_[ULC/URC] and RESPN_[ULC/URC] takes precedence over connection of calibration resistor between RESP_[ULC/URC] and ground. Note: only one per side of the device. Value: 4.02K ohm +/- 1% ohm. Available on selected packages. If available, calibration resistor should be placed between RESP_[ULC/URC] and RESPN_[ULC/URC] instead of between RESP_[ULC/URC] and ground. Note: only one per side of the device. Value: 4.02K ohm +/- 1% ohm. Input buffer power supply for channel x (1.2V/1.5V) on left [L] or right [R] side of device. Output buffer power supply for channel x (1.2V/1.5V) on left [L] or right [R] side of device. Auxiliary power for input and output termination (2.5V) on left [L] or right [R] side of device. RESP_[ULC/URC] — RESPN_[ULC/URC] — [A:D]_VDDIBx_[L/R] [A:D]_VDDOBx_[L/R] [A:D]_VDDAX25_[L/R] — — — 1. The ispLEVER software tools may specify VDDRX, VDDTX, VDDP and VCCL pins. These pins should be considered VCC12 pins. Note: Signals listed as Signal A / Signal B define the same physical pin that is used for different functions based on configuration mode. 4-6 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Pin Information Summary 256 fpBGA Pin Type Single Ended User I/O Differential Pair User I/O LVDS Output Pairs Configuration JTAG (excluding VCCJ) Dedicated Pins VCC VCC12 VCCAUX Bank 1 Bank 2 Bank 3 VCCIO Bank 4 Bank 5 Bank 6 Bank 7 Bank 2 Bank 3 VTT Bank 4 Bank 5 Bank 6 Bank 7 GND NC Bank 1 Bank 2 Bank 3 Single Ended User / Differential I/O per Bank Bank 4 Bank 5 Bank 6 Bank 7 Bank 2 LVDS Output Pairs Per Bank Bank 3 Bank 6 Bank 7 VCCJ SERDES (signal + power supply) Total Dedicated Muxes/MPI sysBus LFSC/M15 139 60 22 9 0 4 2 10 10 10 3 2 2 3 3 2 2 0 0 0 0 0 0 26 0 21/8 15/7 19/8 25/11 25/11 19/8 15/7 5 6 6 5 1 28 256 900 fpBGA LFSC/M15 300 141 44 11 55 4 4 46 35 36 18 14 15 15 15 15 16 2 3 3 3 3 2 177 102 63/30 26/13 43/20 50/22 49/23 43/20 26/13 7 15 15 7 1 60 900 LFSC/M25 378 182 60 11 55 4 4 46 35 36 18 14 15 15 15 15 16 2 3 3 3 3 2 177 24 63/30 30/15 62/29 66/32 65/32 62/29 30/15 9 21 21 9 1 60 900 1020 fcBGA LFSC/M25 476 235 60 11 55 4 4 40 36 32 10 8 10 10 10 10 8 2 3 3 3 3 2 134 92 68/32 34/17 84/42 84/41 88/44 84/42 34/17 9 21 21 9 1 108 1020 LFSC/M40 562 277 78 11 72 4 4 40 36 32 10 8 10 10 10 10 8 2 3 3 3 3 2 134 6 68/32 54/27 94/47 99/48 99/49 94/47 54/27 15 24 24 15 1 108 1152 4-7 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Pin Information Summary (Cont.) 1152 fcBGA Pin Type Single Ended User I/O Differential Pair User I/O LVDS Output Pairs Configuration JTAG (excluding VCCJ) Dedicated Pins VCC VCC12 VCCAUX Bank 1 Bank 2 Bank 3 VCCIO Bank 4 Bank 5 Bank 6 Bank 7 Bank 2 Bank 3 VTT Bank 4 Bank 5 Bank 6 Bank 7 GND NC Bank 1 Bank 2 Bank 3 Single Ended User / Differential I/O per Bank Bank 4 Bank 5 Bank 6 Bank 7 Bank 2 LVDS Output Pairs Per Bank Bank 3 Bank 6 Bank 7 VCCJ SERDES (signal + power supply) Total Dedicated Muxes/MPI sysBus LFSC/M40 604 302 78 11 72 4 4 44 52 38 10 9 12 12 12 12 9 3 3 3 3 3 3 130 62 80/40 60/30 96/48 106/53 106/53 96/48 60/30 15 24 24 15 1 108 1152 660 330 102 11 72 4 4 44 52 38 10 9 12 12 12 12 9 3 3 3 3 3 3 130 6 80/40 76/38 108/54 106/53 106/53 108/54 76/38 21 30 30 21 1 108 1152 660 330 102 11 72 4 4 44 52 38 10 9 12 12 12 12 9 3 3 3 3 3 3 130 6 80/40 76/38 108/54 106/53 106/53 108/54 76/38 21 30 30 21 1 108 1152 1704 fcBGA 904 452 114 11 72 4 4 76 88 52 10 12 14 14 14 14 12 4 4 5 5 4 4 184 52 80/40 96/48 132/66 184/92 184/92 132/66 96/48 24 33 33 24 1 212 1704 942 470 132 11 72 4 4 76 88 52 10 12 14 14 14 14 12 4 4 5 5 4 4 184 14 80/40 103/51 144/72 184/92 184/92 144/72 103/51 27 39 39 27 1 212 1704 LFSC/M80 LFSC/M115 LFSC/M80 LFSC/M115 4-8 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15 Logic Signal Connections: 256 fpBGA1,2 LFSC/M15 Ball Number E4 B1 C1 D2 F5 D1 E1 E2 E3 E5 E6 F2 F1 F3 G1 G4 H3 H2 H5 G5 H1 J1 J2 J3 H4 H6 J4 K5 J5 J6 K1 L1 L4 K4 L2 L3 M3 M2 M1 N1 P2 M5 Ball Function A_VDDAX25_L A_REFCLKP_L A_REFCLKN_L RESP_ULC RESETN DONE INITN M0 M1 M2 M3 PL15A PL15B PL17A PL17B PL18D PL22A PL22B PL22C PL22D PL23A PL23B PL24A PL24B PL24C PL24D PL26A PL26B PL26C PL26D PL28A PL28B PL28C PL28D PL31C PL35A PL35B PL35D PL37A PL37B PL41D PL43A VCCIO Bank 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 VREF2_6 DIFFR_6 PCLKT6_2 PCLKC6_2 VREF1_6 VREF1_7 DIFFR_7 PCLKT7_1 PCLKC7_1 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D VREF2_7 Dual Function 4-9 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15 Logic Signal Connections: 256 fpBGA1,2 (Cont.) LFSC/M15 Ball Number M4 P1 R1 R2 P3 R3 N4 T3 T2 N5 P5 R5 T4 T5 R6 T6 L5 P6 T7 M7 R8 T8 N7 N8 R9 T9 M8 M9 P8 P9 T10 R11 N9 N10 T11 R12 P11 M10 T12 P12 T13 T14 R15 Ball Function PL43B PL45A PL45B XRES TEMP PB3A PB3B PB3C PB3D PB5D PB8A PB8B PB9A PB9B PB12A PB12B PB13C PB15A PB15B PB15D PB16A PB16B PB17A PB17B PB20A PB20B PB21A PB21B PB24A PB24B PB28A PB28B PB31A PB31B PB32A PB32B PB35A PB35B PB36A PB36B PB37A PB37B PB37C VCCIO Bank 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_2 PCLKC4_2 PCLKT4_1 PCLKC4_1 PCLKT4_0 PCLKC4_0 VREF2_4 PCLKT5_0 PCLKC5_0 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_2 PCLKC5_2 PCLKT5_3 PCLKC5_3 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D VREF1_5 LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E Dual Function 4-10 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15 Logic Signal Connections: 256 fpBGA1,2 (Cont.) LFSC/M15 Ball Number N12 T15 R16 L12 M12 P16 N16 R14 P15 M13 N13 P14 M16 L16 M14 M15 K16 J16 H16 L13 L14 L15 K12 J13 K13 H15 F16 J11 J12 J15 J14 E16 D16 H11 H12 H13 H14 G12 G13 F8 F9 G16 F15 Ball Function PB39C PB40A PB40B PB43A PB43B PB44A PB44B PB47C PB48A PB48B PB49A PB49B PR45B PR45A PR43B PR43A PR41D PR37B PR37A PR35D PR35B PR35A PR31C PR28D PR28C PR28B PR28A PR26D PR26C PR26B PR26A PR24D PR24C PR24B PR24A PR23B PR23A PR22D PR22C PR22B PR22A PR18D PR17B VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 VREF2_2 URC_DLLC_IN_C/URC_DLLC_FB_D PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_1 PCLKT2_1 DIFFR_2 VREF1_2 VREF1_3 PCLKC3_2 PCLKT3_2 DIFFR_3 VREF2_3 VREF1_4 LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E PCLKT4_3 PCLKC4_3 Dual Function 4-11 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15 Logic Signal Connections: 256 fpBGA1,2 (Cont.) LFSC/M15 Ball Number F14 E15 E14 D9 C16 B15 B16 E13 C14 C15 A15 A14 B14 E12 D13 D12 E10 C11 D10 A13 B12 A12 C12 A11 B11 E9 E8 D8 A10 C10 E7 C9 A9 B9 A8 B8 C8 B7 C7 A7 B6 A6 C6 Ball Function PR17A PR15B PR15A VCCJ TDO TMS TCK TDI PROGRAMN CCLK PT43D PT43C PT41A PT39B PT39A PT37D PT37C PT37B PT37A PT36D PT36C PT35B PT35A PT33B PT33A PT32D PT32B PT28C PT27B PT27A PT21C A_VDDIB3_L A_HDINP3_L A_HDINN3_L A_HDOUTP3_L A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCCIO Bank 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCS 360 CH 2 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P PCS 360 CH 3 OUT N HDC/SI LDCN/SCS CS1 CS0N RDN WRN D7 D6 D5 D4 D3 D2 D1 D0 QOUT/CEON VREF2_1 DOUT BUSYN/RCLK/SCK PCLKC1_0 PCLKT1_0 VREF1_1 TDO Dual Function URC_DLLT_IN_C/URC_DLLT_FB_D URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B 4-12 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15 Logic Signal Connections: 256 fpBGA1,2 (Cont.) LFSC/M15 Ball Number C5 A5 B5 A4 B4 C4 B3 C3 A3 B2 A2 C2 A1 A16 B10 C13 D15 D3 E11 F13 G14 G2 G8 H10 J7 K15 K3 K9 M6 N11 N14 N2 P10 P4 R13 R7 G10 G7 G9 H7 H8 H9 J10 J8 Ball Function A_VDDIB1_L A_HDINP1_L A_HDINN1_L A_HDOUTP1_L A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L A_HDINN0_L A_HDINP0_L A_VDDIB0_L GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank PCS 360 CH 0 OUT P PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 1 OUT N Dual Function 4-13 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15 Logic Signal Connections: 256 fpBGA1,2 (Cont.) LFSC/M15 Ball Number J9 K8 F6 F11 L11 L6 K7 K10 F10 F7 T1 G11 K11 L10 L9 L7 L8 T16 G6 K6 B13 D11 D14 F12 G15 K14 N15 M11 P13 R10 N6 P7 R4 K2 N3 F4 G3 D4 D7 D5 D6 Ball Function VCC VCC VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCAUX VCCAUX GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND VCCAUX VCCAUX VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCC12 VCC12 VCC12 VCC12 VCCIO Bank Dual Function 1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). 2. The LatticeSC/M15 in a 256-pin package does not support an MPI interface. 4-14 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 LFSC/M15 Ball Number F7 B1 C1 D5 A2 E5 D4 H5 H6 G6 G5 F5 F6 F4 E4 D3 D2 J6 J5 E3 E2 K4 J4 F3 G3 K5 K6 F2 F1 E1 D1 K3 L3 L6 M6 J1 K1 L1 M1 P8 R8 N2 N1 R7 R6 Ball Function A_VDDAX25_L A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC VCC12 VCC12 RESETN TSALLN DONE INITN M0 M1 M2 M3 PL15A PL15B PL15C PL15D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL19A PL19B PL19C PL19D PL22A PL22B PL22C PL22D PL23A PL23B PL24A PL24B PL24C PL24D PL26A PL26B PL26C PL26D VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 VREF1_7 DIFFR_7 PCLKT7_1 PCLKC7_1 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B Dual Function Ball Function A_VDDAX25_L A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC VCC12 VCC12 RESETN TSALLN DONE INITN M0 M1 M2 M3 PL16A PL16B PL16C PL16D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL22A PL22B PL22C PL22D PL25A PL25B PL25C PL25D PL26A PL26B PL27A PL27B PL27C PL27D PL29A PL29B PL29C PL29D VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 VREF1_7 DIFFR_7 PCLKT7_1 PCLKC7_1 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B LFSC/M25 Dual Function 4-15 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number N3 P3 P4 P2 R2 T3 R3 P1 R1 R5 R4 T2 U2 T1 U1 V1 W1 V6 V2 W2 Y1 AA1 AB1 AC1 Y5 Y6 AD2 AE2 AB5 AC3 AD3 AF1 AG1 AB6 AC5 AF2 AG2 AC6 AC7 AE4 AG4 AD5 AF5 AH1 AJ1 Ball Function PL27A PL27B PL27C PL28A PL28B PL28C PL28D PL31A PL31B PL31C PL31D PL32A PL32B PL33A PL33B PL35A PL35B PL35D PL36A PL36B PL37A PL37B PL39A PL39B PL40A PL40B PL41A PL41B PL41D PL43A PL43B PL44A PL44B PL44C PL44D PL45A PL45B PL45C PL45D XRES VCC12 TEMP VCC12 PB3A PB3B VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A VREF2_6 DIFFR_6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 Dual Function Ball Function PL30A PL30B PL30C PL31A PL31B PL31C PL31D PL34A PL34B PL34C PL34D PL35A PL35B PL38A PL38B PL42A PL42B PL42D PL43A PL43B PL44A PL44B PL48A PL48B PL49A PL49B PL51A PL51B PL51D PL52A PL52B PL55A PL55B PL55C PL55D PL57A PL57B PL57C PL57D XRES VCC12 TEMP VCC12 PB3A PB3B VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A VREF2_6 DIFFR_6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 LFSC/M25 Dual Function 4-16 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number AF4 AE5 AG3 AH2 AD6 AJ2 AK2 AD7 AD8 AH3 AJ3 AF9 AE10 AK3 AJ4 AE11 AF10 AK4 AK5 AH10 AH11 AF13 AE14 AK6 AK7 AF14 AJ11 AJ12 AH13 AK8 AK9 AH14 AG14 AK10 AK11 AH15 AG15 AH12 AJ13 AD15 AE15 AK12 AK13 AJ14 AJ15 Ball Function PB3C PB3D PB4A PB4B PB4C PB5A PB5B PB5C PB5D PB7A PB7B PB7C PB7D PB8A PB8B PB9A PB9B PB11A PB11B PB12A PB12B PB12C PB12D PB13A PB13B PB13C PB15A PB15B PB15D PB16A PB16B PB17A PB17B PB19A PB19B PB20A PB20B PB21A PB21B PB21C PB21D PB23A PB23B PB24A PB24B VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 PCLKT5_0 PCLKC5_0 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_2 PCLKC5_2 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 VREF1_5 Dual Function LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C Ball Function PB3C PB3D PB4A PB4B PB4C PB5A PB5B PB5C PB5D PB11A PB11B PB11C PB11D PB12A PB12B PB13A PB13B PB16A PB16B PB20A PB20B PB20C PB20D PB21A PB21B PB21C PB23A PB23B PB23D PB24A PB24B PB25A PB25B PB28A PB28B PB29A PB29B PB31A PB31B PB31C PB31D PB32A PB32B PB33A PB33B VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 PCLKT5_0 PCLKC5_0 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_2 PCLKC5_2 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 VREF1_5 LFSC/M25 Dual Function LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C 4-17 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number AK14 AK15 AK16 AK17 AJ16 AJ17 AE16 AH16 AG16 AK18 AK19 AH17 AH18 AG17 AJ18 AJ19 AK20 AK21 AF18 AG18 AJ20 AJ21 AG19 AK22 AK23 AH19 AK24 AK25 AE19 AE20 AE21 AF21 AG21 AG22 AH22 AH23 AH21 AK28 AK29 AE22 AJ28 AH28 AE24 AE25 AJ29 Ball Function PB25A PB25B PB27A PB27B PB28A PB28B PB28C PB29A PB29B PB31A PB31B PB32A PB32B PB32D PB33A PB33B PB35A PB35B PB36A PB36B PB37A PB37B PB37C PB39A PB39B PB39C PB40A PB40B PB40C PB40D PB41A PB41B PB43A PB43B PB44A PB44B PB44C PB45A PB45B PB45C PB47A PB47B PB47C PB47D PB48A VCCIO Bank 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D VREF1_4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 PCLKT4_2 PCLKC4_2 PCLKT4_1 PCLKC4_1 PCLKT4_0 PCLKC4_0 VREF2_4 PCLKT4_5 PCLKC4_5 Dual Function Ball Function PB35A PB35B PB37A PB37B PB38A PB38B PB38C PB39A PB39B PB41A PB41B PB42A PB42B PB42D PB43A PB43B PB46A PB46B PB47A PB47B PB49A PB49B PB49C PB51A PB51B PB51C PB52A PB52B PB52C PB52D PB53A PB53B PB55A PB55B PB56A PB56B PB56C PB60A PB60B PB60C PB67A PB67B PB67C PB67D PB68A VCCIO Bank 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D VREF1_4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 PCLKT4_2 PCLKC4_2 PCLKT4_1 PCLKC4_1 PCLKT4_0 PCLKC4_0 VREF2_4 PCLKT4_5 PCLKC4_5 LFSC/M25 Dual Function 4-18 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number AH29 AE26 AD25 AJ30 AH30 AG28 AG29 AF26 AD27 AG27 AE28 AC25 AD26 AF28 AF29 AC26 AB26 AG30 AF30 AC28 AB28 AB27 AE30 AD30 AB25 AA25 AA30 Y30 W29 V29 U30 T30 V25 W28 V28 R30 P30 N30 M29 U26 T26 U28 T28 M30 L29 Ball Function PB48B PB48C PB48D PB49A PB49B PB49C PB49D VCC12 PROBE_VCC VCC12 PROBE_GND PR45D PR45C PR45B PR45A PR44D PR44C PR44B PR44A PR43B PR43A PR41D PR41B PR41A PR40B PR40A PR39B PR39A PR37B PR37A PR36B PR36A PR35D PR35B PR35A PR33B PR33A PR32B PR32A PR31D PR31C PR31B PR31A PR28D PR28C VCCIO Bank 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PCLKC3_2 PCLKT3_2 VREF1_3 DIFFR_3 VREF2_3 LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C Dual Function LRC_DLLC_IN_C/LRC_DLLC_FB_D Ball Function PB68B PB68C PB68D PB69A PB69B PB69C PB69D VCC12 PROBE_VCC VCC12 PROBE_GND PR57D PR57C PR57B PR57A PR55D PR55C PR55B PR55A PR52B PR52A PR51D PR51B PR51A PR49B PR49A PR48B PR48A PR44B PR44A PR43B PR43A PR42D PR42B PR42A PR38B PR38A PR35B PR35A PR34D PR34C PR34B PR34A PR31D PR31C VCCIO Bank 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PCLKC3_2 PCLKT3_2 VREF1_3 DIFFR_3 VREF2_3 LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C LFSC/M25 Dual Function LRC_DLLC_IN_C/LRC_DLLC_FB_D 4-19 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number R29 P29 P27 N29 N28 R25 R26 R28 P28 N27 P26 L30 K30 J30 H30 M26 M25 G29 F29 H28 J28 E30 E29 L26 L25 F28 G28 K26 K25 D30 D29 G26 H26 E28 D28 J25 H25 J26 G25 G24 F26 H24 F25 D27 E26 Ball Function PR28B PR28A PR27C PR27B PR27A PR26D PR26C PR26B PR26A PR24D PR24C PR24B PR24A PR23B PR23A PR22D PR22C PR22B PR22A PR19D PR19C PR19B PR19A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR15D PR15C PR15B PR15A VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK VCC12 VCC12 VCCIO Bank 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 CFGIRQN/MPI_IRQ_N TDO URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_1 PCLKT2_1 DIFFR_2 VREF1_2 PCLKT3_3 Dual Function Ball Function PR31B PR31A PR30C PR30B PR30A PR29D PR29C PR29B PR29A PR27D PR27C PR27B PR27A PR26B PR26A PR25D PR25C PR25B PR25A PR22D PR22C PR22B PR22A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK VCC12 VCC12 VCCIO Bank 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 CFGIRQN/MPI_IRQ_N TDO URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_1 PCLKT2_1 DIFFR_2 VREF1_2 PCLKT3_3 LFSC/M25 Dual Function 4-20 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number A29 D26 C30 B30 F24 D25 C28 B28 B27 E25 A28 C27 A27 C26 A26 D24 A25 B26 B25 E24 C25 D23 C24 B24 B23 E23 A24 C23 A23 C22 A22 D22 A21 B22 B21 E22 C21 G22 F22 B20 B19 A20 A19 D19 D18 Ball Function RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R A_VDDAX25_R VCC12 A_VDDIB0_R A_HDINP0_R A_HDINN0_R VCC12 A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R VCC12 A_HDOUTP1_R A_HDINN1_R A_HDINP1_R VCC12 A_VDDIB1_R VCC12 A_VDDIB2_R A_HDINP2_R A_HDINN2_R VCC12 A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R VCC12 A_HDOUTP3_R A_HDINN3_R A_HDINP3_R VCC12 A_VDDIB3_R PT43D PT43C PT41B PT41A PT40D PT40C PT39B PT39A VCCIO Bank 1 1 1 1 1 1 1 1 HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 3 OUT N PCS 3E0 CH 2 OUT N PCS 3E0 CH 2 OUT P PCS 3E0 CH 2 IN P PCS 3E0 CH 2 IN N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 OUT P PCS 3E0 CH 0 IN P PCS 3E0 CH 0 IN N Dual Function Ball Function RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R A_VDDAX25_R VCC12 A_VDDIB0_R A_HDINP0_R A_HDINN0_R VCC12 A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R VCC12 A_HDOUTP1_R A_HDINN1_R A_HDINP1_R VCC12 A_VDDIB1_R VCC12 A_VDDIB2_R A_HDINP2_R A_HDINN2_R VCC12 A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R VCC12 A_HDOUTP3_R A_HDINN3_R A_HDINP3_R VCC12 A_VDDIB3_R PT49D PT49C PT49B PT49A PT47D PT47C PT47B PT47A VCCIO Bank 1 1 1 1 1 1 1 1 HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 3 OUT N PCS 3E0 CH 2 OUT N PCS 3E0 CH 2 OUT P PCS 3E0 CH 2 IN P PCS 3E0 CH 2 IN N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 OUT P PCS 3E0 CH 0 IN P PCS 3E0 CH 0 IN N LFSC/M25 Dual Function 4-21 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number F19 F18 C18 C17 E17 E16 G18 G17 B18 B17 G16 A18 A17 H18 H17 D17 D16 F17 F16 C16 C15 B16 B15 H16 A16 A15 G15 F15 E15 D15 C14 C13 H14 B14 B13 G14 F14 A14 A13 G13 H13 E14 E13 G12 G11 Ball Function PT37D PT37C PT37B PT37A PT36D PT36C PT35B PT35A PT33B PT33A PT32D PT32B PT32A PT31B PT31A PT29B PT29A PT28D PT28C PT28B PT28A PT27B PT27A PT25D PT25B PT25A PT24D PT24C PT24B PT24A PT23B PT23A PT21C PT21B PT21A PT20B PT20A PT19B PT19A PT17D PT17C PT17B PT17A PT15D PT15C VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D0/MPI_DATA0 QOUT/CEON VREF2_1 DOUT MCA_DONE_IN MCA_CLK_P1_OUT MCA_CLK_P1_IN MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA PCLKC1_0 PCLKT1_0/MPI_CLK DP3/PCLKC1_4/MPI_PAR3 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 A3/MPI_ADDR17 A4/MPI_ADDR18 A5/MPI_ADDR19 A6/MPI_ADDR20 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 A9/MPI_ADDR23 A10/MPI_ADDR24 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 Ball Function PT46D PT46C PT46B PT46A PT45D PT45C PT45B PT45A PT43B PT43A PT42D PT42B PT42A PT41B PT41A PT39B PT39A PT38D PT38C PT38B PT38A PT37B PT37A PT35D PT35B PT35A PT33D PT33C PT33B PT33A PT32B PT32A PT31C PT31B PT31A PT29B PT29A PT28B PT28A PT27D PT27C PT27B PT27A PT25D PT25C VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LFSC/M25 Dual Function WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D0/MPI_DATA0 QOUT/CEON VREF2_1 DOUT MCA_DONE_IN MCA_CLK_P1_OUT MCA_CLK_P1_IN MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA PCLKC1_0 PCLKT1_0/MPI_CLK DP3/PCLKC1_4/MPI_PAR3 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 A3/MPI_ADDR17 A4/MPI_ADDR18 A5/MPI_ADDR19 A6/MPI_ADDR20 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 A9/MPI_ADDR23 A10/MPI_ADDR24 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 4-22 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number D14 D13 F12 F13 B12 B11 E12 D12 G10 G9 C10 E9 B10 B9 A10 D9 A9 C9 A8 C8 A7 E8 B8 B7 C7 D8 C6 E7 B6 B5 A6 D7 A5 C5 A4 C4 A3 E6 B4 B3 C3 D6 L5 M5 G2 Ball Function PT15B PT15A PT13D PT13C PT11B PT11A PT10D PT10C PT9B PT9A A_VDDIB3_L VCC12 A_HDINP3_L A_HDINN3_L A_HDOUTP3_L VCC12 A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L VCC12 A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCC12 A_VDDIB1_L VCC12 A_HDINP1_L A_HDINN1_L A_HDOUTP1_L VCC12 A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L VCC12 A_HDINN0_L A_HDINP0_L A_VDDIB0_L VCC12 NC NC NC VCCIO Bank 1 1 1 1 1 1 1 1 1 1 PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT P PCS 360 CH 0 OUT N PCS 360 CH 1 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT P PCS 360 CH 2 OUT N PCS 360 CH 3 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P Dual Function A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 Ball Function PT25B PT25A PT24D PT24C PT24B PT24A PT23D PT23C PT23B PT23A A_VDDIB3_L VCC12 A_HDINP3_L A_HDINN3_L A_HDOUTP3_L VCC12 A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L VCC12 A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCC12 A_VDDIB1_L VCC12 A_HDINP1_L A_HDINN1_L A_HDOUTP1_L VCC12 A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L VCC12 A_HDINN0_L A_HDINP0_L A_VDDIB0_L VCC12 PL21A PL21B PL20A VCCIO Bank 1 1 1 1 1 1 1 1 1 1 7 7 7 PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT P PCS 360 CH 0 OUT N PCS 360 CH 1 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT P PCS 360 CH 2 OUT N PCS 360 CH 3 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P LFSC/M25 Dual Function A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 4-23 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number G1 M4 J3 P5 W5 T6 U3 V3 T5 T4 V5 U6 U4 U5 V4 Y2 AA2 W3 Y3 AB3 AC4 AD4 AE3 AF3 AF7 AF6 AH4 AG5 AF8 AG8 AG7 AG10 AF12 AH7 AE13 AG13 AH8 AJ5 AJ6 AF15 AJ7 AJ8 AE12 AF16 AF19 Ball Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIO Bank Dual Function Ball Function PL20B NC NC NC PL48C PL35C PL36A PL36B PL39A PL39B PL43C PL42C PL40A PL40B PL43D PL47A PL47B PL47D PL47C NC PL53A PL53B PL56A PL56B PB7A PB7B PB8A PB8B PB9A PB9B NC NC NC PB15A PB15D PB23C PB15B PB17A PB17B PB21D PB19A PB19B PB15C PB38D PB49D VCCIO Bank 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 LFSC/M25 Dual Function 4-24 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number AH20 AK27 AJ24 AF17 AH27 AD23 AE23 AH24 AH25 AH26 AF24 AG24 AG25 AF25 AG26 AF27 AD28 AC27 AE29 AD29 AB30 AA28 Y27 W27 V30 W30 W26 V26 U25 T27 R27 V27 U27 U29 T29 T24 Y25 P24 K28 P23 L28 M27 L27 H27 G27 Ball Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIO Bank Dual Function Ball Function PB51D NC NC PB42C PB61B PB57A PB57B PB59A PB59B PB61A PB63A PB63B PB64A PB64B PB65A PB65B PR56B PR56A PR53B PR53A NC NC PR47C PR47D PR47A PR47B PR43D PR43C PR42C PR40B PR40A PR39B PR39A PR36B PR36A PR35C PR48C NC NC NC NC PR21B PR21A PR20B PR20A VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 LFSC/M25 Dual Function 4-25 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number E19 G21 G20 G19 F9 A11 G7 AH9 H8 T8 AB9 AC8 AB22 AC23 R23 H23 H15 L24 T23 AC24 T25 W25 AD24 AE17 AE18 AC15 AD16 AE9 AA6 T7 W6 L7 P7 AA10 AA11 AA12 AA13 AA14 AA17 AA18 AA19 AA20 AA21 AA22 AA9 Ball Function NC NC NC NC NC NC NC NC VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 Dual Function Ball Function NC NC NC NC NC NC NC NC VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 LFSC/M25 Dual Function 4-26 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number AB10 AB21 J10 J21 K10 K11 K12 K13 K14 K17 K18 K19 K20 K21 K22 K9 L10 L21 M10 M21 N10 N21 P10 P21 U10 U21 V10 V21 W10 W21 Y10 Y21 H11 H12 H19 H20 M23 M24 N23 N24 U23 U24 V23 V24 W23 Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO Bank Dual Function Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO Bank LFSC/M25 Dual Function 4-27 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number W24 AC17 AC18 AC19 AD17 AD18 AD19 AC12 AC13 AC14 AD12 AD13 AD14 U7 U8 V7 V8 W7 W8 M7 M8 N7 N8 H10 H21 H22 H9 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J23 J24 K23 K24 L22 L23 M22 N22 Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO Bank Dual Function Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO Bank LFSC/M25 Dual Function 4-28 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number P22 R22 AA23 AA24 AB23 AB24 T22 U22 V22 W22 Y22 Y23 Y24 AB16 AB17 AB18 AB19 AB20 AC20 AC21 AC22 AD20 AD21 AD22 AB11 AB12 AB13 AB14 AB15 AC10 AC11 AC9 AD10 AD11 AD9 AA7 AA8 AB7 AB8 T9 U9 V9 W9 Y7 Y8 Ball Function VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO Bank Dual Function Ball Function VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO Bank LFSC/M25 Dual Function 4-29 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number Y9 J7 J8 K7 K8 L8 L9 M9 N9 P9 R9 A1 A30 AA15 AA16 AK1 AK30 K15 K16 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 N11 N12 N13 N14 N15 N16 Ball Function VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M25 Dual Function 4-30 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number N17 N18 N19 N20 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 U11 U12 U13 U14 U15 U16 U17 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M25 Dual Function 4-31 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number U18 U19 U20 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 H2 N4 N6 J2 L2 H4 AB2 AD1 W4 AA4 AE7 AH6 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO Bank LFSC/M25 Dual Function 4-32 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number AG11 AJ9 AJ23 AG20 AJ26 AG23 AC29 AA26 Y28 AA29 G30 J29 K27 N25 F20 C19 C12 F11 H1 L4 M3 N5 K2 M2 P6 G4 H3 AC2 AA3 AE1 Y4 AB4 AA5 AE6 AE8 AH5 AG9 AG6 AF11 AG12 AJ10 AK26 AJ22 AF20 AJ25 Ball Function VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCCIO1 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M25 Dual Function 4-33 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number AJ27 AF23 AF22 AE27 AA27 AB29 Y26 AC30 Y29 F30 E27 F27 P25 H29 K29 R24 M28 J27 N26 E20 E21 F21 F23 G23 D21 D20 E18 C20 C11 A12 E11 F8 G8 D11 D10 H7 F10 E10 AC16 J22 J9 B2 C2 C29 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC VCC VCC NC RESPN_ULC RESPN_URC VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC VCC VCC NC RESPN_ULC RESPN_URC VCCIO Bank LFSC/M25 Dual Function 4-34 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA1, 2 (Cont.) LFSC/M15 Ball Number B29 Ball Function NC VCCIO Bank Dual Function Ball Function NC VCCIO Bank LFSC/M25 Dual Function 1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). 2. The LatticeSC/M15 and LatticeSC/M25 in a 900-pin package supports a 16-bit MPI interface. 4-35 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 Ball Number C28 D28 B28 F28 J21 J20 K20 K21 K23 J23 J24 K24 K25 J25 K26 K27 D32 D31 M23 N23 E32 E31 J28 K28 F32 F31 L25 L26 G31 G32 J29 H29 M25 N25 H31 H32 M24 N24 L32 M32 R25 R24 N31 N32 P27 P28 P30 P29 T23 T24 LFSC/M25 Ball Function A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC RESETN TSALLN DONE INITN M0 M1 M2 M3 PL16A PL16B PL16C PL16D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL20A PL20B PL20C PL20D PL21A PL21B PL22A PL22B PL22C PL22D PL25A PL25B PL25C PL25D PL26A PL26B PL26C PL26D PL27A PL27B PL27C PL27D PL29A PL29B PL29C PL29D VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 VREF1_7 DIFFR_7 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B Dual Function Ball Function A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC RESETN TSALLN DONE INITN M0 M1 M2 M3 PL16A PL16B PL16C PL16D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL21A PL21B PL21C PL21D PL22A PL22B PL25A PL25B PL25C PL25D PL23A PL23B PL23C PL23D PL35A PL35B PL35C PL35D PL36A PL36B PL36C PL36D PL38A PL38B PL38C PL38D LFSC/M40 VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 VREF1_7 DIFFR_7 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B Dual Function 4-36 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number P32 P31 R28 T28 R30 R29 T25 T26 R31 R32 U23 U24 T31 T32 T27 U28 U32 U31 U26 U25 V32 V31 V24 V23 V29 V30 U27 V28 W30 W29 V25 W26 W31 Y31 W27 Y27 W28 Y28 Y26 W25 W32 Y32 AB28 AA28 AB32 AA32 AB27 AC27 AD31 AC31 LFSC/M25 Ball Function PL30A PL30B PL30C PL30D PL31A PL31B PL31C PL31D PL34A PL34B PL34C PL34D PL35A PL35B PL35C PL35D PL36A PL36B PL36C PL36D PL38A PL38B PL38C PL38D PL39A PL39B PL39C PL39D PL40A PL40B PL40C PL40D PL42A PL42B PL42C PL42D PL43A PL43B PL43C PL43D PL44A PL44B PL44C PL44D PL47A PL47B PL47C PL47D PL48A PL48B VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 DIFFR_6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 PCLKC6_3 Dual Function Ball Function PL39A PL39B PL39C PL39D PL40A PL40B PL40C PL40D PL43A PL43B PL43C PL43D PL44A PL44B PL44C PL44D PL45A PL45B PL45C PL45D PL47A PL47B PL47C PL47D PL48A PL48B PL48C PL48D PL49A PL49B PL49C PL49D PL51A PL51B PL51C PL51D PL52A PL52B PL52C PL52D PL53A PL53B PL53C PL53D PL60A PL60B PL60C PL60D PL61A PL61B LFSC/M40 VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 DIFFR_6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 PCLKC6_3 Dual Function 4-37 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number Y24 Y23 AD29 AD30 AF28 AE28 AC28 AD28 AB26 AC26 AC32 AD32 AA24 AA23 AE30 AE29 AC25 AB25 AE31 AE32 AE26 AE27 AF32 AF31 AC24 AD25 AG32 AG31 AC23 AD24 AH32 AH31 AJ32 AK32 AF27 AG28 AK31 AL31 AE25 AE24 AK30 AL30 AD23 AE23 AK29 AL29 AF26 AF25 AJ28 AK28 LFSC/M25 Ball Function PL48C PL48D PL49A PL49B PL49C PL49D PL51A PL51B PL51C PL51D PL52A PL52B PL52C PL52D PL53A PL53B PL53C PL53D PL55A PL55B PL55C PL55D PL56A PL56B PL56C PL56D PL57A PL57B PL57C PL57D XRES TEMP PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D PB7A PB7B PB7C PB7D PB8A PB8B VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF1_5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F VREF2_6 Dual Function Ball Function PL61C PL61D PL62A PL62B PL62C PL62D PL65A PL65B PL65C PL65D PL66A PL66B PL66C PL66D PL67A PL67B PL67C PL67D PL69A PL69B PL69C PL69D PL70A PL70B PL70C PL70D PL71A PL71B PL71C PL71D XRES TEMP PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D PB7A PB7B PB7C PB7D PB8A PB8B LFSC/M40 VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF1_5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F VREF2_6 Dual Function 4-38 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number AJ31 AH30 AM30 AM29 AH29 AH28 AJ27 AK27 AE22 AF23 AL28 AL27 AC21 AD21 AM28 AM27 AG23 AF22 AG26 AG25 AL26 AM26 AJ24 AK24 AE21 AE20 AJ22 AK22 AG22 AH22 AL23 AL22 AH23 AH24 AJ21 AK21 AE19 AF19 AM23 AM22 AH25 AH26 AL21 AL20 AG20 AG19 AJ19 AK19 AD18 AE18 LFSC/M25 Ball Function PB9A PB9B PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D PB13A PB13B PB13C PB13D PB15A PB15B PB15C PB15D PB16A PB16B PB17A PB17B PB19A PB19B PB19C PB19D PB20A PB20B PB20C PB20D PB21A PB21B PB21C PB21D PB23A PB23B PB23C PB23D PB24A PB24B PB24C PB24D PB25A PB25B PB25C PB25D PB28A PB28B PB28C PB28D VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 PCLKT5_0 PCLKC5_0 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 Dual Function Ball Function PB9A PB9B PB11A PB11B PB11C PB11D PB13A PB13B PB13C PB13D PB15A PB15B PB15C PB15D PB17A PB17B PB17C PB17D PB19A PB19B PB22A PB22B PB25A PB25B PB25C PB25D PB30A PB30B PB30C PB30D PB31A PB31B PB31C PB31D PB33A PB33B PB33C PB33D PB34A PB34B PB34C PB34D PB35A PB35B PB35C PB35D PB37A PB37B PB37C PB37D LFSC/M40 VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 PCLKT5_0 PCLKC5_0 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 Dual Function 4-39 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number AM21 AM20 AH21 AH20 AJ18 AK18 AH19 AH18 AL19 AM19 AH17 AG17 AL18 AM18 AC17 AD17 AL17 AM17 AE17 AF17 AM16 AL16 AF16 AE16 AM15 AL15 AD16 AC16 AM14 AL14 AG16 AH16 AK15 AJ15 AH15 AH14 AM13 AM12 AH13 AH12 AK14 AJ14 AE15 AD15 AL13 AL12 AG14 AG13 AM11 AM10 LFSC/M25 Ball Function PB29A PB29B PB29C PB29D PB31A PB31B PB31C PB31D PB32A PB32B PB32C PB32D PB33A PB33B PB33C PB33D PB35A PB35B PB35C PB35D PB37A PB37B PB37C PB37D PB38A PB38B PB38C PB38D PB39A PB39B PB39C PB39D PB41A PB41B PB41C PB41D PB42A PB42B PB42C PB42D PB43A PB43B PB43C PB43D PB46A PB46B PB46C PB46D PB47A PB47B VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 Dual Function Ball Function PB38A PB38B PB38C PB38D PB39A PB39B PB39C PB39D PB41A PB41B PB41C PB41D PB42A PB42B PB42C PB42D PB43A PB43B PB43C PB43D PB45A PB45B PB45C PB45D PB46A PB46B PB46C PB46D PB47A PB47B PB47C PB47D PB49A PB49B PB49C PB49D PB50A PB50B PB50C PB50D PB51A PB51B PB51C PB51D PB53A PB53B PB53C PB53D PB54A PB54B LFSC/M40 VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 Dual Function 4-40 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number AH11 AH10 AK12 AJ12 AF14 AE14 AL11 AL10 AH9 AH8 AK11 AJ11 AH7 AH6 AK8 AJ8 AF11 AD12 AE12 AM6 AM5 AC12 AL6 AL5 AG7 AG8 AK6 AJ6 AF10 AE11 AM4 AM3 AH5 AH4 AK5 AJ5 AF8 AF7 AL4 AL3 AG5 AF6 AK3 AJ3 AE10 AD10 AL2 AK2 AE9 AE8 LFSC/M25 Ball Function PB47C PB47D PB49A PB49B PB49C PB49D PB51A PB51B PB51C PB51D PB52A PB52B PB52C PB52D PB53A PB53B PB53C PB55A PB55B PB56A PB56B PB56C PB57A PB57B PB59A PB59B PB60A PB60B PB60C PB60D PB61A PB61B PB63A PB63B PB64A PB64B PB64C PB64D PB65A PB65B PB65C PB65D PB67A PB67B PB67C PB67D PB68A PB68B PB68C PB68D VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D VREF1_4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 PCLKT4_5 PCLKC4_5 Dual Function PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 Ball Function PB54C PB54D PB55A PB55B PB55C PB55D PB57A PB57B PB57C PB57D PB58A PB58B PB58C PB58D PB67A PB67B PB67C PB69A PB69B PB70A PB70B PB70C PB73A PB73B PB74A PB74B PB75A PB75B PB75C PB75D PB77A PB77B PB78A PB78B PB79A PB79B PB79C PB79D PB81A PB81B PB81C PB81D PB82A PB82B PB82C PB82D PB83A PB83B PB83C PB83D LFSC/M40 VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D VREF1_4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 PCLKT4_5 PCLKC4_5 Dual Function PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 4-41 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number AJ1 AK1 AJ2 AH3 AH1 AH2 AD9 AC10 AG2 AG1 AD8 AC9 AF2 AF1 AE6 AE7 AE1 AE2 AB8 AC8 AE4 AE3 AA10 AA9 AD1 AC1 AC7 AB7 AD5 AC5 AE5 AF5 AD3 AD4 Y10 Y9 AC2 AD2 AC6 AB6 AA1 AB1 AA5 AB5 Y1 W1 W8 Y7 Y5 W5 LFSC/M25 Ball Function PB69A PB69B PB69C PB69D PROBE_VCC PROBE_GND PR57D PR57C PR57B PR57A PR56D PR56C PR56B PR56A PR55D PR55C PR55B PR55A PR53D PR53C PR53B PR53A PR52D PR52C PR52B PR52A PR51D PR51C PR51B PR51A PR49D PR49C PR49B PR49A PR48D PR48C PR48B PR48A PR47D PR47C PR47B PR47A PR44D PR44C PR44B PR44A PR43D PR43C PR43B PR43A VCCIO Bank 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF2_3 LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E Dual Function LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C Ball Function PB85A PB85B PB85C PB85D PROBE_VCC PROBE_GND PR71D PR71C PR71B PR71A PR70D PR70C PR70B PR70A PR69D PR69C PR69B PR69A PR67D PR67C PR67B PR67A PR66D PR66C PR66B PR66A PR65D PR65C PR65B PR65A PR62D PR62C PR62B PR62A PR61D PR61C PR61B PR61A PR60D PR60C PR60B PR60A PR53D PR53C PR53B PR53A PR52D PR52C PR52B PR52A LFSC/M40 VCCIO Bank 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF2_3 LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E Dual Function LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C 4-42 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number Y6 W6 Y2 W2 W7 V8 W4 W3 V5 U6 V3 V4 V10 V9 V2 V1 U8 U7 U2 U1 U5 T6 T1 T2 U9 U10 R1 R2 T7 T8 R4 R3 T5 R5 P2 P1 T9 T10 P4 P3 P5 P6 N1 N2 R9 R8 M1 L1 N9 M9 LFSC/M25 Ball Function PR42D PR42C PR42B PR42A PR40D PR40C PR40B PR40A PR39D PR39C PR39B PR39A PR38D PR38C PR38B PR38A PR36D PR36C PR36B PR36A PR35D PR35C PR35B PR35A PR34D PR34C PR34B PR34A PR31D PR31C PR31B PR31A PR30D PR30C PR30B PR30A PR29D PR29C PR29B PR29A PR27D PR27C PR27B PR27A PR26D PR26C PR26B PR26A PR25D PR25C VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 DIFFR_2 VREF1_2 PCLKC3_3 PCLKT3_3 PCLKC3_2 PCLKT3_2 VREF1_3 Dual Function DIFFR_3 Ball Function PR51D PR51C PR51B PR51A PR49D PR49C PR49B PR49A PR48D PR48C PR48B PR48A PR47D PR47C PR47B PR47A PR45D PR45C PR45B PR45A PR44D PR44C PR44B PR44A PR43D PR43C PR43B PR43A PR40D PR40C PR40B PR40A PR39D PR39C PR39B PR39A PR38D PR38C PR38B PR38A PR36D PR36C PR36B PR36A PR35D PR35C PR35B PR35A PR23D PR23C LFSC/M40 VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 DIFFR_2 VREF1_2 PCLKC3_3 PCLKT3_3 PCLKC3_2 PCLKT3_2 VREF1_3 Dual Function DIFFR_3 4-43 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number H1 H2 N8 M8 H4 J4 G1 G2 L7 L8 F2 F1 K5 J5 E2 E1 N10 M10 D2 D1 K6 K7 J8 K8 J10 J9 K9 J12 J13 K12 K13 K10 F5 B5 D5 C5 B2 C1 C2 A3 D3 B3 D4 B4 A4 H5 G5 F4 H6 F6 LFSC/M25 Ball Function PR25B PR25A PR22D PR22C PR22B PR22A PR21B PR21A PR20D PR20C PR20B PR20A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R A_VDDIB0_R A_HDINP0_R A_HDINN0_R A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R A_HDOUTP1_R A_HDINN1_R A_HDINP1_R A_VDDIB1_R A_VDDIB2_R A_HDINP2_R VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 PCS 3E0 CH 2 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 IN P PCS 3E0 CH 0 IN N PCS 3E0 CH 0 OUT P CFGIRQN/MPI_IRQ_N TDO URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 Dual Function Ball Function PR23B PR23A PR25D PR25C PR25B PR25A PR22B PR22A PR21D PR21C PR21B PR21A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R A_VDDIB0_R A_HDINP0_R A_HDINN0_R A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R A_HDOUTP1_R A_HDINN1_R A_HDINP1_R A_VDDIB1_R A_VDDIB2_R A_HDINP2_R LFSC/M40 VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 PCS 3E0 CH 2 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 IN P PCS 3E0 CH 0 IN N PCS 3E0 CH 0 OUT P CFGIRQN/MPI_IRQ_N TDO URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 Dual Function 4-44 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number G6 A6 D6 B6 D7 B7 A7 G7 F7 H7 H8 F8 G8 A8 D8 B8 D9 B9 A9 H10 G10 H9 H11 F11 G11 A11 D11 B11 D12 B12 A12 G12 F12 H12 B10 D10 C10 J15 K15 E13 F13 H13 G13 E14 F14 H14 G14 D13 D14 E15 LFSC/M25 Ball Function A_HDINN2_R A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R A_HDOUTP3_R A_HDINN3_R A_HDINP3_R A_VDDIB3_R B_VDDIB0_R B_HDINP0_R B_HDINN0_R B_HDOUTP0_R B_VDDOB0_R B_HDOUTN0_R B_VDDOB1_R B_HDOUTN1_R B_HDOUTP1_R B_HDINN1_R B_HDINP1_R B_VDDIB1_R B_VDDIB2_R B_HDINP2_R B_HDINN2_R B_HDOUTP2_R B_VDDOB2_R B_HDOUTN2_R B_VDDOB3_R B_HDOUTN3_R B_HDOUTP3_R B_HDINN3_R B_HDINP3_R B_VDDIB3_R VCC12 B_REFCLKN_R B_REFCLKP_R PT49D PT49C PT49B PT49A PT47D PT47C PT47B PT47A PT46D PT46C PT46B PT46A PT45D VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 PCS 3E1 CH 3 OUT N PCS 3E1 CH 3 OUT P PCS 3E1 CH 3 IN N PCS 3E1 CH 3 IN P PCS 3E1 CH 2 OUT N PCS 3E1 CH 2 IN P PCS 3E1 CH 2 IN N PCS 3E1 CH 2 OUT P PCS 3E1 CH 1 OUT N PCS 3E1 CH 1 OUT P PCS 3E1 CH 1 IN N PCS 3E1 CH 1 IN P PCS 3E1 CH 0 OUT N PCS 3E1 CH 0 IN P PCS 3E1 CH 0 IN N PCS 3E1 CH 0 OUT P PCS 3E0 CH 3 OUT N PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 2 OUT N Dual Function PCS 3E0 CH 2 IN N PCS 3E0 CH 2 OUT P Ball Function A_HDINN2_R A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R A_HDOUTP3_R A_HDINN3_R A_HDINP3_R A_VDDIB3_R B_VDDIB0_R B_HDINP0_R B_HDINN0_R B_HDOUTP0_R B_VDDOB0_R B_HDOUTN0_R B_VDDOB1_R B_HDOUTN1_R B_HDOUTP1_R B_HDINN1_R B_HDINP1_R B_VDDIB1_R B_VDDIB2_R B_HDINP2_R B_HDINN2_R B_HDOUTP2_R B_VDDOB2_R B_HDOUTN2_R B_VDDOB3_R B_HDOUTN3_R B_HDOUTP3_R B_HDINN3_R B_HDINP3_R B_VDDIB3_R VCC12 B_REFCLKN_R B_REFCLKP_R PT61D PT61C PT59B PT59A PT58D PT58C PT57B PT57A PT55D PT55C PT55B PT55A PT54D LFSC/M40 VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 PCS 3E1 CH 3 OUT N PCS 3E1 CH 3 OUT P PCS 3E1 CH 3 IN N PCS 3E1 CH 3 IN P PCS 3E1 CH 2 OUT N PCS 3E1 CH 2 IN P PCS 3E1 CH 2 IN N PCS 3E1 CH 2 OUT P PCS 3E1 CH 1 OUT N PCS 3E1 CH 1 OUT P PCS 3E1 CH 1 IN N PCS 3E1 CH 1 IN P PCS 3E1 CH 0 OUT N PCS 3E1 CH 0 IN P PCS 3E1 CH 0 IN N PCS 3E1 CH 0 OUT P PCS 3E0 CH 3 OUT N PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 2 OUT N Dual Function PCS 3E0 CH 2 IN N PCS 3E0 CH 2 OUT P 4-45 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number E16 C13 C14 B14 B13 L13 C15 D15 J16 K16 H15 H16 A14 A13 G16 F16 B16 B15 L16 A16 A15 L17 A17 A18 F17 G17 B17 B18 H17 H18 A19 A20 L20 J17 K17 C18 D18 B19 B20 E17 E18 C20 C19 H19 G19 D20 D19 H20 G20 E19 LFSC/M25 Ball Function PT45C PT45B PT45A PT43B PT43A PT42D PT42B PT42A PT41B PT41A PT39D PT39C PT39B PT39A PT38D PT38C PT38B PT38A PT37C PT37B PT37A PT35C PT35B PT35A PT33D PT33C PT33B PT33A PT32D PT32C PT32B PT32A PT31C PT31B PT31A PT29B PT29A PT28B PT28A PT27D PT27C PT27B PT27A PT25D PT25C PT25B PT25A PT24D PT24C PT24B VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D0/MPI_DATA0 QOUT/CEON VREF2_1 DOUT MCA_DONE_IN MCA_CLK_P1_OUT MCA_CLK_P1_IN D21/PCLKC1_1/MPI_DATA21 D22/PCLKT1_1/MPI_DATA22 MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA DP2/MPI_PAR2 PCLKC1_0 PCLKT1_0/MPI_CLK D24/PCLKT1_4/MPI_DATA24 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 A3/MPI_ADDR17 A4/MPI_ADDR18 D25/PCLKC1_5/MPI_DATA25 D26/PCLKT1_5/MPI_DATA26 A5/MPI_ADDR19 A6/MPI_ADDR20 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 A9/MPI_ADDR23 A10/MPI_ADDR24 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 Ball Function PT54C PT53B PT53A PT51B PT51A PT50D PT50B PT50A PT49B PT49A PT47D PT47C PT47B PT47A PT46D PT46C PT46B PT46A PT45C PT45B PT45A PT43C PT43B PT43A PT42D PT42C PT42B PT42A PT41D PT41C PT41B PT41A PT39C PT39B PT39A PT38B PT38A PT37B PT37A PT35D PT35C PT35B PT35A PT33D PT33C PT33B PT33A PT30D PT30C PT30B LFSC/M40 VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D0/MPI_DATA0 QOUT/CEON VREF2_1 DOUT MCA_DONE_IN MCA_CLK_P1_OUT MCA_CLK_P1_IN D21/PCLKC1_1/MPI_DATA21 D22/PCLKT1_1/MPI_DATA22 MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA DP2/MPI_PAR2 PCLKC1_0 PCLKT1_0/MPI_CLK D24/PCLKT1_4/MPI_DATA24 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 A3/MPI_ADDR17 A4/MPI_ADDR18 D25/PCLKC1_5/MPI_DATA25 D26/PCLKT1_5/MPI_DATA26 A5/MPI_ADDR19 A6/MPI_ADDR20 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 A9/MPI_ADDR23 A10/MPI_ADDR24 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 4-46 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number F19 J18 K18 E20 F20 C23 D23 B23 H21 F21 G21 A21 B21 D21 B22 D22 A22 G22 F22 H22 H24 G23 H23 A24 B24 D24 B25 D25 A25 G25 F25 H25 H26 F26 G26 A26 B26 D26 B27 D27 A27 G27 F27 H27 F29 G28 H28 A29 B29 D29 LFSC/M25 Ball Function PT24A PT23D PT23C PT23B PT23A B_REFCLKP_L B_REFCLKN_L VCC12 B_VDDIB3_L B_HDINP3_L B_HDINN3_L B_HDOUTP3_L B_HDOUTN3_L B_VDDOB3_L B_HDOUTN2_L B_VDDOB2_L B_HDOUTP2_L B_HDINN2_L B_HDINP2_L B_VDDIB2_L B_VDDIB1_L B_HDINP1_L B_HDINN1_L B_HDOUTP1_L B_HDOUTN1_L B_VDDOB1_L B_HDOUTN0_L B_VDDOB0_L B_HDOUTP0_L B_HDINN0_L B_HDINP0_L B_VDDIB0_L A_VDDIB3_L A_HDINP3_L A_HDINN3_L A_HDOUTP3_L A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L A_HDINN2_L A_HDINP2_L A_VDDIB2_L A_VDDIB1_L A_HDINP1_L A_HDINN1_L A_HDOUTP1_L A_HDOUTN1_L A_VDDOB1_L VCCIO Bank 1 1 1 1 1 PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 1 OUT N PCS 360 CH 2 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P PCS 360 CH 3 OUT N PCS 361 CH 0 OUT P PCS 361 CH 0 IN N PCS 361 CH 0 IN P PCS 361 CH 0 OUT N PCS 361 CH 1 IN P PCS 361 CH 1 IN N PCS 361 CH 1 OUT P PCS 361 CH 1 OUT N PCS 361 CH 2 OUT P PCS 361 CH 2 IN N PCS 361 CH 2 IN P PCS 361 CH 2 OUT N PCS 361 CH 3 IN P PCS 361 CH 3 IN N PCS 361 CH 3 OUT P PCS 361 CH 3 OUT N Dual Function MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 Ball Function PT30A PT28D PT28C PT27B PT27A B_REFCLKP_L B_REFCLKN_L VCC12 B_VDDIB3_L B_HDINP3_L B_HDINN3_L B_HDOUTP3_L B_HDOUTN3_L B_VDDOB3_L B_HDOUTN2_L B_VDDOB2_L B_HDOUTP2_L B_HDINN2_L B_HDINP2_L B_VDDIB2_L B_VDDIB1_L B_HDINP1_L B_HDINN1_L B_HDOUTP1_L B_HDOUTN1_L B_VDDOB1_L B_HDOUTN0_L B_VDDOB0_L B_HDOUTP0_L B_HDINN0_L B_HDINP0_L B_VDDIB0_L A_VDDIB3_L A_HDINP3_L A_HDINN3_L A_HDOUTP3_L A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L A_HDINN2_L A_HDINP2_L A_VDDIB2_L A_VDDIB1_L A_HDINP1_L A_HDINN1_L A_HDOUTP1_L A_HDOUTN1_L A_VDDOB1_L LFSC/M40 VCCIO Bank 1 1 1 1 1 PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 1 OUT N PCS 360 CH 2 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P PCS 360 CH 3 OUT N PCS 361 CH 0 OUT P PCS 361 CH 0 IN N PCS 361 CH 0 IN P PCS 361 CH 0 OUT N PCS 361 CH 1 IN P PCS 361 CH 1 IN N PCS 361 CH 1 OUT P PCS 361 CH 1 OUT N PCS 361 CH 2 OUT P PCS 361 CH 2 IN N PCS 361 CH 2 IN P PCS 361 CH 2 OUT N PCS 361 CH 3 IN P PCS 361 CH 3 IN N PCS 361 CH 3 OUT P PCS 361 CH 3 OUT N Dual Function MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 4-47 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number B30 D30 A30 C31 C32 B31 AL25 AL24 AG27 AH27 AM25 AM24 AL9 AL8 AK9 AJ9 AG10 AG11 J30 H30 M28 N28 J32 J31 N26 N27 K31 K32 P25 P26 L27 L28 M29 L29 M30 L30 L31 M31 AA29 AA30 AB31 AA31 AG30 AG29 AB29 AB30 Y25 AA25 AA8 Y8 LFSC/M25 Ball Function A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L A_HDINN0_L A_HDINP0_L A_VDDIB0_L NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIO Bank PCS 360 CH 0 OUT P PCS 360 CH 0 IN N PCS 360 CH 0 IN P Dual Function PCS 360 CH 0 OUT N Ball Function A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L A_HDINN0_L A_HDINP0_L A_VDDIB0_L PB26A PB26B PB26C PB26D PB27A PB27B PB62A PB62B PB63A PB63B PB63C PB63D PL26A PL26B PL26C PL26D PL27A PL27B PL27C PL27D PL29A PL29B PL29C PL29D PL22C PL22D PL30A PL30B PL31A PL31B PL34A PL34B PL56A PL56B PL57A PL57B PL57C PL57D PL58A PL58B PL58C PL58D PR58D PR58C LFSC/M40 VCCIO Bank 5 5 5 5 5 5 4 4 4 4 4 4 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 3 3 PCS 360 CH 0 OUT P PCS 360 CH 0 IN N PCS 360 CH 0 IN P Dual Function PCS 360 CH 0 OUT N 4-48 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number AB3 AB4 AG4 AG3 AA2 AB2 AA3 AA4 L5 L6 M2 L2 L3 M3 L4 M4 P7 P8 K1 K2 N6 N7 J2 J1 N5 M5 H3 J3 A5 A28 AJ25 AK25 AF20 AG6 AM7 AL7 AD13 AC13 AC20 AD20 AM9 AM8 AF13 AE13 E30 E29 E27 E26 E25 E24 LFSC/M25 Ball Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VDDAX25_R VDDAX25_L NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCIO Bank Dual Function Ball Function PR58B PR58A PR57D PR57C PR57B PR57A PR56B PR56A PR22D PR22C PR34B PR34A PR31B PR31A PR30B PR30A PR29D PR29C PR29B PR29A PR27D PR27C PR27B PR27A PR26D PR26C PR26B PR26A VDDAX25_R VDDAX25_L PB21A PB21B PB27C PB62C PB66A PB66B PB66C PB66D PB22C PB22D PB61A PB61B PB61C PB61D VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 LFSC/M40 VCCIO Bank 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 5 5 4 4 4 4 4 5 5 4 4 4 4 Dual Function 4-49 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number E22 E21 E3 E4 E6 E7 E8 E9 E11 E12 A23 A31 AA13 AA15 AA18 AA20 AA26 AA6 AB10 AB24 AC14 AC22 AC29 AC3 AD11 AD19 AD27 AD7 AF12 AF18 AF24 AF30 AF4 AG15 AG21 AG9 AJ10 AJ16 AJ20 AJ26 AJ29 AJ4 AK13 AK17 AK23 AK7 AL1 AL32 AM2 AM31 LFSC/M25 Ball Function VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFSC/M40 VCCIO Bank Dual Function 4-50 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number B1 B32 C11 C12 C16 C21 C22 C24 C25 C26 C27 C29 C3 C30 C4 C6 C7 C8 C9 D17 F18 F3 F30 F9 G15 G24 G29 G3 J14 J22 J26 J6 K11 K19 K30 K4 L23 L9 M13 M15 M18 M20 M27 M7 N12 N14 N19 N21 N29 N3 LFSC/M25 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND LFSC/M40 VCCIO Bank Dual Function 4-51 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number P10 P13 P15 P18 P20 P24 R12 R14 R16 R17 R19 R21 R26 R6 T15 T18 T30 T4 U15 U18 U29 U3 V12 V14 V16 V17 V19 V21 V27 V7 W13 W15 W18 W20 W23 W9 Y12 Y14 Y19 Y21 Y30 Y4 N13 N15 N16 N17 N18 N20 P14 P16 LFSC/M25 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC LFSC/M40 VCCIO Bank Dual Function 4-52 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number P17 P19 R13 R15 R18 R20 T13 T14 T16 T17 T19 T20 U13 U14 U16 U17 U19 U20 V13 V15 V18 V20 W14 W16 W17 W19 Y13 Y15 Y16 Y17 Y18 Y20 C17 D16 F15 F24 G18 G9 J11 J19 K14 K22 G4 J7 K3 L10 M6 N4 P9 R7 LFSC/M25 Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO Bank Dual Function Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 LFSC/M40 VCCIO Bank Dual Function 4-53 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number AA7 AB9 AC4 AD6 AF3 T3 U4 V6 W10 Y3 AC11 AD14 AF15 AF9 AG12 AJ13 AJ7 AK10 AK16 AK4 AC19 AD22 AF21 AG18 AG24 AJ17 AJ23 AJ30 AK20 AK26 AA27 AB23 AC30 AD26 AF29 T29 U30 V26 W24 Y29 G30 J27 K29 L24 M26 N30 P23 R27 AA11 AA12 LFSC/M25 Ball Function VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCAUX VCCAUX VCCIO Bank Dual Function Ball Function VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCAUX VCCAUX LFSC/M40 VCCIO Bank Dual Function 4-54 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number AA21 AA22 AB11 AB12 AB15 AB16 AB17 AB18 AB21 AB22 L11 L12 L14 L15 L18 L19 L21 L22 M11 M12 M21 M22 P11 P22 R11 R22 V11 V22 W11 W22 N11 R10 T11 U11 Y11 AB13 AB14 AC15 AB19 AB20 AC18 T22 U22 Y22 N22 R23 M17 M16 T12 T21 LFSC/M25 Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VCC12 VCC12 VCC12 VCC12 VCCIO Bank 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 Dual Function Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VCC12 VCC12 VCC12 VCC12 LFSC/M40 VCCIO Bank 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 Dual Function 4-55 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA1, 2 (Cont.) Ball Number U12 U21 AA16 AA17 M14 P12 W12 AA14 AA19 W21 P21 M19 A2 A10 E28 E5 F10 E10 E23 F23 LFSC/M25 Ball Function VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 GND GND NC NC NC NC NC NC VCCIO Bank Dual Function Ball Function VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 GND GND NC NC NC NC NC NC LFSC/M40 VCCIO Bank Dual Function 1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). 2. The LatticeSC/M25 and LatticeSC/M40 in a 1020-pin package support a 16-bit MPI interface. 4-56 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M40 Ball Number G27 H27 H25 H26 B33 C34 D34 C33 J27 K27 M26 L26 F30 G30 H28 J28 F31 G31 N25 P25 D33 E33 H29 J29 F32 G32 P26 N26 H30 J30 L28 M28 J31 K31 L27 M27 J32 K32 L29 M29 H33 J33 N27 P27 K33 Ball Function A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC RESETN TSALLN DONE INITN M0 M1 M2 M3 PL16A PL16B PL16C PL16D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL21A PL21B PL21C PL21D PL22A PL22B PL22C PL22D PL23A PL23B PL23C PL23D PL25A PL25B PL25C PL25D PL26A PL26B PL26C PL26D PL27A VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 VREF1_7 DIFFR_7 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B Dual Function Ball Function A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC RESETN TSALLN DONE INITN M0 M1 M2 M3 PL16A PL16B PL16C PL16D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL20A PL20B PL20C PL20D PL21A PL21B PL21C PL21D PL29A PL29B PL29C PL29D PL31A PL31B PL31C PL31D PL33A PL33B PL33C PL33D PL35A VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 VREF1_7 DIFFR_7 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B LFSC/M80 Dual Function 4-57 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number L33 M30 N30 M31 N31 P24 R24 M33 N33 U25 T25 L34 M34 P29 R29 N34 P34 R27 T27 R32 R31 U24 T24 P33 R33 T26 U26 T32 T31 U29 V29 T30 U30 U27 V27 R34 T34 U28 V28 V30 W30 W27 Y27 T33 U33 Ball Function PL27B PL27C PL27D PL29A PL29B PL29C PL29D PL30A PL30B PL30C PL30D PL31A PL31B PL31C PL31D PL34A PL34B PL34C PL34D PL35A PL35B PL35C PL35D PL36A PL36B PL36C PL36D PL38A PL38B PL38C PL38D PL39A PL39B PL39C PL39D PL40A PL40B PL40C PL40D PL43A PL43B PL43C PL43D PL44A PL44B VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 PCLKC6_3 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 Dual Function Ball Function PL35B PL35C PL35D PL37A PL37B PL37C PL37D PL42A PL42B PL42C PL42D PL43A PL43B PL43C PL43D PL46A PL46B PL46C PL46D PL47A PL47B PL47C PL47D PL48A PL48B PL48C PL48D PL50A PL50B PL50C PL50D PL51A PL51B PL51C PL51D PL52A PL52B PL52C PL52D PL55A PL55B PL55C PL55D PL56A PL56B VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 PCLKC6_3 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 LFSC/M80 Dual Function 4-58 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number V25 W25 U34 V34 V26 W26 V33 W33 V24 W24 W31 Y31 Y29 AA29 Y33 AA33 Y28 AA28 AB32 AC32 AA26 AA27 AB31 AC31 Y24 AA24 AE34 AF34 AB30 AC30 AD33 AE33 AD30 AE30 AE32 AF32 AA25 AB25 AJ34 AK34 AB27 AC27 AF33 AG33 AC29 Ball Function PL44C PL44D PL45A PL45B PL45C PL45D PL47A PL47B PL47C PL47D PL48A PL48B PL48C PL48D PL49A PL49B PL49C PL49D PL51A PL51B PL51C PL51D PL52A PL52B PL52C PL52D PL53A PL53B PL53C PL53D PL56A PL56B PL56C PL56D PL57A PL57B PL57C PL57D PL58A PL58B PL58C PL58D PL60A PL60B PL60C VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 DIFFR_6 Dual Function Ball Function PL56C PL56D PL57A PL57B PL57C PL57D PL60A PL60B PL60C PL60D PL63A PL63B PL63C PL63D PL65A PL65B PL65C PL65D PL76A PL76B PL76C PL76D PL77A PL77B PL77C PL77D PL78A PL78B PL78C PL78D PL80A PL80B PL80C PL80D PL81A PL81B PL81C PL81D PL82A PL82B PL82C PL82D PL84A PL84B PL84C VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 DIFFR_6 LFSC/M80 Dual Function 4-59 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AD29 AE31 AF31 AF30 AF29 AH33 AJ33 AC28 AD28 AH32 AJ32 AD27 AE27 AG34 AH34 AC26 AB26 AK33 AL33 AG30 AH30 AL34 AM34 AJ30 AK30 AJ31 AH31 AD26 AD25 AL32 AL31 AG29 AG28 AF28 AF27 AM33 AN33 AH29 AJ29 AM32 AM31 AG27 AG26 AL29 AL28 Ball Function PL60D PL61A PL61B PL61C PL61D PL62A PL62B PL62C PL62D PL65A PL65B PL65C PL65D PL66A PL66B PL66C PL66D PL67A PL67B PL67C PL67D PL69A PL69B PL69C PL69D PL70A PL70B PL70C PL70D PL71A PL71B PL71C PL71D XRES TEMP PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F VREF2_6 Dual Function Ball Function PL84D PL85A PL85B PL85C PL85D PL86A PL86B PL86C PL86D PL89A PL89B PL89C PL89D PL90A PL90B PL90C PL90D PL91A PL91B PL91C PL91D PL93A PL93B PL93C PL93D PL94A PL94B PL94C PL94D PL95A PL95B PL95C PL95D XRES TEMP PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F VREF2_6 LFSC/M80 Dual Function 4-60 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AH27 AH26 AN32 AP32 AF25 AE25 AN31 AN30 AK29 AK28 AP31 AP30 AD24 AE24 AM29 AM28 AJ27 AJ26 AP29 AP28 AK27 AK26 AN29 AN28 AG25 AG24 AL26 AL25 AG23 AG22 AN27 AN26 AF24 AF23 AP27 AP26 AK25 AK24 AN25 AN24 AE22 AE21 AM26 AM25 AF22 Ball Function PB5C PB5D PB7A PB7B PB7C PB7D PB8A PB8B PB8C PB8D PB9A PB9B PB9C PB9D PB11A PB11B PB11C PB11D PB13A PB13B PB13C PB13D PB15A PB15B PB15C PB15D PB17A PB17B PB17C PB17D PB19A PB19B PB19C PB19D PB22A PB22B PB22C PB22D PB25A PB25B PB25C PB25D PB26A PB26B PB26C VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF1_5 Dual Function Ball Function PB5C PB5D PB7A PB7B PB7C PB7D PB9A PB9B PB9C PB9D PB11A PB11B PB11C PB11D PB13A PB13B PB13C PB13D PB15A PB15B PB15C PB15D PB17A PB17B PB17C PB17D PB19A PB19B PB19C PB19D PB21A PB21B PB21C PB21D PB24A PB24B PB24C PB24D PB27A PB27B PB27C PB27D PB29A PB29B PB29C VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF1_5 LFSC/M80 Dual Function 4-61 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AF21 AN23 AN22 AP23 AP22 AG21 AG20 AP25 AP24 AD21 AD20 AL23 AL22 AH24 AH23 AM23 AM22 AJ24 AJ23 AN21 AN20 AE19 AD19 AK21 AK20 AK23 AK22 AL20 AL19 AG19 AF19 AP21 AP20 AH21 AH20 AM20 AM19 AJ21 AJ20 AK19 AK18 AE18 AD18 AN19 AN18 Ball Function PB26D PB27A PB27B PB29A PB29B PB29C PB29D PB30A PB30B PB30C PB30D PB31A PB31B PB31C PB31D PB33A PB33B PB33C PB33D PB34A PB34B PB34C PB34D PB35A PB35B PB35C PB35D PB37A PB37B PB37C PB37D PB38A PB38B PB38C PB38D PB39A PB39B PB39C PB39D PB41A PB41B PB41C PB41D PB42A PB42B VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 PCLKT5_0 PCLKC5_0 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 Dual Function Ball Function PB29D PB45A PB45B PB55A PB55B PB55C PB55D PB48A PB48B PB48C PB48D PB49A PB49B PB49C PB49D PB51A PB51B PB51C PB51D PB52A PB52B PB52C PB52D PB53A PB53B PB53C PB53D PB56A PB56B PB56C PB56D PB57A PB57B PB57C PB57D PB59A PB59B PB59C PB59D PB60A PB60B PB60C PB60D PB61A PB61B VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 PCLKT5_0 PCLKC5_0 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 LFSC/M80 Dual Function 4-62 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AG18 AF18 AP19 AP18 AJ18 AH18 AP17 AP16 AJ17 AH17 AN17 AN16 AE17 AD17 AK17 AK16 AG17 AF17 AM16 AM15 AJ15 AJ14 AL16 AL15 AG16 AF16 AP15 AP14 AH15 AH14 AN15 AN14 AE16 AD16 AK15 AK14 AG15 AG14 AM13 AM12 AJ12 AJ11 AL13 AL12 AH12 Ball Function PB42C PB42D PB43A PB43B PB43C PB43D PB45A PB45B PB45C PB45D PB46A PB46B PB46C PB46D PB47A PB47B PB47C PB47D PB49A PB49B PB49C PB49D PB50A PB50B PB50C PB50D PB51A PB51B PB51C PB51D PB53A PB53B PB53C PB53D PB54A PB54B PB54C PB54D PB55A PB55B PB55C PB55D PB57A PB57B PB57C VCCIO Bank 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_5 PCLKC4_5 PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 Dual Function Ball Function PB61C PB61D PB63A PB63B PB63C PB63D PB65A PB65B PB65C PB65D PB66A PB66B PB66C PB66D PB67A PB67B PB67C PB67D PB69A PB69B PB69C PB69D PB70A PB70B PB70C PB70D PB71A PB71B PB71C PB71D PB74A PB74B PB74C PB74D PB75A PB75B PB75C PB75D PB77A PB77B PB77C PB77D PB79A PB79B PB79C VCCIO Bank 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_5 PCLKC4_5 PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 LFSC/M80 Dual Function 4-63 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AH11 AN13 AN12 AD14 AD15 AP13 AP12 AK13 AK12 AP11 AP10 AN11 AN10 AF14 AF13 AM10 AM9 AE14 AE13 AP9 AP8 AK11 AK10 AL10 AL9 AF12 AF11 AN9 AN8 AG11 AG10 AP7 AP6 AG13 AG12 AN7 AN6 AK9 AK8 AP5 AP4 AD11 AE11 AM7 AM6 Ball Function PB57D PB58A PB58B PB58C PB58D PB61A PB61B PB61C PB61D PB62A PB62B PB63A PB63B PB63C PB63D PB67A PB67B PB67C PB67D PB69A PB69B PB69C PB69D PB70A PB70B PB70C PB70D PB73A PB73B PB73C PB73D PB74A PB74B PB74C PB74D PB75A PB75B PB75C PB75D PB77A PB77B PB77C PB77D PB78A PB78B VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 Dual Function Ball Function PB79D PB80A PB80B PB80C PB80D PB73A PB73B PB73C PB73D PB83A PB83B PB99A PB99B PB99C PB99D PB101A PB101B PB101C PB101D PB104A PB104B PB104C PB104D PB107A PB107B PB107C PB107D PB109A PB109B PB109C PB109D PB111A PB111B PB111C PB111D PB113A PB113B PB113C PB113D PB115A PB115B PB115C PB115D PB117A PB117B VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 LFSC/M80 Dual Function 4-64 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AJ9 AJ8 AP3 AN3 AF10 AE10 AL7 AL6 AK7 AK6 AN5 AN4 AH9 AH8 AM3 AM4 AG9 AG8 AN2 AM2 AJ6 AH6 AF7 AF8 AG7 AG6 AL4 AL3 AD10 AD9 AH4 AJ4 AK5 AJ5 AM1 AL1 AH5 AG5 AL2 AK2 AB9 AC9 AH1 AG1 AE8 Ball Function PB78C PB78D PB79A PB79B PB79C PB79D PB81A PB81B PB81C PB81D PB82A PB82B PB82C PB82D PB83A PB83B PB83C PB83D PB85A PB85B PB85C PB85D PROBE_VCC PROBE_GND PR71D PR71C PR71B PR71A PR70D PR70C PR70B PR70A PR69D PR69C PR69B PR69A PR67D PR67C PR67B PR67A PR66D PR66C PR66B PR66A PR65D VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF2_3 LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D VREF1_4 Dual Function Ball Function PB117C PB117D PB119A PB119B PB119C PB119D PB121A PB121B PB121C PB121D PB123A PB123B PB123C PB123D PB124A PB124B PB124C PB124D PB125A PB125B PB125C PB125D PROBE_VCC PROBE_GND PR95D PR95C PR95B PR95A PR94D PR94C PR94B PR94A PR93D PR93C PR93B PR93A PR91D PR91C PR91B PR91A PR90D PR90C PR90B PR90A PR89D VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF2_3 LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D VREF1_4 LFSC/M80 Dual Function 4-65 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AD8 AJ3 AH3 AD7 AC7 AJ2 AH2 AF6 AF5 AF4 AE4 AD6 AC6 AG2 AF2 AC8 AB8 AK1 AJ1 AB10 AA10 AF3 AE3 AE5 AD5 AE2 AD2 AC5 AB5 AF1 AE1 AA11 Y11 AC4 AB4 AA8 AA9 AC3 AB3 AA7 Y7 AA2 Y2 AA6 Y6 Ball Function PR65C PR65B PR65A PR62D PR62C PR62B PR62A PR61D PR61C PR61B PR61A PR60D PR60C PR60B PR60A PR58D PR58C PR58B PR58A PR57D PR57C PR57B PR57A PR56D PR56C PR56B PR56A PR53D PR53C PR53B PR53A PR52D PR52C PR52B PR52A PR51D PR51C PR51B PR51A PR49D PR49C PR49B PR49A PR48D PR48C VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 DIFFR_3 Dual Function Ball Function PR89C PR89B PR89A PR86D PR86C PR86B PR86A PR85D PR85C PR85B PR85A PR84D PR84C PR84B PR84A PR82D PR82C PR82B PR82A PR81D PR81C PR81B PR81A PR80D PR80C PR80B PR80A PR78D PR78C PR78B PR78A PR77D PR77C PR77B PR77A PR76D PR76C PR76B PR76A PR65D PR65C PR65B PR65A PR63D PR63C VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 DIFFR_3 LFSC/M80 Dual Function 4-66 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number Y4 W4 W11 V11 W2 V2 W9 V9 V1 U1 W10 V10 U2 T2 Y8 W8 W5 V5 V7 U7 T1 R1 V8 U8 U5 T5 V6 U6 T4 T3 U9 T9 R2 P2 T11 U11 R4 R3 T8 R8 P1 N1 R6 P6 M1 Ball Function PR48B PR48A PR47D PR47C PR47B PR47A PR45D PR45C PR45B PR45A PR44D PR44C PR44B PR44A PR43D PR43C PR43B PR43A PR40D PR40C PR40B PR40A PR39D PR39C PR39B PR39A PR38D PR38C PR38B PR38A PR36D PR36C PR36B PR36A PR35D PR35C PR35B PR35A PR34D PR34C PR34B PR34A PR31D PR31C PR31B VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 PCLKC3_3 PCLKT3_3 PCLKC3_2 PCLKT3_2 VREF1_3 Dual Function Ball Function PR63B PR63A PR60D PR60C PR60B PR60A PR57D PR57C PR57B PR57A PR56D PR56C PR56B PR56A PR55D PR55C PR55B PR55A PR52D PR52C PR52B PR52A PR51D PR51C PR51B PR51A PR50D PR50C PR50B PR50A PR48D PR48C PR48B PR48A PR47D PR47C PR47B PR47A PR46D PR46C PR46B PR46A PR43D PR43C PR43B VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 PCLKC3_3 PCLKT3_3 PCLKC3_2 PCLKT3_2 VREF1_3 LFSC/M80 Dual Function 4-67 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number L1 T10 U10 N2 M2 R11 P11 N4 M4 N5 M5 L2 K2 P8 N8 J2 H2 M6 L6 K3 J3 M8 L8 K4 J4 M7 L7 J5 H5 N9 P9 G3 F3 J6 H6 E2 D2 P10 N10 G4 F4 J7 H7 G5 F5 Ball Function PR31A PR30D PR30C PR30B PR30A PR29D PR29C PR29B PR29A PR27D PR27C PR27B PR27A PR26D PR26C PR26B PR26A PR25D PR25C PR25B PR25A PR23D PR23C PR23B PR23A PR22D PR22C PR22B PR22A PR21D PR21C PR21B PR21A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 DIFFR_2 VREF1_2 Dual Function Ball Function PR43A PR42D PR42C PR42B PR42A PR37D PR37C PR37B PR37A PR35D PR35C PR35B PR35A PR33D PR33C PR33B PR33A PR31D PR31C PR31B PR31A PR29D PR29C PR29B PR29A PR21D PR21C PR21B PR21A PR20D PR20C PR20B PR20A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 DIFFR_2 VREF1_2 LFSC/M80 Dual Function 4-68 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number C2 M9 L9 D1 C1 J8 K8 B2 H9 H10 H8 G8 C3 D3 A3 B3 E5 A4 F6 B4 F7 B5 E6 A5 B6 A6 C6 D4 C7 D5 A7 B7 E7 A8 F8 B8 F9 B9 E8 A9 B10 A10 C10 D6 G10 Ball Function VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R VCC12 A_VDDIB0_R A_HDINP0_R A_HDINN0_R VCC12 A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R VCC12 A_HDOUTP1_R A_HDINN1_R A_HDINP1_R VCC12 A_VDDIB1_R VCC12 A_VDDIB2_R A_HDINP2_R A_HDINN2_R VCC12 A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R VCC12 A_HDOUTP3_R A_HDINN3_R A_HDINP3_R VCC12 A_VDDIB3_R VCC12 VCCIO Bank 1 1 1 PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 3 OUT N PCS 3E0 CH 2 OUT N PCS 3E0 CH 2 OUT P PCS 3E0 CH 2 IN P PCS 3E0 CH 2 IN N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 OUT P PCS 3E0 CH 0 IN P PCS 3E0 CH 0 IN N CFGIRQN/MPI_IRQ_N TDO Dual Function Ball Function VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R VCC12 A_VDDIB0_R A_HDINP0_R A_HDINN0_R VCC12 A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R VCC12 A_HDOUTP1_R A_HDINN1_R A_HDINP1_R VCC12 A_VDDIB1_R VCC12 A_VDDIB2_R A_HDINP2_R A_HDINN2_R VCC12 A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R VCC12 A_HDOUTP3_R A_HDINN3_R A_HDINP3_R VCC12 A_VDDIB3_R VCC12 VCCIO Bank 1 1 1 PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 3 OUT N PCS 3E0 CH 2 OUT N PCS 3E0 CH 2 OUT P PCS 3E0 CH 2 IN P PCS 3E0 CH 2 IN N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 OUT P PCS 3E0 CH 0 IN P PCS 3E0 CH 0 IN N CFGIRQN/MPI_IRQ_N TDO LFSC/M80 Dual Function 4-69 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number D7 E10 F10 K10 A11 D10 B11 D11 B12 L10 A12 F11 E11 G11 D8 G12 D9 E12 F12 K11 A13 D12 B13 D13 B14 L11 A14 F13 E13 G13 E9 L13 J11 H11 M15 M16 F14 G14 L15 L14 D14 E14 L16 K16 G15 Ball Function B_VDDIB0_R B_HDINP0_R B_HDINN0_R VCC12 B_HDOUTP0_R B_VDDOB0_R B_HDOUTN0_R B_VDDOB1_R B_HDOUTN1_R VCC12 B_HDOUTP1_R B_HDINN1_R B_HDINP1_R VCC12 B_VDDIB1_R VCC12 B_VDDIB2_R B_HDINP2_R B_HDINN2_R VCC12 B_HDOUTP2_R B_VDDOB2_R B_HDOUTN2_R B_VDDOB3_R B_HDOUTN3_R VCC12 B_HDOUTP3_R B_HDINN3_R B_HDINP3_R VCC12 B_VDDIB3_R VCC12 B_REFCLKN_R B_REFCLKP_R PT61D PT61C PT59B PT59A PT58D PT58C PT57B PT57A PT55D PT55C PT55B VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 PCS 3E1 CH 3 OUT P PCS 3E1 CH 3 IN N PCS 3E1 CH 3 IN P PCS 3E1 CH 3 OUT N PCS 3E1 CH 2 OUT N PCS 3E1 CH 2 OUT P PCS 3E1 CH 2 IN P PCS 3E1 CH 2 IN N PCS 3E1 CH 1 OUT P PCS 3E1 CH 1 IN N PCS 3E1 CH 1 IN P PCS 3E1 CH 1 OUT N PCS 3E1 CH 0 OUT N PCS 3E1 CH 0 OUT P PCS 3E1 CH 0 IN P PCS 3E1 CH 0 IN N Dual Function Ball Function B_VDDIB0_R B_HDINP0_R B_HDINN0_R VCC12 B_HDOUTP0_R B_VDDOB0_R B_HDOUTN0_R B_VDDOB1_R B_HDOUTN1_R VCC12 B_HDOUTP1_R B_HDINN1_R B_HDINP1_R VCC12 B_VDDIB1_R VCC12 B_VDDIB2_R B_HDINP2_R B_HDINN2_R VCC12 B_HDOUTP2_R B_VDDOB2_R B_HDOUTN2_R B_VDDOB3_R B_HDOUTN3_R VCC12 B_HDOUTP3_R B_HDINN3_R B_HDINP3_R VCC12 B_VDDIB3_R VCC12 B_REFCLKN_R B_REFCLKP_R PT77D PT77C PT77B PT77A PT75D PT75C PT75B PT75A PT74D PT74C PT74B VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 PCS 3E1 CH 3 OUT P PCS 3E1 CH 3 IN N PCS 3E1 CH 3 IN P PCS 3E1 CH 3 OUT N PCS 3E1 CH 2 OUT N PCS 3E1 CH 2 OUT P PCS 3E1 CH 2 IN P PCS 3E1 CH 2 IN N PCS 3E1 CH 1 OUT P PCS 3E1 CH 1 IN N PCS 3E1 CH 1 IN P PCS 3E1 CH 1 OUT N PCS 3E1 CH 0 OUT N PCS 3E1 CH 0 OUT P PCS 3E1 CH 0 IN P PCS 3E1 CH 0 IN N LFSC/M80 Dual Function 4-70 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number F15 K14 K13 B15 A15 J14 H14 A16 B16 J13 H13 D15 E15 J16 J17 D16 E16 H15 H16 C15 C16 L17 K17 E17 F17 G17 H17 A17 B17 G18 H18 E18 F18 J18 J19 C20 C19 K18 L18 D19 E19 H19 H20 A18 B18 Ball Function PT55A PT54D PT54C PT53B PT53A PT51D PT51C PT51B PT51A PT50D PT50C PT50B PT50A PT49D PT49C PT49B PT49A PT47D PT47C PT47B PT47A PT46D PT46C PT46B PT46A PT45D PT45C PT45B PT45A PT43D PT43C PT43B PT43A PT42D PT42C PT42B PT42A PT41D PT41C PT41B PT41A PT39D PT39C PT39B PT39A VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function D5/MPI_DATA5 D4/MPI_DATA4 D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D16/PCLKC1_3/MPI_DATA16 D17/PCLKT1_3/MPI_DATA17 D0/MPI_DATA0 QOUT/CEON VREF2_1 D18/MPI_DATA18 DOUT MCA_DONE_IN D19/PCLKC1_2/MPI_DATA19 D20/PCLKT1_2/MPI_DATA20 MCA_CLK_P1_OUT MCA_CLK_P1_IN D21/PCLKC1_1/MPI_DATA21 D22/PCLKT1_1/MPI_DATA22 MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA D23/MPI_DATA23 DP2/MPI_PAR2 PCLKC1_0 PCLKT1_0/MPI_CLK DP3/PCLKC1_4/MPI_PAR3 D24/PCLKT1_4/MPI_DATA24 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 A3/MPI_ADDR17 A4/MPI_ADDR18 D25/PCLKC1_5/MPI_DATA25 D26/PCLKT1_5/MPI_DATA26 A5/MPI_ADDR19 A6/MPI_ADDR20 D27/MPI_DATA27 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 Ball Function PT74A PT73D PT73C PT73B PT73A PT71D PT71C PT71B PT71A PT70D PT70C PT70B PT70A PT69D PT69C PT69B PT69A PT67D PT67C PT67B PT67A PT66D PT66C PT66B PT66A PT65D PT65C PT65B PT65A PT63D PT63C PT63B PT63A PT61D PT61C PT61B PT61A PT60D PT60C PT60B PT60A PT59D PT59C PT59B PT59A VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LFSC/M80 Dual Function D5/MPI_DATA5 D4/MPI_DATA4 D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D16/PCLKC1_3/MPI_DATA16 D17/PCLKT1_3/MPI_DATA17 D0/MPI_DATA0 QOUT/CEON VREF2_1 D18/MPI_DATA18 DOUT MCA_DONE_IN D19/PCLKC1_2/MPI_DATA19 D20/PCLKT1_2/MPI_DATA20 MCA_CLK_P1_OUT MCA_CLK_P1_IN D21/PCLKC1_1/MPI_DATA21 D22/PCLKT1_1/MPI_DATA22 MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA D23/MPI_DATA23 DP2/MPI_PAR2 PCLKC1_0 PCLKT1_0/MPI_CLK DP3/PCLKC1_4/MPI_PAR3 D24/PCLKT1_4/MPI_DATA24 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 A3/MPI_ADDR17 A4/MPI_ADDR18 D25/PCLKC1_5/MPI_DATA25 D26/PCLKT1_5/MPI_DATA26 A5/MPI_ADDR19 A6/MPI_ADDR20 D27/MPI_DATA27 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 4-71 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number H21 J21 A19 B19 H22 J22 F20 G20 K21 K22 A20 B20 L21 L20 D20 E20 L19 K19 D21 E21 M20 M19 F21 G21 H24 J24 L22 E26 G22 E22 F22 A21 L24 B21 D22 B22 D23 A22 K24 F23 E23 D26 G23 D27 G24 Ball Function PT38D PT38C PT38B PT38A PT37D PT37C PT37B PT37A PT35D PT35C PT35B PT35A PT33D PT33C PT33B PT33A PT30D PT30C PT30B PT30A PT28D PT28C PT27B PT27A B_REFCLKP_L B_REFCLKN_L VCC12 B_VDDIB3_L VCC12 B_HDINP3_L B_HDINN3_L B_HDOUTP3_L VCC12 B_HDOUTN3_L B_VDDOB3_L B_HDOUTN2_L B_VDDOB2_L B_HDOUTP2_L VCC12 B_HDINN2_L B_HDINP2_L B_VDDIB2_L VCC12 B_VDDIB1_L VCC12 VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCS 361 CH 2 IN N PCS 361 CH 2 IN P PCS 361 CH 2 OUT P PCS 361 CH 2 OUT N PCS 361 CH 3 OUT N PCS 361 CH 3 IN P PCS 361 CH 3 IN N PCS 361 CH 3 OUT P Dual Function D28/PCLKC1_6/MPI_DATA28 D29/PCLKT1_6/MPI_DATA29 A9/MPI_ADDR23 A10/MPI_ADDR24 D30/PCLKC1_7/MPI_DATA30 D31/PCLKT1_7/MPI_DATA31 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 Ball Function PT57D PT57C PT57B PT57A PT56D PT56C PT56B PT56A PT55D PT55C PT55B PT55A PT53D PT53C PT53B PT53A PT52D PT52C PT52B PT52A PT51D PT51C PT51B PT51A B_REFCLKP_L B_REFCLKN_L VCC12 B_VDDIB3_L VCC12 B_HDINP3_L B_HDINN3_L B_HDOUTP3_L VCC12 B_HDOUTN3_L B_VDDOB3_L B_HDOUTN2_L B_VDDOB2_L B_HDOUTP2_L VCC12 B_HDINN2_L B_HDINP2_L B_VDDIB2_L VCC12 B_VDDIB1_L VCC12 VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCS 361 CH 2 IN N PCS 361 CH 2 IN P PCS 361 CH 2 OUT P PCS 361 CH 2 OUT N PCS 361 CH 3 OUT N PCS 361 CH 3 IN P PCS 361 CH 3 IN N PCS 361 CH 3 OUT P LFSC/M80 Dual Function D28/PCLKC1_6/MPI_DATA28 D29/PCLKT1_6/MPI_DATA29 A9/MPI_ADDR23 A10/MPI_ADDR24 D30/PCLKC1_7/MPI_DATA30 D31/PCLKT1_7/MPI_DATA31 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 4-72 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number E24 F24 A23 L25 B23 D24 B24 D25 A24 K25 F25 E25 D28 G25 D29 C25 A25 B25 A26 E27 B26 F26 B27 F27 A27 E28 B28 A28 D30 C28 D31 C29 A29 B29 A30 E29 B30 F28 B31 F29 A31 E30 B32 A32 D32 Ball Function B_HDINP1_L B_HDINN1_L B_HDOUTP1_L VCC12 B_HDOUTN1_L B_VDDOB1_L B_HDOUTN0_L B_VDDOB0_L B_HDOUTP0_L VCC12 B_HDINN0_L B_HDINP0_L B_VDDIB0_L VCC12 A_VDDIB3_L VCC12 A_HDINP3_L A_HDINN3_L A_HDOUTP3_L VCC12 A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L VCC12 A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCC12 A_VDDIB1_L VCC12 A_HDINP1_L A_HDINN1_L A_HDOUTP1_L VCC12 A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L VCC12 A_HDINN0_L A_HDINP0_L A_VDDIB0_L VCCIO Bank PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT P PCS 360 CH 0 OUT N PCS 360 CH 1 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT P PCS 360 CH 2 OUT N PCS 360 CH 3 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P PCS 361 CH 0 IN N PCS 361 CH 0 IN P PCS 361 CH 0 OUT P PCS 361 CH 0 OUT N PCS 361 CH 1 OUT N Dual Function PCS 361 CH 1 IN P PCS 361 CH 1 IN N PCS 361 CH 1 OUT P Ball Function B_HDINP1_L B_HDINN1_L B_HDOUTP1_L VCC12 B_HDOUTN1_L B_VDDOB1_L B_HDOUTN0_L B_VDDOB0_L B_HDOUTP0_L VCC12 B_HDINN0_L B_HDINP0_L B_VDDIB0_L VCC12 A_VDDIB3_L VCC12 A_HDINP3_L A_HDINN3_L A_HDOUTP3_L VCC12 A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L VCC12 A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCC12 A_VDDIB1_L VCC12 A_HDINP1_L A_HDINN1_L A_HDOUTP1_L VCC12 A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L VCC12 A_HDINN0_L A_HDINP0_L A_VDDIB0_L VCCIO Bank PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT P PCS 360 CH 0 OUT N PCS 360 CH 1 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT P PCS 360 CH 2 OUT N PCS 360 CH 3 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P PCS 361 CH 0 IN N PCS 361 CH 0 IN P PCS 361 CH 0 OUT P PCS 361 CH 0 OUT N PCS 361 CH 1 OUT N LFSC/M80 Dual Function PCS 361 CH 1 IN P PCS 361 CH 1 IN N PCS 361 CH 1 OUT P 4-73 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number C32 E34 F34 F33 G33 K30 L30 G34 H34 M32 N32 P28 R28 J34 K34 P30 R30 W34 Y34 W32 Y32 AA34 AB34 AC34 AD34 Y30 AA30 AB33 AC33 AC2 AB2 AA5 Y5 AD1 AC1 AB1 AA1 Y3 W3 Y1 W1 R5 P5 K1 J1 Ball Function VCC12 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIO Bank Dual Function Ball Function VCC12 PL22A PL22B PL24A PL24B PL25A PL25B PL26A PL26B PL39A PL39B PL39C PL39D PL41A PL41B PL41C PL41D PL59A PL59B PL61A PL61B PL64A PL64B PL67A PL67B PL68A PL68B PL69A PL69B PR69B PR69A PR68B PR68A PR67B PR67A PR64B PR64A PR61B PR61A PR59B PR59A PR41D PR41C PR41B PR41A VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 LFSC/M80 Dual Function 4-74 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number R7 P7 N3 M3 H1 G1 L5 K5 G2 F2 F1 E1 A2 A33 AA15 AA20 AA32 AA4 AB28 AB6 AC11 AC18 AC25 AD23 AD3 AD31 AE12 AE15 AE29 AE7 AE9 AF20 AF26 AG32 AG4 AH13 AH19 AH25 AH7 AJ10 AJ16 AJ22 AJ28 AK3 AK31 Ball Function NC NC NC NC NC NC NC NC NC NC NC NC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function PR39D PR39C PR39B PR39A PR26B PR26A PR25B PR25A PR24B PR24A PR22B PR22A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 LFSC/M80 Dual Function 4-75 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AL11 AL17 AL21 AL27 AL5 AM14 AM18 AM24 AM30 AM8 AN1 AN34 AP2 AP33 B1 B34 C11 C12 C13 C14 C17 C21 C22 C23 C24 C26 C27 C30 C31 C4 C5 C8 C9 D18 E32 E4 F19 G16 G29 G7 H3 H31 J10 J15 J26 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M80 Dual Function 4-76 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number K20 K23 K26 K28 K6 K9 L12 L32 L4 M10 M17 M24 N29 N7 P15 P20 P3 P31 R10 R14 R16 R19 R21 R26 T15 T17 T18 T20 T28 T6 U16 U19 U23 U32 U4 V12 V16 V19 V3 V31 W15 W17 W18 W20 W29 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M80 Dual Function 4-77 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number W7 AA14 AA16 AA17 AA18 AA19 AA21 AB13 AB22 N13 N22 P14 P16 P17 P18 P19 P21 R15 R17 R18 R20 T14 T16 T19 T21 U14 U15 U17 U18 U20 U21 V14 V15 V17 V18 V20 V21 W14 W16 W19 W21 Y15 Y17 Y18 Y20 Ball Function GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank Dual Function Ball Function GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank LFSC/M80 Dual Function 4-78 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AB15 AB20 N15 N20 R13 R22 Y13 Y22 AA12 AA23 AB12 AB16 AB17 AB18 AB19 AB23 AC12 AC13 Y19 AC14 AC17 AC21 AC22 AC23 M13 M14 M18 M21 M22 N12 N16 N17 N18 N19 N23 P12 P23 T13 T22 U12 U13 U22 V13 V22 V23 Ball Function VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO Bank Dual Function Ball Function VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO Bank LFSC/M80 Dual Function 4-79 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number W13 W22 Y21 Y25 C18 D17 F16 G19 J20 K12 K15 L23 Y9 J9 E3 G6 H4 K7 L3 M11 N6 P4 R9 AA3 AB7 AC10 AD4 AE6 AG3 AK4 T7 U3 V4 W6 Y10 AD12 AF15 AF9 AH10 AH16 AJ13 AJ7 AL14 AL8 AM11 Ball Function VCCAUX VCCAUX GND GND VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 GND VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO Bank Dual Function Ball Function VCCAUX VCCAUX GND GND VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 GND VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO Bank LFSC/M80 Dual Function 4-80 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AM17 AM5 AE20 AE23 AE26 AH22 AH28 AJ19 AJ25 AL18 AL24 AL30 AM21 AM27 AA31 AB29 AC24 AD32 AE28 AG31 AK32 T29 U31 V32 W28 Y26 E31 G28 H32 K29 L31 M25 N28 P32 R25 J25 N11 R12 T12 AB11 W12 Y12 AC15 AC16 AD13 Ball Function VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO1 VTT_2 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VCCIO Bank 2 2 2 3 3 3 4 4 4 Dual Function Ball Function VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO1 VTT_2 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VCCIO Bank 2 2 2 3 3 3 4 4 4 LFSC/M80 Dual Function 4-81 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA1, 2 (Cont.) LFSC/M40 Ball Number AC19 AC20 AD22 AB24 W23 Y23 N24 R23 T23 M12 M23 Y16 Y14 N21 P22 AA22 AB21 AB14 AA13 P13 N14 G26 G9 J12 H12 H23 J23 Ball Function VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VTT_7 VDDAX25_R VDDAX25_L GND GND VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 NC NC NC NC NC NC VCCIO Bank 5 5 5 6 6 6 7 7 7 Dual Function Ball Function VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VTT_7 VDDAX25_R VDDAX25_L GND GND VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 NC NC NC NC NC NC VCCIO Bank 5 5 5 6 6 6 7 7 7 LFSC/M80 Dual Function 1. Differential pair grouping within a PCI is A (True) and B (complement) and C (True) and D (Complement). 2. The LatticeSC/M40 and LatticeSC/M80 in an 1152-pin package support a 32-bit MPI interface. 4-82 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number G27 H27 H25 H26 B33 C34 D34 C33 J27 K27 M26 L26 F30 G30 H28 J28 F31 G31 N25 P25 D33 E33 H29 J29 F32 G32 P26 N26 H30 J30 L28 M28 J31 K31 L27 M27 J32 K32 L29 M29 H33 J33 Ball Function A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC RESETN TSALLN DONE INITN M0 M1 M2 M3 PL15A PL15B PL15C PL15D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL19A PL19B PL19C PL19D PL26A PL26B PL26C PL26D PL43A PL43B PL43C PL43D PL45A PL45B PL45C PL45D PL47A PL47B VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 VREF1_7 DIFFR_7 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B Dual Function 4-83 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number N27 P27 K33 L33 M30 N30 M31 N31 P24 R24 M33 N33 U25 T25 L34 M34 P29 R29 N34 P34 R27 T27 R32 R31 U24 T24 P33 R33 T26 U26 T32 T31 U29 V29 T30 U30 U27 V27 R34 T34 U28 V28 V30 Ball Function PL47C PL47D PL49A PL49B PL49C PL49D PL51A PL51B PL51C PL51D PL56A PL56B PL56C PL56D PL57A PL57B PL57C PL57D PL60A PL60B PL60C PL60D PL61A PL61B PL61C PL61D PL62A PL62B PL62C PL62D PL64A PL64B PL64C PL64D PL65A PL65B PL65C PL65D PL66A PL66B PL66C PL66D PL69A VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 PCLKT6_2 PCLKC6_2 PCLKT6_3 PCLKC6_3 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 Dual Function 4-84 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number W30 W27 Y27 T33 U33 V25 W25 U34 V34 V26 W26 V33 W33 V24 W24 W31 Y31 Y29 AA29 Y33 AA33 Y28 AA28 AB32 AC32 AA26 AA27 AB31 AC31 Y24 AA24 AE34 AF34 AB30 AC30 AD33 AE33 AD30 AE30 AE32 AF32 AA25 AB25 Ball Function PL69B PL69C PL69D PL70A PL70B PL70C PL70D PL71A PL71B PL71C PL71D PL74A PL74B PL74C PL74D PL77A PL77B PL77C PL77D PL79A PL79B PL79C PL79D PL90A PL90B PL90C PL90D PL91A PL91B PL91C PL91D PL92A PL92B PL92C PL92D PL94A PL94B PL94C PL94D PL96A PL96B PL96C PL96D VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 DIFFR_6 VREF1_6 Dual Function 4-85 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AJ34 AK34 AB27 AC27 AF33 AG33 AC29 AD29 AE31 AF31 AF30 AF29 AH33 AJ33 AC28 AD28 AH32 AJ32 AD27 AE27 AG34 AH34 AC26 AB26 AK33 AL33 AG30 AH30 AL34 AM34 AJ30 AK30 AJ31 AH31 AD26 AD25 AL32 AL31 AG29 AG28 AF28 AF27 AM33 Ball Function PL98A PL98B PL98C PL98D PL99A PL99B PL99C PL99D PL103A PL103B PL103C PL103D PL104A PL104B PL104C PL104D PL107A PL107B PL107C PL107D PL109A PL109B PL109C PL109D PL112A PL112B PL112C PL112D PL115A PL115B PL115C PL115D PL116A PL116B PL116C PL116D PL117A PL117B PL117C PL117D XRES TEMP PB3A VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F VREF2_6 Dual Function 4-86 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AN33 AH29 AJ29 AM32 AM31 AG27 AG26 AL29 AL28 AH27 AH26 AN32 AP32 AF25 AE25 AN31 AN30 AK29 AK28 AP31 AP30 AD24 AE24 AM29 AM28 AJ27 AJ26 AP29 AP28 AK27 AK26 AN29 AN28 AG25 AG24 AL26 AL25 AG23 AG22 AN27 AN26 AF24 AF23 Ball Function PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D PB7A PB7B PB7C PB7D PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D PB15A PB15B PB15C PB15D PB16A PB16B PB16C PB16D PB19A PB19B PB19C PB19D PB20A PB20B PB20C PB20D PB23A PB23B PB23C PB23D VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF1_5 Dual Function LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C 4-87 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AP27 AP26 AK25 AK24 AN25 AN24 AE22 AE21 AM26 AM25 AF22 AF21 AN23 AN22 AP23 AP22 AG21 AG20 AP25 AP24 AD21 AD20 AL23 AL22 AH24 AH23 AM23 AM22 AJ24 AJ23 AN21 AN20 AE19 AD19 AK21 AK20 AK23 AK22 AL20 AL19 AG19 AF19 AP21 Ball Function PB26A PB26B PB26C PB26D PB29A PB29B PB29C PB29D PB31A PB31B PB31C PB31D PB47A PB47B PB57A PB57B PB57C PB57D PB50A PB50B PB50C PB50D PB51A PB51B PB51C PB51D PB53A PB53B PB53C PB53D PB54A PB54B PB54C PB54D PB55A PB55B PB55C PB55D PB58A PB58B PB58C PB58D PB61A VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 PCLKT5_0 PCLKC5_0 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 Dual Function 4-88 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AP20 AH21 AH20 AM20 AM19 AJ21 AJ20 AK19 AK18 AE18 AD18 AN19 AN18 AG18 AF18 AP19 AP18 AJ18 AH18 AP17 AP16 AJ17 AH17 AN17 AN16 AE17 AD17 AK17 AK16 AG17 AF17 AM16 AM15 AJ15 AJ14 AL16 AL15 AG16 AF16 AP15 AP14 AH15 AH14 Ball Function PB61B PB61C PB61D PB63A PB63B PB63C PB63D PB66A PB66B PB66C PB66D PB69A PB69B PB69C PB69D PB71A PB71B PB71C PB71D PB73A PB73B PB73C PB73D PB75A PB75B PB75C PB75D PB78A PB78B PB78C PB78D PB81A PB81B PB81C PB81D PB83A PB83B PB83C PB83D PB86A PB86B PB86C PB86D VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Dual Function 4-89 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AN15 AN14 AE16 AD16 AK15 AK14 AG15 AG14 AM13 AM12 AJ12 AJ11 AL13 AL12 AH12 AH11 AN13 AN12 AD14 AD15 AP13 AP12 AK13 AK12 AP11 AP10 AN11 AN10 AF14 AF13 AM10 AM9 AE14 AE13 AP9 AP8 AK11 AK10 AL10 AL9 AF12 AF11 AN9 Ball Function PB89A PB89B PB89C PB89D PB90A PB90B PB90C PB90D PB91A PB91B PB91C PB91D PB93A PB93B PB93C PB93D PB94A PB94B PB94C PB94D PB87A PB87B PB87C PB87D PB97A PB97B PB113A PB113B PB113C PB113D PB115A PB115B PB115C PB115D PB118A PB118B PB118C PB118D PB121A PB121B PB121C PB121D PB123A VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 PCLKT4_5 PCLKC4_5 Dual Function PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 4-90 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AN8 AG11 AG10 AP7 AP6 AG13 AG12 AN7 AN6 AK9 AK8 AP5 AP4 AD11 AE11 AM7 AM6 AJ9 AJ8 AP3 AN3 AF10 AE10 AL7 AL6 AK7 AK6 AN5 AN4 AH9 AH8 AM3 AM4 AG9 AG8 AN2 AM2 AJ6 AH6 AF7 AF8 AG7 AG6 Ball Function PB123B PB123C PB123D PB125A PB125B PB125C PB125D PB127A PB127B PB127C PB127D PB129A PB129B PB129C PB129D PB131A PB131B PB131C PB131D PB133A PB133B PB133C PB133D PB135A PB135B PB135C PB135D PB138A PB138B PB138C PB138D PB139A PB139B PB139C PB139D PB141A PB141B PB141C PB141D PROBE_VCC PROBE_GND PR117D PR117C VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D VREF1_4 Dual Function 4-91 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AL4 AL3 AD10 AD9 AH4 AJ4 AK5 AJ5 AM1 AL1 AH5 AG5 AL2 AK2 AB9 AC9 AH1 AG1 AE8 AD8 AJ3 AH3 AD7 AC7 AJ2 AH2 AF6 AF5 AF4 AE4 AD6 AC6 AG2 AF2 AC8 AB8 AK1 AJ1 AB10 AA10 AF3 AE3 AE5 Ball Function PR117B PR117A PR116D PR116C PR116B PR116A PR115D PR115C PR115B PR115A PR112D PR112C PR112B PR112A PR109D PR109C PR109B PR109A PR107D PR107C PR107B PR107A PR104D PR104C PR104B PR104A PR103D PR103C PR103B PR103A PR99D PR99C PR99B PR99A PR98D PR98C PR98B PR98A PR96D PR96C PR96B PR96A PR94D VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 VREF2_3 LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F Dual Function LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E 4-92 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AD5 AE2 AD2 AC5 AB5 AF1 AE1 AA11 Y11 AC4 AB4 AA8 AA9 AC3 AB3 AA7 Y7 AA2 Y2 AA6 Y6 Y4 W4 W11 V11 W2 V2 W9 V9 V1 U1 W10 V10 U2 T2 Y8 W8 W5 V5 V7 U7 T1 R1 Ball Function PR94C PR94B PR94A PR92D PR92C PR92B PR92A PR91D PR91C PR91B PR91A PR90D PR90C PR90B PR90A PR79D PR79C PR79B PR79A PR77D PR77C PR77B PR77A PR74D PR74C PR74B PR74A PR71D PR71C PR71B PR71A PR70D PR70C PR70B PR70A PR69D PR69C PR69B PR69A PR66D PR66C PR66B PR66A VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 PCLKC3_2 PCLKT3_2 VREF1_3 DIFFR_3 Dual Function 4-93 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number V8 U8 U5 T5 V6 U6 T4 T3 U9 T9 R2 P2 T11 U11 R4 R3 T8 R8 P1 N1 R6 P6 M1 L1 T10 U10 N2 M2 R11 P11 N4 M4 N5 M5 L2 K2 P8 N8 J2 H2 M6 L6 K3 Ball Function PR65D PR65C PR65B PR65A PR64D PR64C PR64B PR64A PR62D PR62C PR62B PR62A PR61D PR61C PR61B PR61A PR60D PR60C PR60B PR60A PR57D PR57C PR57B PR57A PR56D PR56C PR56B PR56A PR51D PR51C PR51B PR51A PR49D PR49C PR49B PR49A PR47D PR47C PR47B PR47A PR45D PR45C PR45B VCCIO Bank 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 Dual Function PCLKC3_3 PCLKT3_3 4-94 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number J3 M8 L8 K4 J4 M7 L7 J5 H5 N9 P9 G3 F3 J6 H6 E2 D2 P10 N10 G4 F4 J7 H7 G5 F5 C2 M9 L9 D1 C1 J8 K8 B2 H9 H10 H8 G8 C3 D3 A3 B3 E5 A4 Ball Function PR45A PR43D PR43C PR43B PR43A PR26D PR26C PR26B PR26A PR19D PR19C PR19B PR19A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR15D PR15C PR15B PR15A VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R VCC12 A_VDDIB0_R A_HDINP0_R A_HDINN0_R VCC12 A_HDOUTP0_R VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 PCS 3E0 CH 0 OUT P PCS 3E0 CH 0 IN P PCS 3E0 CH 0 IN N CFGIRQN/MPI_IRQ_N TDO URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 DIFFR_2 VREF1_2 Dual Function 4-95 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number F6 B4 F7 B5 E6 A5 B6 A6 C6 D4 C7 D5 A7 B7 E7 A8 F8 B8 F9 B9 E8 A9 B10 A10 C10 D6 G10 D7 E10 F10 K10 A11 D10 B11 D11 B12 L10 A12 F11 E11 G11 D8 G12 Ball Function A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R VCC12 A_HDOUTP1_R A_HDINN1_R A_HDINP1_R VCC12 A_VDDIB1_R VCC12 A_VDDIB2_R A_HDINP2_R A_HDINN2_R VCC12 A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R VCC12 A_HDOUTP3_R A_HDINN3_R A_HDINP3_R VCC12 A_VDDIB3_R VCC12 B_VDDIB0_R B_HDINP0_R B_HDINN0_R VCC12 B_HDOUTP0_R B_VDDOB0_R B_HDOUTN0_R B_VDDOB1_R B_HDOUTN1_R VCC12 B_HDOUTP1_R B_HDINN1_R B_HDINP1_R VCC12 B_VDDIB1_R VCC12 VCCIO Bank PCS 3E1 CH 1 OUT P PCS 3E1 CH 1 IN N PCS 3E1 CH 1 IN P PCS 3E1 CH 1 OUT N PCS 3E1 CH 0 OUT N PCS 3E1 CH 0 OUT P PCS 3E1 CH 0 IN P PCS 3E1 CH 0 IN N PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 3 OUT N PCS 3E0 CH 2 OUT N PCS 3E0 CH 2 OUT P PCS 3E0 CH 2 IN P PCS 3E0 CH 2 IN N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 0 OUT N Dual Function 4-96 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number D9 E12 F12 K11 A13 D12 B13 D13 B14 L11 A14 F13 E13 G13 E9 L13 J11 H11 M15 M16 F14 G14 L15 L14 D14 E14 L16 K16 G15 F15 K14 K13 B15 A15 J14 H14 A16 B16 J13 H13 D15 E15 J16 Ball Function B_VDDIB2_R B_HDINP2_R B_HDINN2_R VCC12 B_HDOUTP2_R B_VDDOB2_R B_HDOUTN2_R B_VDDOB3_R B_HDOUTN3_R VCC12 B_HDOUTP3_R B_HDINN3_R B_HDINP3_R VCC12 B_VDDIB3_R VCC12 B_REFCLKN_R B_REFCLKP_R PT93D PT93C PT93B PT93A PT90D PT90C PT90B PT90A PT89D PT89C PT89B PT89A PT87D PT87C PT87B PT87A PT86D PT86C PT86B PT86A PT83D PT83C PT83B PT83A PT81D VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D16/PCLKC1_3/MPI_DATA16 D17/PCLKT1_3/MPI_DATA17 D0/MPI_DATA0 QOUT/CEON VREF2_1 D18/MPI_DATA18 DOUT MCA_DONE_IN D19/PCLKC1_2/MPI_DATA19 PCS 3E1 CH 3 OUT P PCS 3E1 CH 3 IN N PCS 3E1 CH 3 IN P PCS 3E1 CH 3 OUT N PCS 3E1 CH 2 OUT N PCS 3E1 CH 2 OUT P PCS 3E1 CH 2 IN P PCS 3E1 CH 2 IN N Dual Function 4-97 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number J17 D16 E16 H15 H16 C15 C16 L17 K17 E17 F17 G17 H17 A17 B17 G18 H18 E18 F18 J18 J19 C20 C19 K18 L18 D19 E19 H19 H20 A18 B18 H21 J21 A19 B19 H22 J22 F20 G20 K21 K22 A20 B20 Ball Function PT81C PT81B PT81A PT78D PT78C PT78B PT78A PT75D PT75C PT75B PT75A PT73D PT73C PT73B PT73A PT71D PT71C PT71B PT71A PT69D PT69C PT69B PT69A PT66D PT66C PT66B PT66A PT63D PT63C PT63B PT63A PT61D PT61C PT61B PT61A PT58D PT58C PT58B PT58A PT57D PT57C PT57B PT57A VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function D20/PCLKT1_2/MPI_DATA20 MCA_CLK_P1_OUT MCA_CLK_P1_IN D21/PCLKC1_1/MPI_DATA21 D22/PCLKT1_1/MPI_DATA22 MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA D23/MPI_DATA23 DP2/MPI_PAR2 PCLKC1_0 PCLKT1_0/MPI_CLK DP3/PCLKC1_4/MPI_PAR3 D24/PCLKT1_4/MPI_DATA24 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 A3/MPI_ADDR17 A4/MPI_ADDR18 D25/PCLKC1_5/MPI_DATA25 D26/PCLKT1_5/MPI_DATA26 A5/MPI_ADDR19 A6/MPI_ADDR20 D27/MPI_DATA27 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 D28/PCLKC1_6/MPI_DATA28 D29/PCLKT1_6/MPI_DATA29 A9/MPI_ADDR23 A10/MPI_ADDR24 D30/PCLKC1_7/MPI_DATA30 D31/PCLKT1_7/MPI_DATA31 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 4-98 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number L21 L20 D20 E20 L19 K19 D21 E21 M20 M19 F21 G21 H24 J24 L22 E26 G22 E22 F22 A21 L24 B21 D22 B22 D23 A22 K24 F23 E23 D26 G23 D27 G24 E24 F24 A23 L25 B23 D24 B24 D25 A24 K25 Ball Function PT55D PT55C PT55B PT55A PT54D PT54C PT54B PT54A PT51D PT51C PT51B PT51A B_REFCLKP_L B_REFCLKN_L VCC12 B_VDDIB3_L VCC12 B_HDINP3_L B_HDINN3_L B_HDOUTP3_L VCC12 B_HDOUTN3_L B_VDDOB3_L B_HDOUTN2_L B_VDDOB2_L B_HDOUTP2_L VCC12 B_HDINN2_L B_HDINP2_L B_VDDIB2_L VCC12 B_VDDIB1_L VCC12 B_HDINP1_L B_HDINN1_L B_HDOUTP1_L VCC12 B_HDOUTN1_L B_VDDOB1_L B_HDOUTN0_L B_VDDOB0_L B_HDOUTP0_L VCC12 VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 PCS 361 CH 0 OUT P PCS 361 CH 0 OUT N PCS 361 CH 1 OUT N PCS 361 CH 1 IN P PCS 361 CH 1 IN N PCS 361 CH 1 OUT P PCS 361 CH 2 IN N PCS 361 CH 2 IN P PCS 361 CH 2 OUT P PCS 361 CH 2 OUT N PCS 361 CH 3 OUT N PCS 361 CH 3 IN P PCS 361 CH 3 IN N PCS 361 CH 3 OUT P Dual Function A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 4-99 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number F25 E25 D28 G25 D29 C25 A25 B25 A26 E27 B26 F26 B27 F27 A27 E28 B28 A28 D30 C28 D31 C29 A29 B29 A30 E29 B30 F28 B31 F29 A31 E30 B32 A32 D32 C32 E34 F34 F33 G33 K30 L30 G34 Ball Function B_HDINN0_L B_HDINP0_L B_VDDIB0_L VCC12 A_VDDIB3_L VCC12 A_HDINP3_L A_HDINN3_L A_HDOUTP3_L VCC12 A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L VCC12 A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCC12 A_VDDIB1_L VCC12 A_HDINP1_L A_HDINN1_L A_HDOUTP1_L VCC12 A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L VCC12 A_HDINN0_L A_HDINP0_L A_VDDIB0_L VCC12 PL30A PL30B PL34A PL34B PL38A PL38B PL40A VCCIO Bank 7 7 7 7 7 7 7 PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT P PCS 360 CH 0 OUT N PCS 360 CH 1 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT P PCS 360 CH 2 OUT N PCS 360 CH 3 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P Dual Function PCS 361 CH 0 IN N PCS 361 CH 0 IN P 4-100 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number H34 M32 N32 P28 R28 J34 K34 P30 R30 W34 Y34 W32 Y32 AA34 AB34 AC34 AD34 Y30 AA30 AB33 AC33 AC2 AB2 AA5 Y5 AD1 AC1 AB1 AA1 Y3 W3 Y1 W1 R5 P5 K1 J1 R7 P7 N3 M3 H1 G1 Ball Function PL40B PL53A PL53B PL53C PL53D PL55A PL55B PL55C PL55D PL73A PL73B PL75A PL75B PL78A PL78B PL81A PL81B PL82A PL82B PL83A PL83B PR83B PR83A PR82B PR82A PR81B PR81A PR78B PR78A PR75B PR75A PR73B PR73A PR55D PR55C PR55B PR55A PR53D PR53C PR53B PR53A PR40B PR40A VCCIO Bank 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 Dual Function 4-101 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number L5 K5 G2 F2 F1 E1 A2 A33 AA15 AA20 AA32 AA4 AB28 AB6 AC11 AC18 AC25 AD23 AD3 AD31 AE12 AE15 AE29 AE7 AE9 AF20 AF26 AG32 AG4 AH13 AH19 AH25 AH7 AJ10 AJ16 AJ22 AJ28 AK3 AK31 AL11 AL17 AL21 AL27 Ball Function PR38B PR38A PR34B PR34A PR30B PR30A GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank 2 2 2 2 2 2 Dual Function 4-102 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AL5 AM14 AM18 AM24 AM30 AM8 AN1 AN34 AP2 AP33 B1 B34 C11 C12 C13 C14 C17 C21 C22 C23 C24 C26 C27 C30 C31 C4 C5 C8 C9 D18 E32 E4 F19 G16 G29 G7 H3 H31 J10 J15 J26 K20 K23 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function 4-103 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number K26 K28 K6 K9 L12 L32 L4 M10 M17 M24 N29 N7 P15 P20 P3 P31 R10 R14 R16 R19 R21 R26 T15 T17 T18 T20 T28 T6 U16 U19 U23 U32 U4 V12 V16 V19 V3 V31 W15 W17 W18 W20 W29 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function 4-104 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number W7 AA14 AA16 AA17 AA18 AA19 AA21 AB13 AB22 N13 N22 P14 P16 P17 P18 P19 P21 R15 R17 R18 R20 T14 T16 T19 T21 U14 U15 U17 U18 U20 U21 V14 V15 V17 V18 V20 V21 W14 W16 W19 W21 Y15 Y17 Ball Function GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank Dual Function 4-105 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number Y18 Y20 AB15 AB20 N15 N20 R13 R22 Y13 Y22 AA12 AA23 AB12 AB16 AB17 AB18 AB19 AB23 AC12 AC13 Y19 AC14 AC17 AC21 AC22 AC23 M13 M14 M18 M21 M22 N12 N16 N17 N18 N19 N23 P12 P23 T13 T22 U12 U13 Ball Function VCC VCC VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO Bank Dual Function 4-106 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number U22 V13 V22 V23 W13 W22 Y21 Y25 C18 D17 F16 G19 J20 K12 K15 L23 Y9 J9 E3 G6 H4 K7 L3 M11 N6 P4 R9 AA3 AB7 AC10 AD4 AE6 AG3 AK4 T7 U3 V4 W6 Y10 AD12 AF15 AF9 AH10 Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX GND GND VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 GND VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO Bank Dual Function 4-107 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number AH16 AJ13 AJ7 AL14 AL8 AM11 AM17 AM5 AE20 AE23 AE26 AH22 AH28 AJ19 AJ25 AL18 AL24 AL30 AM21 AM27 AA31 AB29 AC24 AD32 AE28 AG31 AK32 T29 U31 V32 W28 Y26 E31 G28 H32 K29 L31 M25 N28 P32 R25 J25 N11 Ball Function VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO1 VTT_2 VCCIO Bank 2 Dual Function 4-108 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M115 Logic Signal Connections: 1152 fcBGA1, 2 LFSC/M115 Ball Number R12 T12 AB11 W12 Y12 AC15 AC16 AD13 AC19 AC20 AD22 AB24 W23 Y23 N24 R23 T23 M12 M23 Y16 Y14 N21 P22 AA22 AB21 AB14 AA13 P13 N14 G26 G9 J12 H12 H23 J23 Ball Function VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VTT_7 VDDAX25_R VDDAX25_L GND GND VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 NC NC NC NC NC NC VCCIO Bank 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 Dual Function 1. Differential pair grouping within a PCI is A (True) and B (complement) and C (True) and D (Complement). 2. The LatticeSC/M115 in an 1152-pin package supports a 32-bit MPI interface. 4-109 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 LFSC/M80 Ball Number G34 H34 N30 H33 P25 P26 P31 P23 P30 P22 P24 R22 J37 J38 P32 R32 G40 H40 N33 P33 G41 H41 T29 U29 G42 H42 M34 M35 K37 L37 N34 P34 K38 L38 T33 R33 J41 K41 U31 V31 K42 J42 J36 K36 N38 Ball Function A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC RESETN TSALLN DONE INITN M0 M1 M2 M3 PL16A PL16B PL16C PL16D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL20A PL20B PL20C PL20D PL21A PL21B PL21C PL21D PL22A PL22B PL22C PL22D PL24A PL24B PL24C PL24D PL25A PL25B PL25C PL25D PL26A VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B Dual Function Ball Function A_REFCLKP_L A_REFCLKN_L VCC12 RESP_ULC RESETN TSALLN DONE INITN M0 M1 M2 M3 PL15A PL15B PL15C PL15D PL17A PL17B PL17C PL17D PL18A PL18B PL18C PL18D PL19A PL19B PL19C PL19D PL26A PL26B PL26C PL26D PL30A PL30B PL30C PL30D PL34A PL34B PL34C PL34D PL38A PL38B PL38C PL38D PL40A VCCIO Bank 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 VREF2_7 ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B LFSC/M115 Dual Function 4-110 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number P38 N35 N36 N39 P39 R34 T34 L41 M41 W29 Y29 L42 M42 U32 V32 R37 T37 M36 M37 P40 N40 R35 T35 N41 P41 V33 U33 R38 T38 R36 T36 N42 P42 Y31 AA31 U37 V37 U34 V34 U39 T39 V35 W35 R41 T41 Ball Function PL26B PL26C PL26D PL29A PL29B PL29C PL29D PL30A PL30B PL30C PL30D PL31A PL31B PL31C PL31D PL33A PL33B PL33C PL33D PL34A PL34B PL34C PL34D PL35A PL35B PL35C PL35D PL37A PL37B PL37C PL37D PL38A PL38B PL38C PL38D PL39A PL39B PL39C PL39D PL41A PL41B PL41C PL41D PL42A PL42B VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 VREF1_7 DIFFR_7 Dual Function Ball Function PL40B PL40C PL40D PL43A PL43B PL43C PL43D PL44A PL44B PL44C PL44D PL45A PL45B PL45C PL45D PL47A PL47B PL47C PL47D PL48A PL48B PL48C PL48D PL49A PL49B PL49C PL49D PL51A PL51B PL51C PL51D PL52A PL52B PL52C PL52D PL53A PL53B PL53C PL53D PL55A PL55B PL55C PL55D PL56A PL56B VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 VREF1_7 DIFFR_7 LFSC/M115 Dual Function 4-111 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number W33 Y33 W37 Y37 Y32 AA32 U38 V38 W34 Y34 T40 U40 AA33 AB33 R42 T42 AA34 AB34 U41 V41 V36 W36 U42 V42 AB31 AC31 W38 Y38 AA35 AB35 W39 Y39 AB32 AC32 W40 Y40 AA36 AB36 W41 Y41 AA37 AB37 W42 Y42 AC33 Ball Function PL42C PL42D PL43A PL43B PL43C PL43D PL46A PL46B PL46C PL46D PL47A PL47B PL47C PL47D PL48A PL48B PL48C PL48D PL50A PL50B PL50C PL50D PL51A PL51B PL51C PL51D PL52A PL52B PL52C PL52D PL55A PL55B PL55C PL55D PL56A PL56B PL56C PL56D PL57A PL57B PL57C PL57D PL59A PL59B PL59C VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 PCLKC6_3 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 Dual Function Ball Function PL56C PL56D PL57A PL57B PL57C PL57D PL60A PL60B PL60C PL60D PL61A PL61B PL61C PL61D PL62A PL62B PL62C PL62D PL64A PL64B PL64C PL64D PL65A PL65B PL65C PL65D PL66A PL66B PL66C PL66D PL69A PL69B PL69C PL69D PL70A PL70B PL70C PL70D PL71A PL71B PL71C PL71D PL73A PL73B PL73C VCCIO Bank 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 VREF1_6 PCLKT6_2 PCLKC6_2 PCLKT6_3 PCLKC6_3 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 LFSC/M115 Dual Function 4-112 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AD33 AA38 AB38 AC29 AD29 AA41 AB41 AC34 AD34 AA42 AB42 AC37 AD37 AC38 AD38 AD36 AE36 AC39 AD39 AD35 AE35 AC40 AD40 AE37 AF37 AC41 AD41 AE34 AF34 AC42 AD42 AE33 AF33 AE38 AF38 AE32 AF32 AE41 AF41 AE31 AF31 AE42 AF42 AG37 AH37 Ball Function PL59D PL60A PL60B PL60C PL60D PL61A PL61B PL61C PL61D PL63A PL63B PL63C PL63D PL64A PL64B PL64C PL64D PL65A PL65B PL65C PL65D PL67A PL67B PL67C PL67D PL68A PL68B PL68C PL68D PL69A PL69B PL69C PL69D PL72A PL72B PL72C PL72D PL73A PL73B PL73C PL73D PL74A PL74B PL74C PL74D VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Dual Function Ball Function PL73D PL74A PL74B PL74C PL74D PL75A PL75B PL75C PL75D PL77A PL77B PL77C PL77D PL78A PL78B PL78C PL78D PL79A PL79B PL79C PL79D PL81A PL81B PL81C PL81D PL82A PL82B PL82C PL82D PL83A PL83B PL83C PL83D PL86A PL86B PL86C PL86D PL87A PL87B PL87C PL87D PL88A PL88B PL88C PL88D VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LFSC/M115 Dual Function 4-113 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AF40 AG40 AG36 AH36 AF39 AG39 AF29 AG29 AH42 AG42 AG35 AH35 AG41 AH41 AG34 AH34 AJ42 AK42 AG33 AH33 AJ41 AK41 AJ37 AK37 AJ40 AK40 AJ34 AK34 AJ38 AK38 AH32 AJ32 AL42 AM42 AK36 AL36 AL38 AM38 AJ33 AK33 AN42 AP42 AH31 AJ31 AN41 Ball Function PL76A PL76B PL76C PL76D PL77A PL77B PL77C PL77D PL78A PL78B PL78C PL78D PL80A PL80B PL80C PL80D PL81A PL81B PL81C PL81D PL82A PL82B PL82C PL82D PL84A PL84B PL84C PL84D PL85A PL85B PL85C PL85D PL86A PL86B PL86C PL86D PL89A PL89B PL89C PL89D PL90A PL90B PL90C PL90D PL91A VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 VREF2_6 DIFFR_6 Dual Function Ball Function PL90A PL90B PL90C PL90D PL91A PL91B PL91C PL91D PL92A PL92B PL92C PL92D PL94A PL94B PL94C PL94D PL96A PL96B PL96C PL96D PL98A PL98B PL98C PL98D PL99A PL99B PL99C PL99D PL103A PL103B PL103C PL103D PL104A PL104B PL104C PL104D PL107A PL107B PL107C PL107D PL109A PL109B PL109C PL109D PL112A VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 VREF2_6 DIFFR_6 LFSC/M115 Dual Function 4-114 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AP41 AK35 AL35 AN38 AP38 AL37 AM37 AR41 AT41 AN37 AP37 AR39 AR40 AN36 AP36 AT40 AU41 AU42 AV42 AL33 AL34 AU38 AV38 AM34 AM33 AV41 AW41 AK30 AK29 AW42 AY42 AR37 AR38 AV40 AV39 AN35 AN34 AW40 AY40 AP34 AP35 AW39 AW38 AL32 AL31 Ball Function PL91B PL91C PL91D PL93A PL93B PL93C PL93D PL94A PL94B PL94C PL94D PL95A PL95B PL95C PL95D XRES TEMP PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D PB7A PB7B PB7C PB7D PB8A PB8B PB8C PB8D PB9A PB9B PB9C PB9D PB11A PB11B PB11C PB11D VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF1_5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F Dual Function Ball Function PL112B PL112C PL112D PL115A PL115B PL115C PL115D PL116A PL116B PL116C PL116D PL117A PL117B PL117C PL117D XRES TEMP PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B PB5C PB5D PB7A PB7B PB7C PB7D PB9A PB9B PB9C PB9D PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF1_5 LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F LFSC/M115 Dual Function 4-115 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AY41 BA41 AT39 AT38 AV37 AV36 AM31 AM32 BA40 BB40 AM29 AL29 AY39 AY38 AN33 AN32 BA39 BA38 AT37 AT36 AW36 AW35 AM28 AL28 BB38 BB39 AR34 AR33 AV35 AV34 AT33 AT34 BA37 BA36 AP33 AP32 AY36 AY35 AN31 AN30 BB37 BB36 AP31 AP30 AV33 Ball Function PB12A PB12B PB12C PB12D PB13A PB13B PB13C PB13D PB15A PB15B PB15C PB15D PB16A PB16B PB16C PB16D PB17A PB17B PB17C PB17D PB19A PB19B PB19C PB19D PB20A PB20B PB20C PB20D PB21A PB21B PB21C PB21D PB23A PB23B PB23C PB23D PB24A PB24B PB24C PB24D PB25A PB25B PB25C PB25D PB27A VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dual Function Ball Function PB13A PB13B PB13C PB13D PB15A PB15B PB15C PB15D PB16A PB16B PB16C PB16D PB17A PB17B PB17C PB17D PB19A PB19B PB19C PB19D PB20A PB20B PB20C PB20D PB21A PB21B PB21C PB21D PB23A PB23B PB23C PB23D PB25A PB25B PB25C PB25D PB26A PB26B PB26C PB26D PB27A PB27B PB27C PB27D PB29A VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 LFSC/M115 Dual Function 4-116 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AV32 AU36 AU37 BA35 BA34 AJ26 AJ27 AW33 AW32 AU35 AU34 BB35 BB34 AN29 AP29 AY33 AY32 AR31 AR30 AV31 AV30 AN28 AP28 BA33 BA32 AT30 AT31 BB33 BB32 AM26 AL26 AW30 AW29 AP27 AN27 BA31 BA30 AU32 AU33 BB31 BB30 AR28 AR27 AV29 AV28 Ball Function PB27B PB27C PB27D PB28A PB28B PB28C PB28D PB29A PB29B PB29C PB29D PB31A PB31B PB31C PB31D PB32A PB32B PB32C PB32D PB33A PB33B PB33C PB33D PB35A PB35B PB35C PB35D PB36A PB36B PB36C PB36D PB37A PB37B PB37C PB37D PB39A PB39B PB39C PB39D PB40A PB40B PB40C PB40D PB41A PB41B VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Dual Function Ball Function PB29B PB29C PB29D PB30A PB30B PB30C PB30D PB31A PB31B PB31C PB31D PB33A PB33B PB33C PB33D PB34A PB34B PB34C PB34D PB35A PB35B PB35C PB35D PB37A PB37B PB37C PB37D PB38A PB38B PB38C PB38D PB39A PB39B PB39C PB39D PB41A PB41B PB41C PB41D PB42A PB42B PB42C PB42D PB43A PB43B VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 LFSC/M115 Dual Function 4-117 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AP26 AN26 AY30 AY29 AU30 AU31 AV27 AV26 AT28 AT27 BA29 BA28 AL25 AM25 BB29 BB28 AN25 AP25 AY27 AY26 AT25 AT24 AW27 AW26 AU29 AU28 BB27 BB26 AR25 AR24 BA27 BA26 AP24 AN24 AV25 AV24 AU27 AU26 BA25 BA24 AU24 AU25 BB24 BB25 AM23 Ball Function PB41C PB41D PB43A PB43B PB43C PB43D PB44A PB44B PB44C PB44D PB45A PB45B PB45C PB45D PB47A PB47B PB47C PB47D PB48A PB48B PB48C PB48D PB49A PB49B PB49C PB49D PB51A PB51B PB51C PB51D PB52A PB52B PB52C PB52D PB53A PB53B PB53C PB53D PB55A PB55B PB55C PB55D PB56A PB56B PB56C VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 PCLKT5_0 PCLKC5_0 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 Dual Function Ball Function PB43C PB43D PB45A PB45B PB45C PB45D PB46A PB46B PB46C PB46D PB47A PB47B PB47C PB47D PB49A PB49B PB49C PB49D PB50A PB50B PB50C PB50D PB51A PB51B PB51C PB51D PB53A PB53B PB53C PB53D PB54A PB54B PB54C PB54D PB55A PB55B PB55C PB55D PB57A PB57B PB57C PB57D PB58A PB58B PB58C VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 PCLKT5_0 PCLKC5_0 PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 LFSC/M115 Dual Function 4-118 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AL23 AW24 AW23 AN23 AP23 AY23 AY24 AU23 AU22 AV23 AV22 AM22 AL22 BA23 BA22 AN22 AP22 BB23 BB22 AT22 AR22 BB21 BB20 AR21 AT21 BA21 BA20 AP21 AN21 AV21 AV20 AM21 AL21 AY20 AY19 AU21 AU20 AW20 AW19 AP20 AN20 BB19 BB18 AM20 AL20 Ball Function PB56D PB57A PB57B PB57C PB57D PB59A PB59B PB59C PB59D PB60A PB60B PB60C PB60D PB61A PB61B PB61C PB61D PB63A PB63B PB63C PB63D PB65A PB65B PB65C PB65D PB66A PB66B PB66C PB66D PB67A PB67B PB67C PB67D PB69A PB69B PB69C PB69D PB70A PB70B PB70C PB70D PB71A PB71B PB71C PB71D VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Dual Function Ball Function PB58D PB61A PB61B PB61C PB61D PB63A PB63B PB63C PB63D PB66A PB66B PB66C PB66D PB69A PB69B PB69C PB69D PB71A PB71B PB71C PB71D PB73A PB73B PB73C PB73D PB75A PB75B PB75C PB75D PB78A PB78B PB78C PB78D PB81A PB81B PB81C PB81D PB83A PB83B PB83C PB83D PB86A PB86B PB86C PB86D VCCIO Bank 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LFSC/M115 Dual Function 4-119 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number BA19 BA18 AU19 AU18 AV19 AV18 AN19 AP19 BB17 BB16 AT19 AT18 BA17 BA16 AR19 AR18 AY17 AY16 AN18 AP18 AW17 AW16 AU17 AU16 AV17 AV16 AL18 AM18 BB15 BB14 AP17 AN17 BA15 BA14 AT16 AT15 AV15 AV14 AR16 AR15 AY14 AY13 AU15 AU14 BB13 Ball Function PB73A PB73B PB73C PB73D PB74A PB74B PB74C PB74D PB75A PB75B PB75C PB75D PB77A PB77B PB77C PB77D PB79A PB79B PB79C PB79D PB80A PB80B PB80C PB80D PB81A PB81B PB81C PB81D PB83A PB83B PB83C PB83D PB84A PB84B PB84C PB84D PB85A PB85B PB85C PB85D PB87A PB87B PB87C PB87D PB88A VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 PCLKT4_5 PCLKC4_5 PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 Dual Function Ball Function PB87A PB87B PB87C PB87D PB89A PB89B PB89C PB89D PB90A PB90B PB90C PB90D PB91A PB91B PB91C PB91D PB93A PB93B PB93C PB93D PB94A PB94B PB94C PB94D PB95A PB95B PB95C PB95D PB97A PB97B PB97C PB97D PB98A PB98B PB98C PB98D PB99A PB99B PB99C PB99D PB101A PB101B PB101C PB101D PB102A VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 PCLKT4_5 PCLKC4_5 PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 LFSC/M115 Dual Function 4-120 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number BB12 AM17 AL17 AW14 AW13 AP16 AN16 BA13 BA12 AU13 AU12 BB11 BB10 AP15 AN15 AV13 AV12 AT13 AT12 BA11 BA10 AR13 AR12 AY11 AY10 AP14 AN14 BB9 BB8 AU11 AU10 AW11 AW10 AJ16 AJ17 BA9 BA8 AM15 AL15 AV11 AV10 AP13 AP12 BB7 BB6 Ball Function PB88B PB88C PB88D PB89A PB89B PB89C PB89D PB91A PB91B PB91C PB91D PB92A PB92B PB92C PB92D PB93A PB93B PB93C PB93D PB95A PB95B PB95C PB95D PB96A PB96B PB96C PB96D PB97A PB97B PB97C PB97D PB99A PB99B PB99C PB99D PB100A PB100B PB100C PB100D PB101A PB101B PB101C PB101D PB103A PB103B VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Dual Function Ball Function PB102B PB102C PB102D PB103A PB103B PB103C PB103D PB105A PB105B PB105C PB105D PB106A PB106B PB106C PB106D PB107A PB107B PB107C PB107D PB109A PB109B PB109C PB109D PB110A PB110B PB110C PB110D PB111A PB111B PB111C PB111D PB113A PB113B PB113C PB113D PB114A PB114B PB114C PB114D PB115A PB115B PB115C PB115D PB117A PB117B VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LFSC/M115 Dual Function 4-121 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AU9 AU8 AY8 AY7 AU7 AU6 BA7 BA6 AN13 AN12 AV9 AV8 AT10 AT9 AW8 AW7 AP11 AP10 BB5 BB4 AR10 AR9 BA5 BA4 AT7 AT6 BB3 BA3 AM14 AL14 AY5 AY4 AN11 AN10 AV7 AV6 AM12 AM11 AW5 AW4 AT5 AT4 AY2 BA2 AP9 Ball Function PB103C PB103D PB104A PB104B PB104C PB104D PB105A PB105B PB105C PB105D PB107A PB107B PB107C PB107D PB108A PB108B PB108C PB108D PB109A PB109B PB109C PB109D PB111A PB111B PB111C PB111D PB112A PB112B PB112C PB112D PB113A PB113B PB113C PB113D PB115A PB115B PB115C PB115D PB116A PB116B PB116C PB116D PB117A PB117B PB117C VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Dual Function Ball Function PB117C PB117D PB118A PB118B PB118C PB118D PB119A PB119B PB119C PB119D PB121A PB121B PB121C PB121D PB122A PB122B PB122C PB122D PB123A PB123B PB123C PB123D PB125A PB125B PB125C PB125D PB126A PB126B PB126C PB126D PB127A PB127B PB127C PB127D PB129A PB129B PB129C PB129D PB130A PB130B PB130C PB130D PB131A PB131B PB131C VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LFSC/M115 Dual Function 4-122 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AP8 AY3 AW3 AR6 AR5 AU5 AV5 AL12 AL11 AV3 AV4 AN9 AN8 AW1 AY1 AK14 AK13 AV2 AW2 AM10 AM9 AV1 AU1 AL10 AL9 AT3 AU2 AP7 AN7 AR3 AR4 AP6 AN6 AT2 AR2 AM6 AL6 AP5 AN5 AL8 AK8 AP2 AN2 AJ12 AH12 Ball Function PB117D PB119A PB119B PB119C PB119D PB120A PB120B PB120C PB120D PB121A PB121B PB121C PB121D PB123A PB123B PB123C PB123D PB124A PB124B PB124C PB124D PB125A PB125B PB125C PB125D PROBE_VCC PROBE_GND PR95D PR95C PR95B PR95A PR94D PR94C PR94B PR94A PR93D PR93C PR93B PR93A PR91D PR91C PR91B PR91A PR90D PR90C VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D VREF1_4 Dual Function Ball Function PB131D PB133A PB133B PB133C PB133D PB134A PB134B PB134C PB134D PB135A PB135B PB135C PB135D PB138A PB138B PB138C PB138D PB139A PB139B PB139C PB139D PB141A PB141B PB141C PB141D PROBE_VCC PROBE_GND PR117D PR117C PR117B PR117A PR116D PR116C PR116B PR116A PR115D PR115C PR115B PR115A PR112D PR112C PR112B PR112A PR109D PR109C VCCIO Bank 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D VREF1_4 LFSC/M115 Dual Function 4-123 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AP1 AN1 AK10 AJ10 AM5 AL5 AL7 AK7 AM1 AL1 AJ11 AH11 AK5 AJ5 AK9 AJ9 AK3 AJ3 AK6 AJ6 AK2 AJ2 AH10 AG10 AK1 AJ1 AH9 AG9 AH2 AG2 AH8 AG8 AG1 AH1 AG14 AF14 AG4 AF4 AH7 AG7 AG3 AF3 AH6 AG6 AF1 Ball Function PR90B PR90A PR89D PR89C PR89B PR89A PR86D PR86C PR86B PR86A PR85D PR85C PR85B PR85A PR84D PR84C PR84B PR84A PR82D PR82C PR82B PR82A PR81D PR81C PR81B PR81A PR80D PR80C PR80B PR80A PR78D PR78C PR78B PR78A PR77D PR77C PR77B PR77A PR76D PR76C PR76B PR76A PR74D PR74C PR74B VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 DIFFR_3 VREF2_3 Dual Function Ball Function PR109B PR109A PR107D PR107C PR107B PR107A PR104D PR104C PR104B PR104A PR103D PR103C PR103B PR103A PR99D PR99C PR99B PR99A PR98D PR98C PR98B PR98A PR96D PR96C PR96B PR96A PR94D PR94C PR94B PR94A PR92D PR92C PR92B PR92A PR91D PR91C PR91B PR91A PR90D PR90C PR90B PR90A PR88D PR88C PR88B VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 DIFFR_3 VREF2_3 LFSC/M115 Dual Function 4-124 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AE1 AF12 AE12 AF2 AE2 AF11 AE11 AF5 AE5 AF10 AE10 AD1 AC1 AF9 AE9 AD2 AC2 AF6 AE6 AD3 AC3 AE8 AD8 AD4 AC4 AE7 AD7 AD5 AC5 AD6 AC6 AB1 AA1 AD9 AC9 AB2 AA2 AD14 AC14 AB5 AA5 AD10 AC10 Y1 W1 Ball Function PR74A PR73D PR73C PR73B PR73A PR72D PR72C PR72B PR72A PR69D PR69C PR69B PR69A PR68D PR68C PR68B PR68A PR67D PR67C PR67B PR67A PR65D PR65C PR65B PR65A PR64D PR64C PR64B PR64A PR63D PR63C PR63B PR63A PR61D PR61C PR61B PR61A PR60D PR60C PR60B PR60A PR59D PR59C PR59B PR59A VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Dual Function Ball Function PR88A PR87D PR87C PR87B PR87A PR86D PR86C PR86B PR86A PR83D PR83C PR83B PR83A PR82D PR82C PR82B PR82A PR81D PR81C PR81B PR81A PR79D PR79C PR79B PR79A PR78D PR78C PR78B PR78A PR77D PR77C PR77B PR77A PR75D PR75C PR75B PR75A PR74D PR74C PR74B PR74A PR73D PR73C PR73B PR73A VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 LFSC/M115 Dual Function 4-125 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AB6 AA6 Y2 W2 AB7 AA7 Y3 W3 AC11 AB11 Y4 W4 AB8 AA8 Y5 W5 AC12 AB12 V1 U1 W7 V7 V2 U2 AB9 AA9 T1 R1 AB10 AA10 U3 T3 Y9 W9 V5 U5 AA11 Y11 Y6 W6 Y10 W10 T2 R2 W8 Ball Function PR57D PR57C PR57B PR57A PR56D PR56C PR56B PR56A PR55D PR55C PR55B PR55A PR52D PR52C PR52B PR52A PR51D PR51C PR51B PR51A PR50D PR50C PR50B PR50A PR48D PR48C PR48B PR48A PR47D PR47C PR47B PR47A PR46D PR46C PR46B PR46A PR43D PR43C PR43B PR43A PR42D PR42C PR42B PR42A PR41D VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 PCLKC3_3 PCLKT3_3 PCLKC3_2 PCLKT3_2 VREF1_3 Dual Function Ball Function PR71D PR71C PR71B PR71A PR70D PR70C PR70B PR70A PR69D PR69C PR69B PR69A PR66D PR66C PR66B PR66A PR65D PR65C PR65B PR65A PR64D PR64C PR64B PR64A PR62D PR62C PR62B PR62A PR61D PR61C PR61B PR61A PR60D PR60C PR60B PR60A PR57D PR57C PR57B PR57A PR56D PR56C PR56B PR56A PR55D VCCIO Bank 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 PCLKC3_3 PCLKT3_3 PCLKC3_2 PCLKT3_2 VREF1_3 LFSC/M115 Dual Function 4-126 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number V8 T4 U4 V9 U9 V6 U6 AA12 Y12 P1 N1 T7 R7 T5 R5 U10 V10 P2 N2 T8 R8 N3 P3 M6 M7 T6 R6 V11 U11 M1 L1 Y14 W14 M2 L2 T9 R9 P4 N4 N7 N8 P5 N5 K7 J7 Ball Function PR41C PR41B PR41A PR39D PR39C PR39B PR39A PR38D PR38C PR38B PR38A PR37D PR37C PR37B PR37A PR35D PR35C PR35B PR35A PR34D PR34C PR34B PR34A PR33D PR33C PR33B PR33A PR31D PR31C PR31B PR31A PR30D PR30C PR30B PR30A PR29D PR29C PR29B PR29A PR26D PR26C PR26B PR26A PR25D PR25C VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIFFR_2 VREF1_2 Dual Function Ball Function PR55C PR55B PR55A PR53D PR53C PR53B PR53A PR52D PR52C PR52B PR52A PR51D PR51C PR51B PR51A PR49D PR49C PR49B PR49A PR48D PR48C PR48B PR48A PR47D PR47C PR47B PR47A PR45D PR45C PR45B PR45A PR44D PR44C PR44B PR44A PR43D PR43C PR43B PR43A PR40D PR40C PR40B PR40A PR38D PR38C VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIFFR_2 VREF1_2 LFSC/M115 Dual Function 4-127 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number J1 K1 V12 U12 K2 J2 R10 T10 L5 K5 P9 N9 L6 K6 M8 M9 H1 G1 U14 T14 H2 G2 P10 N10 H3 G3 R11 P11 J5 J6 P18 P19 R21 P20 P12 P17 P21 P13 H10 N13 H9 G9 F2 H4 C1 Ball Function PR25B PR25A PR24D PR24C PR24B PR24A PR22D PR22C PR22B PR22A PR21D PR21C PR21B PR21A PR20D PR20C PR20B PR20A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R VCC12 A_VDDIB0_R A_HDINP0_R VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 PCS 3E0 CH 0 IN P CFGIRQN/MPI_IRQ_N TDO URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 Dual Function Ball Function PR38B PR38A PR34D PR34C PR34B PR34A PR30D PR30C PR30B PR30A PR26D PR26C PR26B PR26A PR19D PR19C PR19B PR19A PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR15D PR15C PR15B PR15A VCCJ TDO TMS TCK TDI PROGRAMN MPIIRQN CCLK RESP_URC VCC12 A_REFCLKN_R A_REFCLKP_R VCC12 A_VDDIB0_R A_HDINP0_R VCCIO Bank 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 PCS 3E0 CH 0 IN P CFGIRQN/MPI_IRQ_N TDO URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D VREF2_2 LFSC/M115 Dual Function 4-128 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number D1 F1 A3 E1 B3 C2 A4 B2 B4 E3 D3 M10 E2 J11 M11 D4 E4 K9 A5 D2 B5 L10 B6 G6 A6 E5 D5 K12 L13 N14 F9 D6 E6 J8 B7 G4 A7 K8 A8 L9 B8 E7 D7 F10 K13 Ball Function A_HDINN0_R VCC12 A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R VCC12 A_HDOUTP1_R A_HDINN1_R A_HDINP1_R VCC12 A_VDDIB1_R VCC12 A_VDDIB2_R A_HDINP2_R A_HDINN2_R VCC12 A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R VCC12 A_HDOUTP3_R A_HDINN3_R A_HDINP3_R VCC12 A_VDDIB3_R VCC12 B_VDDIB0_R B_HDINP0_R B_HDINN0_R VCC12 B_HDOUTP0_R B_VDDOB0_R B_HDOUTN0_R B_VDDOB1_R B_HDOUTN1_R VCC12 B_HDOUTP1_R B_HDINN1_R B_HDINP1_R VCC12 B_VDDIB1_R VCCIO Bank PCS 3E1 CH 1 OUT P PCS 3E1 CH 1 IN N PCS 3E1 CH 1 IN P PCS 3E1 CH 1 OUT N PCS 3E1 CH 0 OUT N PCS 3E1 CH 0 OUT P PCS 3E1 CH 0 IN P PCS 3E1 CH 0 IN N PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 3 OUT N PCS 3E0 CH 2 OUT N PCS 3E0 CH 2 OUT P PCS 3E0 CH 2 IN P PCS 3E0 CH 2 IN N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 OUT P Dual Function PCS 3E0 CH 0 IN N Ball Function A_HDINN0_R VCC12 A_HDOUTP0_R A_VDDOB0_R A_HDOUTN0_R A_VDDOB1_R A_HDOUTN1_R VCC12 A_HDOUTP1_R A_HDINN1_R A_HDINP1_R VCC12 A_VDDIB1_R VCC12 A_VDDIB2_R A_HDINP2_R A_HDINN2_R VCC12 A_HDOUTP2_R A_VDDOB2_R A_HDOUTN2_R A_VDDOB3_R A_HDOUTN3_R VCC12 A_HDOUTP3_R A_HDINN3_R A_HDINP3_R VCC12 A_VDDIB3_R VCC12 B_VDDIB0_R B_HDINP0_R B_HDINN0_R VCC12 B_HDOUTP0_R B_VDDOB0_R B_HDOUTN0_R B_VDDOB1_R B_HDOUTN1_R VCC12 B_HDOUTP1_R B_HDINN1_R B_HDINP1_R VCC12 B_VDDIB1_R VCCIO Bank PCS 3E1 CH 1 OUT P PCS 3E1 CH 1 IN N PCS 3E1 CH 1 IN P PCS 3E1 CH 1 OUT N PCS 3E1 CH 0 OUT N PCS 3E1 CH 0 OUT P PCS 3E1 CH 0 IN P PCS 3E1 CH 0 IN N PCS 3E0 CH 3 OUT P PCS 3E0 CH 3 IN N PCS 3E0 CH 3 IN P PCS 3E0 CH 3 OUT N PCS 3E0 CH 2 OUT N PCS 3E0 CH 2 OUT P PCS 3E0 CH 2 IN P PCS 3E0 CH 2 IN N PCS 3E0 CH 1 OUT P PCS 3E0 CH 1 IN N PCS 3E0 CH 1 IN P PCS 3E0 CH 1 OUT N PCS 3E0 CH 0 OUT N PCS 3E0 CH 0 OUT P LFSC/M115 Dual Function PCS 3E0 CH 0 IN N 4-129 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number K14 H11 D8 E8 G5 B9 L12 A9 C5 A10 H5 B10 E9 D9 J13 H12 J12 M14 L14 J14 G12 D10 E10 H6 B11 M12 A11 L11 A12 K11 B12 E11 D11 H13 C6 H15 G13 D12 E12 J9 B13 K10 A13 J10 A14 Ball Function VCC12 B_VDDIB2_R B_HDINP2_R B_HDINN2_R VCC12 B_HDOUTP2_R B_VDDOB2_R B_HDOUTN2_R B_VDDOB3_R B_HDOUTN3_R VCC12 B_HDOUTP3_R B_HDINN3_R B_HDINP3_R VCC12 B_VDDIB3_R VCC12 B_REFCLKN_R B_REFCLKP_R VCC12 C_VDDIB0_R C_HDINP0_R C_HDINN0_R VCC12 C_HDOUTP0_R C_VDDOB0_R C_HDOUTN0_R C_VDDOB1_R C_HDOUTN1_R VCC12 C_HDOUTP1_R C_HDINN1_R C_HDINP1_R VCC12 C_VDDIB1_R VCC12 C_VDDIB2_R C_HDINP2_R C_HDINN2_R VCC12 C_HDOUTP2_R C_VDDOB2_R C_HDOUTN2_R C_VDDOB3_R C_HDOUTN3_R VCCIO Bank PCS 3E2 CH 3 OUT N PCS 3E2 CH 2 OUT N PCS 3E2 CH 2 OUT P PCS 3E2 CH 2 IN P PCS 3E2 CH 2 IN N PCS 3E2 CH 1 OUT P PCS 3E2 CH 1 IN N PCS 3E2 CH 1 IN P PCS 3E2 CH 1 OUT N PCS 3E2 CH 0 OUT N PCS 3E2 CH 0 OUT P PCS 3E2 CH 0 IN P PCS 3E2 CH 0 IN N PCS 3E1 CH 3 OUT P PCS 3E1 CH 3 IN N PCS 3E1 CH 3 IN P PCS 3E1 CH 3 OUT N PCS 3E1 CH 2 OUT N PCS 3E1 CH 2 OUT P PCS 3E1 CH 2 IN P PCS 3E1 CH 2 IN N Dual Function Ball Function VCC12 B_VDDIB2_R B_HDINP2_R B_HDINN2_R VCC12 B_HDOUTP2_R B_VDDOB2_R B_HDOUTN2_R B_VDDOB3_R B_HDOUTN3_R VCC12 B_HDOUTP3_R B_HDINN3_R B_HDINP3_R VCC12 B_VDDIB3_R VCC12 B_REFCLKN_R B_REFCLKP_R VCC12 C_VDDIB0_R C_HDINP0_R C_HDINN0_R VCC12 C_HDOUTP0_R C_VDDOB0_R C_HDOUTN0_R C_VDDOB1_R C_HDOUTN1_R VCC12 C_HDOUTP1_R C_HDINN1_R C_HDINP1_R VCC12 C_VDDIB1_R VCC12 C_VDDIB2_R C_HDINP2_R C_HDINN2_R VCC12 C_HDOUTP2_R C_VDDOB2_R C_HDOUTN2_R C_VDDOB3_R C_HDOUTN3_R VCCIO Bank PCS 3E2 CH 3 OUT N PCS 3E2 CH 2 OUT N PCS 3E2 CH 2 OUT P PCS 3E2 CH 2 IN P PCS 3E2 CH 2 IN N PCS 3E2 CH 1 OUT P PCS 3E2 CH 1 IN N PCS 3E2 CH 1 IN P PCS 3E2 CH 1 OUT N PCS 3E2 CH 0 OUT N PCS 3E2 CH 0 OUT P PCS 3E2 CH 0 IN P PCS 3E2 CH 0 IN N PCS 3E1 CH 3 OUT P PCS 3E1 CH 3 IN N PCS 3E1 CH 3 IN P PCS 3E1 CH 3 OUT N PCS 3E1 CH 2 OUT N PCS 3E1 CH 2 OUT P PCS 3E1 CH 2 IN P PCS 3E1 CH 2 IN N LFSC/M115 Dual Function 4-130 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number F5 B14 E13 D13 F12 G14 F11 K15 J15 G15 H16 D14 E14 F6 B15 M13 A15 F8 A16 F7 B16 F15 E15 K17 F13 C14 C15 D16 E16 C11 B17 C9 A17 D17 A18 C17 B18 F17 E17 F14 F16 G16 M17 L17 G18 Ball Function VCC12 C_HDOUTP3_R C_HDINN3_R C_HDINP3_R VCC12 C_VDDIB3_R VCC12 C_REFCLKN_R C_REFCLKP_R VCC12 D_VDDIB0_R D_HDINP0_R D_HDINN0_R VCC12 D_HDOUTP0_R D_VDDOB0_R D_HDOUTN0_R D_VDDOB1_R D_HDOUTN1_R VCC12 D_HDOUTP1_R D_HDINN1_R D_HDINP1_R VCC12 D_VDDIB1_R VCC12 D_VDDIB2_R D_HDINP2_R D_HDINN2_R VCC12 D_HDOUTP2_R D_VDDOB2_R D_HDOUTN2_R D_VDDOB3_R D_HDOUTN3_R VCC12 D_HDOUTP3_R D_HDINN3_R D_HDINP3_R VCC12 D_VDDIB3_R VCC12 D_REFCLKN_R D_REFCLKP_R PT77D VCCIO Bank 1 HDC/SI PCS 3E3 CH 3 OUT P PCS 3E3 CH 3 IN N PCS 3E3 CH 3 IN P PCS 3E3 CH 3 OUT N PCS 3E3 CH 2 OUT N PCS 3E3 CH 2 OUT P PCS 3E3 CH 2 IN P PCS 3E3 CH 2 IN N PCS 3E3 CH 1 OUT P PCS 3E3 CH 1 IN N PCS 3E3 CH 1 IN P PCS 3E3 CH 1 OUT N PCS 3E3 CH 0 OUT N PCS 3E3 CH 0 OUT P PCS 3E3 CH 0 IN P PCS 3E3 CH 0 IN N PCS 3E2 CH 3 OUT P PCS 3E2 CH 3 IN N PCS 3E2 CH 3 IN P Dual Function Ball Function VCC12 C_HDOUTP3_R C_HDINN3_R C_HDINP3_R VCC12 C_VDDIB3_R VCC12 C_REFCLKN_R C_REFCLKP_R VCC12 D_VDDIB0_R D_HDINP0_R D_HDINN0_R VCC12 D_HDOUTP0_R D_VDDOB0_R D_HDOUTN0_R D_VDDOB1_R D_HDOUTN1_R VCC12 D_HDOUTP1_R D_HDINN1_R D_HDINP1_R VCC12 D_VDDIB1_R VCC12 D_VDDIB2_R D_HDINP2_R D_HDINN2_R VCC12 D_HDOUTP2_R D_VDDOB2_R D_HDOUTN2_R D_VDDOB3_R D_HDOUTN3_R VCC12 D_HDOUTP3_R D_HDINN3_R D_HDINP3_R VCC12 D_VDDIB3_R VCC12 D_REFCLKN_R D_REFCLKP_R PT93D VCCIO Bank 1 HDC/SI PCS 3E3 CH 3 OUT P PCS 3E3 CH 3 IN N PCS 3E3 CH 3 IN P PCS 3E3 CH 3 OUT N PCS 3E3 CH 2 OUT N PCS 3E3 CH 2 OUT P PCS 3E3 CH 2 IN P PCS 3E3 CH 2 IN N PCS 3E3 CH 1 OUT P PCS 3E3 CH 1 IN N PCS 3E3 CH 1 IN P PCS 3E3 CH 1 OUT N PCS 3E3 CH 0 OUT N PCS 3E3 CH 0 OUT P PCS 3E3 CH 0 IN P PCS 3E3 CH 0 IN N PCS 3E2 CH 3 OUT P PCS 3E2 CH 3 IN N PCS 3E2 CH 3 IN P LFSC/M115 Dual Function 4-131 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number H18 F18 E18 H19 G19 D19 D18 J20 K20 E19 F19 K18 J18 A19 B19 H17 J17 B20 C20 M20 L20 F20 G20 K19 J19 D20 E20 H21 G21 B21 C21 M21 L21 A21 A20 J21 K21 E21 F21 G22 H22 A23 A22 L22 M22 Ball Function PT77C PT77B PT77A PT75D PT75C PT75B PT75A PT74D PT74C PT74B PT74A PT73D PT73C PT73B PT73A PT71D PT71C PT71B PT71A PT70D PT70C PT70B PT70A PT69D PT69C PT69B PT69A PT67D PT67C PT67B PT67A PT66D PT66C PT66B PT66A PT65D PT65C PT65B PT65A PT63D PT63C PT63B PT63A PT61D PT61C VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Dual Function LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D16/PCLKC1_3/MPI_DATA16 D17/PCLKT1_3/MPI_DATA17 D0/MPI_DATA0 QOUT/CEON VREF2_1 D18/MPI_DATA18 DOUT MCA_DONE_IN D19/PCLKC1_2/MPI_DATA19 D20/PCLKT1_2/MPI_DATA20 MCA_CLK_P1_OUT MCA_CLK_P1_IN D21/PCLKC1_1/MPI_DATA21 D22/PCLKT1_1/MPI_DATA22 MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA D23/MPI_DATA23 DP2/MPI_PAR2 PCLKC1_0 PCLKT1_0/MPI_CLK DP3/PCLKC1_4/MPI_PAR3 D24/PCLKT1_4/MPI_DATA24 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 Ball Function PT93C PT93B PT93A PT90D PT90C PT90B PT90A PT89D PT89C PT89B PT89A PT87D PT87C PT87B PT87A PT86D PT86C PT86B PT86A PT83D PT83C PT83B PT83A PT81D PT81C PT81B PT81A PT78D PT78C PT78B PT78A PT75D PT75C PT75B PT75A PT73D PT73C PT73B PT73A PT71D PT71C PT71B PT71A PT69D PT69C VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LFSC/M115 Dual Function LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 D3/MPI_DATA3 D2/MPI_DATA2 D1/MPI_DATA1 D16/PCLKC1_3/MPI_DATA16 D17/PCLKT1_3/MPI_DATA17 D0/MPI_DATA0 QOUT/CEON VREF2_1 D18/MPI_DATA18 DOUT MCA_DONE_IN D19/PCLKC1_2/MPI_DATA19 D20/PCLKT1_2/MPI_DATA20 MCA_CLK_P1_OUT MCA_CLK_P1_IN D21/PCLKC1_1/MPI_DATA21 D22/PCLKT1_1/MPI_DATA22 MCA_CLK_P2_OUT MCA_CLK_P2_IN MCA_DONE_OUT BUSYN/RCLK/SCK DP0/MPI_PAR0 MPI_TA D23/MPI_DATA23 DP2/MPI_PAR2 PCLKC1_0 PCLKT1_0/MPI_CLK DP3/PCLKC1_4/MPI_PAR3 D24/PCLKT1_4/MPI_DATA24 MPI_RETRY A0/MPI_ADDR14 A1/MPI_ADDR15 A2/MPI_ADDR16 4-132 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number B22 B23 K23 J23 D22 E22 K22 J22 D23 C23 L23 M23 A24 B24 K25 J25 F23 F22 J26 K26 E23 E24 G23 G24 F26 F27 H25 H24 C25 C26 K24 J24 F24 F25 L26 M26 G27 C29 F28 D26 E26 B25 D24 A25 E25 Ball Function PT61B PT61A PT60D PT60C PT60B PT60A PT59D PT59C PT59B PT59A PT57D PT57C PT57B PT57A PT56D PT56C PT56B PT56A PT55D PT55C PT55B PT55A PT53D PT53C PT53B PT53A PT52D PT52C PT52B PT52A PT51D PT51C PT51B PT51A D_REFCLKP_L D_REFCLKN_L VCC12 D_VDDIB3_L VCC12 D_HDINP3_L D_HDINN3_L D_HDOUTP3_L VCC12 D_HDOUTN3_L D_VDDOB3_L VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCS 363 CH 3 OUT N PCS 363 CH 3 IN P PCS 363 CH 3 IN N PCS 363 CH 3 OUT P Dual Function A3/MPI_ADDR17 A4/MPI_ADDR18 D25/PCLKC1_5/MPI_DATA25 D26/PCLKT1_5/MPI_DATA26 A5/MPI_ADDR19 A6/MPI_ADDR20 D27/MPI_DATA27 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 D28/PCLKC1_6/MPI_DATA28 D29/PCLKT1_6/MPI_DATA29 A9/MPI_ADDR23 A10/MPI_ADDR24 D30/PCLKC1_7/MPI_DATA30 D31/PCLKT1_7/MPI_DATA31 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 Ball Function PT69B PT69A PT66D PT66C PT66B PT66A PT63D PT63C PT63B PT63A PT61D PT61C PT61B PT61A PT58D PT58C PT58B PT58A PT57D PT57C PT57B PT57A PT55D PT55C PT55B PT55A PT54D PT54C PT54B PT54A PT51D PT51C PT51B PT51A D_REFCLKP_L D_REFCLKN_L VCC12 D_VDDIB3_L VCC12 D_HDINP3_L D_HDINN3_L D_HDOUTP3_L VCC12 D_HDOUTN3_L D_VDDOB3_L VCCIO Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCS 363 CH 3 OUT N PCS 363 CH 3 IN P PCS 363 CH 3 IN N PCS 363 CH 3 OUT P LFSC/M115 Dual Function A3/MPI_ADDR17 A4/MPI_ADDR18 D25/PCLKC1_5/MPI_DATA25 D26/PCLKT1_5/MPI_DATA26 A5/MPI_ADDR19 A6/MPI_ADDR20 D27/MPI_DATA27 VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 D28/PCLKC1_6/MPI_DATA28 D29/PCLKT1_6/MPI_DATA29 A9/MPI_ADDR23 A10/MPI_ADDR24 D30/PCLKC1_7/MPI_DATA30 D31/PCLKT1_7/MPI_DATA31 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 MPI_TEA D14/MPI_DATA14 DP1/MPI_PAR1 A21/MPI_BURST D15/MPI_DATA15 4-133 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number A26 C34 B26 C32 E27 D27 G25 F29 H26 F30 D28 E28 B27 F36 A27 F35 A28 M30 B28 F37 E29 D29 H27 G28 J28 K28 F32 G29 C31 D30 E30 B29 F38 A29 J33 A30 K33 B30 J34 F31 E31 G30 H28 C37 H30 Ball Function D_HDOUTN2_L D_VDDOB2_L D_HDOUTP2_L VCC12 D_HDINN2_L D_HDINP2_L D_VDDIB2_L VCC12 D_VDDIB1_L VCC12 D_HDINP1_L D_HDINN1_L D_HDOUTP1_L VCC12 D_HDOUTN1_L D_VDDOB1_L D_HDOUTN0_L D_VDDOB0_L D_HDOUTP0_L VCC12 D_HDINN0_L D_HDINP0_L D_VDDIB0_L VCC12 C_REFCLKP_L C_REFCLKN_L VCC12 C_VDDIB3_L VCC12 C_HDINP3_L C_HDINN3_L C_HDOUTP3_L VCC12 C_HDOUTN3_L C_VDDOB3_L C_HDOUTN2_L C_VDDOB2_L C_HDOUTP2_L VCC12 C_HDINN2_L C_HDINP2_L C_VDDIB2_L VCC12 C_VDDIB1_L VCC12 VCCIO Bank PCS 362 CH 2 IN N PCS 362 CH 2 IN P PCS 362 CH 2 OUT P PCS 362 CH 2 OUT N PCS 362 CH 3 OUT N PCS 362 CH 3 IN P PCS 362 CH 3 IN N PCS 362 CH 3 OUT P PCS 363 CH 0 IN N PCS 363 CH 0 IN P PCS 363 CH 0 OUT P PCS 363 CH 0 OUT N PCS 363 CH 1 OUT N PCS 363 CH 1 IN P PCS 363 CH 1 IN N PCS 363 CH 1 OUT P PCS 363 CH 2 IN N PCS 363 CH 2 IN P PCS 363 CH 2 OUT P Dual Function PCS 363 CH 2 OUT N Ball Function D_HDOUTN2_L D_VDDOB2_L D_HDOUTP2_L VCC12 D_HDINN2_L D_HDINP2_L D_VDDIB2_L VCC12 D_VDDIB1_L VCC12 D_HDINP1_L D_HDINN1_L D_HDOUTP1_L VCC12 D_HDOUTN1_L D_VDDOB1_L D_HDOUTN0_L D_VDDOB0_L D_HDOUTP0_L VCC12 D_HDINN0_L D_HDINP0_L D_VDDIB0_L VCC12 C_REFCLKP_L C_REFCLKN_L VCC12 C_VDDIB3_L VCC12 C_HDINP3_L C_HDINN3_L C_HDOUTP3_L VCC12 C_HDOUTN3_L C_VDDOB3_L C_HDOUTN2_L C_VDDOB2_L C_HDOUTP2_L VCC12 C_HDINN2_L C_HDINP2_L C_VDDIB2_L VCC12 C_VDDIB1_L VCC12 VCCIO Bank PCS 362 CH 2 IN N PCS 362 CH 2 IN P PCS 362 CH 2 OUT P PCS 362 CH 2 OUT N PCS 362 CH 3 OUT N PCS 362 CH 3 IN P PCS 362 CH 3 IN N PCS 362 CH 3 OUT P PCS 363 CH 0 IN N PCS 363 CH 0 IN P PCS 363 CH 0 OUT P PCS 363 CH 0 OUT N PCS 363 CH 1 OUT N PCS 363 CH 1 IN P PCS 363 CH 1 IN N PCS 363 CH 1 OUT P PCS 363 CH 2 IN N PCS 363 CH 2 IN P PCS 363 CH 2 OUT P LFSC/M115 Dual Function PCS 363 CH 2 OUT N 4-134 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number D32 E32 B31 K32 A31 L32 A32 M31 B32 H37 E33 D33 G31 J29 L29 M29 J31 H31 J30 D34 E34 B33 H38 A33 C38 A34 L31 B34 G38 E35 D35 H32 K29 K30 F33 D36 E36 B35 L34 A35 K35 A36 G39 B36 J35 Ball Function C_HDINP1_L C_HDINN1_L C_HDOUTP1_L VCC12 C_HDOUTN1_L C_VDDOB1_L C_HDOUTN0_L C_VDDOB0_L C_HDOUTP0_L VCC12 C_HDINN0_L C_HDINP0_L C_VDDIB0_L VCC12 B_REFCLKP_L B_REFCLKN_L VCC12 B_VDDIB3_L VCC12 B_HDINP3_L B_HDINN3_L B_HDOUTP3_L VCC12 B_HDOUTN3_L B_VDDOB3_L B_HDOUTN2_L B_VDDOB2_L B_HDOUTP2_L VCC12 B_HDINN2_L B_HDINP2_L B_VDDIB2_L VCC12 B_VDDIB1_L VCC12 B_HDINP1_L B_HDINN1_L B_HDOUTP1_L VCC12 B_HDOUTN1_L B_VDDOB1_L B_HDOUTN0_L B_VDDOB0_L B_HDOUTP0_L VCC12 VCCIO Bank PCS 361 CH 0 OUT P PCS 361 CH 0 OUT N PCS 361 CH 1 OUT N PCS 361 CH 1 IN P PCS 361 CH 1 IN N PCS 361 CH 1 OUT P PCS 361 CH 2 IN N PCS 361 CH 2 IN P PCS 361 CH 2 OUT P PCS 361 CH 2 OUT N PCS 361 CH 3 OUT N PCS 361 CH 3 IN P PCS 361 CH 3 IN N PCS 361 CH 3 OUT P PCS 362 CH 0 IN N PCS 362 CH 0 IN P PCS 362 CH 0 OUT P PCS 362 CH 0 OUT N PCS 362 CH 1 OUT N Dual Function PCS 362 CH 1 IN P PCS 362 CH 1 IN N PCS 362 CH 1 OUT P Ball Function C_HDINP1_L C_HDINN1_L C_HDOUTP1_L VCC12 C_HDOUTN1_L C_VDDOB1_L C_HDOUTN0_L C_VDDOB0_L C_HDOUTP0_L VCC12 C_HDINN0_L C_HDINP0_L C_VDDIB0_L VCC12 B_REFCLKP_L B_REFCLKN_L VCC12 B_VDDIB3_L VCC12 B_HDINP3_L B_HDINN3_L B_HDOUTP3_L VCC12 B_HDOUTN3_L B_VDDOB3_L B_HDOUTN2_L B_VDDOB2_L B_HDOUTP2_L VCC12 B_HDINN2_L B_HDINP2_L B_VDDIB2_L VCC12 B_VDDIB1_L VCC12 B_HDINP1_L B_HDINN1_L B_HDOUTP1_L VCC12 B_HDOUTN1_L B_VDDOB1_L B_HDOUTN0_L B_VDDOB0_L B_HDOUTP0_L VCC12 VCCIO Bank PCS 361 CH 0 OUT P PCS 361 CH 0 OUT N PCS 361 CH 1 OUT N PCS 361 CH 1 IN P PCS 361 CH 1 IN N PCS 361 CH 1 OUT P PCS 361 CH 2 IN N PCS 361 CH 2 IN P PCS 361 CH 2 OUT P PCS 361 CH 2 OUT N PCS 361 CH 3 OUT N PCS 361 CH 3 IN P PCS 361 CH 3 IN N PCS 361 CH 3 OUT P PCS 362 CH 0 IN N PCS 362 CH 0 IN P PCS 362 CH 0 OUT P PCS 362 CH 0 OUT N PCS 362 CH 1 OUT N LFSC/M115 Dual Function PCS 362 CH 1 IN P PCS 362 CH 1 IN N PCS 362 CH 1 OUT P 4-135 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number E37 D37 F34 N29 L30 K31 D38 E38 A37 G37 B37 L33 B38 D41 A38 K34 E39 D39 M32 J32 E41 M33 D40 E40 B39 B41 A39 C41 B40 E42 A40 F42 D42 C42 H39 F41 P16 P27 K39 L39 M38 K40 L40 N37 P37 Ball Function B_HDINN0_L B_HDINP0_L B_VDDIB0_L VCC12 A_VDDIB3_L VCC12 A_HDINP3_L A_HDINN3_L A_HDOUTP3_L VCC12 A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L VCC12 A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCC12 A_VDDIB1_L VCC12 A_HDINP1_L A_HDINN1_L A_HDOUTP1_L VCC12 A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L VCC12 A_HDINN0_L A_HDINP0_L A_VDDIB0_L VCC12 VDDAX25_R VDDAX25_L NC NC NC NC NC NC NC VCCIO Bank PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT P PCS 360 CH 0 OUT N PCS 360 CH 1 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT P PCS 360 CH 2 OUT N PCS 360 CH 3 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P Dual Function PCS 361 CH 0 IN N PCS 361 CH 0 IN P Ball Function B_HDINN0_L B_HDINP0_L B_VDDIB0_L VCC12 A_VDDIB3_L VCC12 A_HDINP3_L A_HDINN3_L A_HDOUTP3_L VCC12 A_HDOUTN3_L A_VDDOB3_L A_HDOUTN2_L A_VDDOB2_L A_HDOUTP2_L VCC12 A_HDINN2_L A_HDINP2_L A_VDDIB2_L VCC12 A_VDDIB1_L VCC12 A_HDINP1_L A_HDINN1_L A_HDOUTP1_L VCC12 A_HDOUTN1_L A_VDDOB1_L A_HDOUTN0_L A_VDDOB0_L A_HDOUTP0_L VCC12 A_HDINN0_L A_HDINP0_L A_VDDIB0_L VCC12 VDDAX25_R VDDAX25_L PL32A PL32B PL35A PL36A PL36B PL39A PL39B VCCIO Bank 7 7 7 7 7 7 7 PCS 360 CH 0 IN N PCS 360 CH 0 IN P PCS 360 CH 0 OUT P PCS 360 CH 0 OUT N PCS 360 CH 1 OUT N PCS 360 CH 1 IN P PCS 360 CH 1 IN N PCS 360 CH 1 OUT P PCS 360 CH 2 IN N PCS 360 CH 2 IN P PCS 360 CH 2 OUT P PCS 360 CH 2 OUT N PCS 360 CH 3 OUT N PCS 360 CH 3 IN P PCS 360 CH 3 IN N PCS 360 CH 3 OUT P LFSC/M115 Dual Function PCS 361 CH 0 IN N PCS 361 CH 0 IN P 4-136 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AG38 AH38 AJ39 AK39 AL41 AM41 AN40 AM40 AM39 AN39 AR42 AT42 AT1 AR1 AN4 AM4 AM3 AN3 AM2 AL2 AK4 AJ4 AH5 AG5 P6 N6 L3 K3 M5 L4 K4 A2 A41 AA20 AA23 AA3 AA39 AB20 AB23 AB4 AB40 AC17 AC19 AC21 AC22 Ball Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function PL95A PL95B PL100A PL100B PL105A PL105B PL108A PL108B PL111A PL111B PL113A PL113B PR113B PR113A PR111B PR111A PR108B PR108A PR105B PR105A PR100B PR100A PR95B PR95A PR39B PR39A PR36B PR36A PR35A PR32B PR32A GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank 6 6 6 6 6 6 6 6 6 6 6 6 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 LFSC/M115 Dual Function 4-137 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AC24 AC26 AC35 AC8 AD12 AD16 AD18 AD20 AD23 AD25 AD27 AD31 AE17 AE19 AE24 AE26 AE3 AE39 AF18 AF20 AF23 AF25 AF36 AF7 AG11 AG16 AG19 AG24 AG27 AG32 AH15 AH28 AH4 AH40 AJ35 AJ8 AK12 AK31 AL13 AL19 AL24 AL3 AL30 AL39 AM16 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M115 Dual Function 4-138 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AM27 AM36 AM7 AP4 AP40 AR14 AR20 AR23 AR29 AR35 AR8 AT11 AT17 AT26 AT32 AU3 AU39 AW12 AW18 AW22 AW28 AW34 AW6 AY15 AY21 AY25 AY31 AY37 AY9 B1 B42 BA1 BA42 BB2 BB41 C10 C12 C13 C16 C18 C19 C22 C24 C27 C28 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M115 Dual Function 4-139 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number C3 C30 C33 C35 C36 C39 C4 C40 C7 C8 D15 D21 D25 D31 F4 F40 G11 G17 G26 G32 H14 H20 H23 H29 H35 H8 J3 J39 L16 L27 L36 L7 M19 M24 M4 M40 N12 N31 P35 P8 R15 R28 R3 R39 T11 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCIO Bank LFSC/M115 Dual Function 4-140 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number T16 T19 T24 T27 T32 U18 U20 U23 U25 U36 U7 G36 G7 V17 V19 V24 V26 V4 V40 W12 W16 W18 W20 W23 W25 W27 W31 Y17 Y19 Y21 Y22 AA17 AA18 AA19 AA21 AA22 AA24 AA25 AA26 AB17 AB18 AB19 AB21 AB22 AB24 Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank Dual Function Ball Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank LFSC/M115 Dual Function 4-141 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AB25 AB26 AC16 AC18 AC20 AC23 AC25 AC27 AD17 AD19 AD21 AD22 AD24 AD26 AE16 AE18 AE20 AE21 AE22 AE23 AE25 AE27 AF17 AF19 AF21 AF22 AF24 AF26 AG18 AG20 AG23 AG25 T18 T20 T23 T25 U17 U19 U21 U22 U24 U26 V16 V18 V20 Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank Dual Function Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIO Bank LFSC/M115 Dual Function 4-142 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number V21 V22 V23 V25 V27 W17 W19 W21 W22 W24 W26 Y16 Y18 Y20 Y23 Y25 Y27 AG22 AG26 T17 T21 T22 T26 U16 U27 AC15 AC28 AD15 AD28 AE15 AE28 AF15 AF28 AG15 AG28 AH14 AH16 AH17 AH18 AH19 AH20 AH23 AH24 AH25 AH26 Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO Bank Dual Function Ball Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO Bank LFSC/M115 Dual Function 4-143 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AH27 AH29 AJ14 AJ15 AJ28 AJ29 P14 P15 P28 P29 R14 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R29 T15 T28 U15 U28 V15 V28 W15 W28 Y15 Y28 F3 F39 G35 G8 L19 L24 M16 M27 N11 N32 AA4 H7 J4 Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO Bank Dual Function Ball Function VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO Bank LFSC/M115 Dual Function 4-144 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number L8 M3 P7 R4 T12 U8 V3 W11 Y7 AB3 AC7 AD11 AE4 AF8 AG12 AH3 AJ7 AK11 AL4 AM8 AP3 AR7 AU4 AL16 AM13 AM19 AR11 AR17 AT14 AT20 AT8 AW15 AW21 AW9 AY12 AY18 AY6 AL27 AM24 AM30 AR26 AR32 AT23 AT29 AT35 Ball Function VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO Bank Dual Function Ball Function VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO Bank LFSC/M115 Dual Function 4-145 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AW25 AW31 AW37 AY22 AY28 AY34 AB39 AC36 AD32 AE40 AF35 AG31 AH39 AJ36 AK32 AL40 AM35 AP39 AR36 AU40 AA40 H36 J40 L35 M39 P36 R40 T31 U35 V39 W32 Y36 AA14 AA15 R12 V14 AB14 AB15 AE14 AJ13 AH21 AJ18 AJ19 AJ20 AJ21 Ball Function VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VTT_2 VTT_2 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_4 VTT_4 VCCIO Bank 2 2 2 2 3 3 3 3 4 4 4 4 4 Dual Function Ball Function VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VTT_2 VTT_2 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 VTT_4 VTT_4 VCCIO Bank 2 2 2 2 3 3 3 3 4 4 4 4 4 LFSC/M115 Dual Function 4-146 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA1, 2 (Cont.) LFSC/M80 Ball Number AH22 AJ22 AJ23 AJ24 AJ25 AB28 AB29 AE29 AJ30 AA28 AA29 R31 V29 Y24 Y26 Y8 Y35 AA16 AA27 AB16 AB27 AF16 AF27 AG17 AG21 G33 G10 M15 L15 K16 J16 M18 L18 M25 L25 J27 K27 L28 M28 Ball Function VTT_5 VTT_5 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VTT_7 VTT_7 GND GND GND GND VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIO Bank 5 5 5 5 5 6 6 6 6 7 7 7 7 Dual Function Ball Function VTT_5 VTT_5 VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VTT_7 VTT_7 GND GND GND GND VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 VCC12 NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIO Bank 5 5 5 5 5 6 6 6 6 7 7 7 7 LFSC/M115 Dual Function 1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). 2. The LatticeSC/M80 and LatticeSC/M115 in a 1704-pin package supports a 32-bit MPI interface. 4-147 Lattice Semiconductor Pinout Information LatticeSC/M Family Data Sheet Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Designers must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For Further Information For further information regarding Thermal Management, refer to the following located on the Lattice website at www.latticesemi.com. • Thermal Management document • Technical Note TN1101 - Power Estimation and Management for LatticeSC Devices • Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from www.latticesemi.com/software 4-148 LatticeSC/M Family Data Sheet Ordering Information November 2007 Data Sheet DS1004 Part Number Description LF XXX XXX XX E PX – X XXXXXX X LF = Lattice FPGA Device Family LatticeSC FPGA LatticeSCM FPGA SERDES Speed 3GA = 3.8G Logic Capacity 15K LUTs 25K LUTs 40K LUTs 80K LUTs 115K LUTs Supply Voltage E = 1.2V Grade C = Commercial I = Industrial Package1 F256 = 256-ball fpBGA F900 = 900-ball fpBGA FF1020 = 1020-ball Organic fcBGA FC1152 = 1152-ball Ceramic fcBGA FC1704 = 1704-ball Ceramic fcBGA FN256 = 256-ball Lead-Free fpBGA FN900 = 900-ball Lead-Free fpBGA FFN1020 = 1020-ball Lead-Free Organic fcBGA FCN1152 = 1152-ball Lead-Free Ceramic fcBGA FCN1704 = 1704-ball Lead-Free Ceramic fcBGA Speed Grade -5 (Slowest) -6 -7 (Fastest)2 Predefined Function (LatticeSCM Only) P1 = Initial MACO Option 1. fpBGA = 1.0mm pitch BGA, fcBGA = 1.0mm flip-chip BGA (organic and ceramic). 2. Not available in the LatticeSC115 and LatticeSCM115 devices. Ordering Information Depending on the speed and temperature grade, the device can either be dual marked or single marked. The commercial grade is one speed grade faster than the associated dual marked industrial grade. The slowest commercial speed grade does not have industrial markings. The markings appear as follows: LFSC3GA25E 6F900C-5I XXXXXXXX or LFSC3GA25E 7F900C XXXXXXXX Temperature Grade Commercial Speed Grade -7 -6 -5 -6 -5 Single or Dual Mark? Either OK Dual Only Single Only Either OK Dual Only Industrial © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 5-1 DS1004 Ordering Information_01.6 Lattice Semiconductor Conventional Packaging Commercial Part Number LFSC3GA15E-7F256C LFSC3GA15E-6F256C LFSC3GA15E-5F256C LFSC3GA15E-7F900C LFSC3GA15E-6F900C LFSC3GA15E-5F900C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Balls 256 256 256 900 900 900 Ordering Information LatticeSC/M Family Data Sheet Temp. COM COM COM COM COM COM LUTs (K) 15.2 15.2 15.2 15.2 15.2 15.2 Part Number LFSCM3GA15EP1-7F256C LFSCM3GA15EP1-6F256C LFSCM3GA15EP1-5F256C LFSCM3GA15EP1-7F900C LFSCM3GA15EP1-6F900C LFSCM3GA15EP1-5F900C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Balls 256 256 256 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 15.2 15.2 15.2 15.2 15.2 15.2 Part Number LFSC3GA25E-7F900C LFSC3GA25E-6F900C LFSC3GA25E-5F900C LFSC3GA25E-7FF1020C LFSC3GA25E-6FF1020C LFSC3GA25E-5FF1020C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fcBGA fcBGA fcBGA Balls 900 900 900 1020 1020 1020 Temp. COM COM COM COM COM COM LUTs (K) 25.4 25.4 25.4 25.4 25.4 25.4 Part Number LFSCM3GA25EP1-7F900C LFSCM3GA25EP1-6F900C LFSCM3GA25EP1-5F900C LFSCM3GA25EP1-7FF1020C LFSCM3GA25EP1-6FF1020C LFSCM3GA25EP1-5FF1020C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fcBGA fcBGA fcBGA Balls 900 900 900 1020 1020 1020 Temp. COM COM COM COM COM COM LUTs (K) 25.4 25.4 25.4 25.4 25.4 25.4 Part Number LFSC3GA40E-7FF1020C LFSC3GA40E-6FF1020C LFSC3GA40E-5FF1020C LFSC3GA40E-7FC1152C LFSC3GA40E-6FC1152C LFSC3GA40E-5FC1152C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Balls 1020 1020 1020 1152 1152 1152 Temp. COM COM COM COM COM COM LUTs (K) 40.4 40.4 40.4 40.4 40.4 40.4 5-2 Lattice Semiconductor Commercial (Cont.) Part Number LFSCM3GA40EP1-7FF1020C LFSCM3GA40EP1-6FF1020C LFSCM3GA40EP1-5FF1020C LFSCM3GA40EP1-7FC1152C LFSCM3GA40EP1-6FC1152C LFSCM3GA40EP1-5FC1152C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Ordering Information LatticeSC/M Family Data Sheet Balls 1020 1020 1020 1152 1152 1152 Temp. COM COM COM COM COM COM LUTs (K) 40.4 40.4 40.4 40.4 40.4 40.4 Part Number LFSC3GA80E-7FC1152C LFSC3GA80E-6FC1152C LFSC3GA80E-5FC1152C LFSC3GA80E-7FC1704C LFSC3GA80E-6FC1704C LFSC3GA80E-5FC1704C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1152 1704 1704 1704 Temp. COM COM COM COM COM COM LUTs (K) 80.1 80.1 80.1 80.1 80.1 80.1 Part Number LFSCM3GA80EP1-7FC1152C LFSCM3GA80EP1-6FC1152C LFSCM3GA80EP1-5FC1152C LFSCM3GA80EP1-7FC1704C LFSCM3GA80EP1-6FC1704C LFSCM3GA80EP1-5FC1704C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1152 1704 1704 1704 Temp. COM COM COM COM COM COM LUTs (K) 80.1 80.1 80.1 80.1 80.1 80.1 Part Number LFSC3GA115E-6FC1152C LFSC3GA115E-5FC1152C LFSC3GA115E-6FC1704C LFSC3GA115E-5FC1704C Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. COM COM COM COM LUTs (K) 115.2 115.2 115.2 115.2 Part Number LFSCM3GA115EP1-6FC1152C LFSCM3GA115EP1-5FC1152C LFSCM3GA115EP1-6FC1704C LFSCM3GA115EP1-5FC1704C Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. COM COM COM COM LUTs (K) 115.2 115.2 115.2 115.2 5-3 Lattice Semiconductor Industrial Part Number LFSC3GA15E-6F256I LFSC3GA15E-5F256I LFSC3GA15E-6F900I LFSC3GA15E-5F900I Grade -6 -5 -6 -5 Package fpBGA fpBGA fpBGA fpBGA Balls 256 256 900 900 Ordering Information LatticeSC/M Family Data Sheet Temp. IND IND IND IND LUTs (K) 15.2 15.2 15.2 15.2 Part Number LFSCM3GA15EP1-6F256I LFSCM3GA15EP1-5F256I LFSCM3GA15EP1-6F900I LFSCM3GA15EP1-5F900I Grade -6 -5 -6 -5 Package fpBGA fpBGA fpBGA fpBGA Balls 256 256 900 900 Temp. IND IND IND IND LUTs (K) 15.2 15.2 15.2 15.2 Part Number LFSC3GA25E-6F900I LFSC3GA25E-5F900I LFSC3GA25E-6FF1020I LFSC3GA25E-5FF1020I Grade -6 -5 -6 -5 Package fpBGA fpBGA fcBGA fcBGA Balls 900 900 1020 1020 Temp. IND IND IND IND LUTs (K) 25.4 25.4 25.4 25.4 Part Number LFSCM3GA25EP1-6F900I LFSCM3GA25EP1-5F900I LFSCM3GA25EP1-6FF1020I LFSCM3GA25EP1-5FF1020I Grade -6 -5 -6 -5 Package fpBGA fpBGA fcBGA fcBGA Balls 900 900 1020 1020 Temp. IND IND IND IND LUTs (K) 25.4 25.4 25.4 25.4 Part Number LFSC3GA40E-6FF1020I LFSC3GA40E-5FF1020I LFSC3GA40E-6FC1152I LFSC3GA40E-5FC1152I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1020 1020 1152 1152 Temp. IND IND IND IND LUTs (K) 40.4 40.4 40.4 40.4 Part Number LFSCM3GA40EP1-6FF1020I LFSCM3GA40EP1-5FF1020I LFSCM3GA40EP1-6FC1152I LFSCM3GA40EP1-5FC1152I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1020 1020 1152 1152 Temp. IND IND IND IND LUTs (K) 40.4 40.4 40.4 40.4 5-4 Lattice Semiconductor Industrial (Cont.) Part Number LFSC3GA80E-6FC1152I LFSC3GA80E-5FC1152I LFSC3GA80E-6FC1704I LFSC3GA80E-5FC1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Ordering Information LatticeSC/M Family Data Sheet Temp. IND IND IND IND LUTs (K) 80.1 80.1 80.1 80.1 Part Number LFSCM3GA80EP1-6FC1152I LFSCM3GA80EP1-5FC1152I LFSCM3GA80EP1-6FC1704I LFSCM3GA80EP1-5FC1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. IND IND IND IND LUTs (K) 80.1 80.1 80.1 80.1 Part Number LFSC3GA115E-6FC1152I LFSC3GA115E-5FC1152I LFSC3GA115E-6FC1704I LFSC3GA115E-5FC1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. IND IND IND IND LUTs (K) 115.2 115.2 115.2 115.2 Part Number LFSCM3GA115EP1-6FC1152I LFSCM3GA115EP1-5FC1152I LFSCM3GA115EP1-6FC1704I LFSCM3GA115EP1-5FC1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. IND IND IND IND LUTs (K) 115.2 115.2 115.2 115.2 5-5 Lattice Semiconductor Lead-Free Packaging Commercial Part Number LFSC3GA15E-7FN256C LFSC3GA15E-6FN256C LFSC3GA15E-5FN256C LFSC3GA15E-7FN900C LFSC3GA15E-6FN900C LFSC3GA15E-5FN900C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeSC/M Family Data Sheet Balls 256 256 256 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 15.2 15.2 15.2 15.2 15.2 15.2 Part Number LFSCM3GA15EP1-7FN256C LFSCM3GA15EP1-6FN256C LFSCM3GA15EP1-5FN256C LFSCM3GA15EP1-7FN900C LFSCM3GA15EP1-6FN900C LFSCM3GA15EP1-5FN900C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fpBGA fpBGA fpBGA Balls 256 256 256 900 900 900 Temp. COM COM COM COM COM COM LUTs (K) 15.2 15.2 15.2 15.2 15.2 15.2 Part Number LFSC3GA25E-7FN900C LFSC3GA25E-6FN900C LFSC3GA25E-5FN900C LFSC3GA25E-7FFN1020C LFSC3GA25E-6FFN1020C LFSC3GA25E-5FFN1020C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fcBGA fcBGA fcBGA Balls 900 900 900 1020 1020 1020 Temp. COM COM COM COM COM COM LUTs (K) 25.4 25.4 25.4 25.4 25.4 25.4 Part Number LFSCM3GA25EP1-7FN900C LFSCM3GA25EP1-6FN900C LFSCM3GA25EP1-5FN900C LFSCM3GA25EP1-7FFN1020C LFSCM3GA25EP1-6FFN1020C LFSCM3GA25EP1-5FFN1020C Grade -7 -6 -5 -7 -6 -5 Package fpBGA fpBGA fpBGA fcBGA fcBGA fcBGA Balls 900 900 900 1020 1020 1020 Temp. COM COM COM COM COM COM LUTs (K) 25.4 25.4 25.4 25.4 25.4 25.4 Part Number LFSC3GA40E-7FFN1020C LFSC3GA40E-6FFN1020C LFSC3GA40E-5FFN1020C LFSC3GA40E-7FCN1152C LFSC3GA40E-6FCN1152C LFSC3GA40E-5FCN1152C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Balls 1020 1020 1020 1152 1152 1152 Temp. COM COM COM COM COM COM LUTs (K) 40.4 40.4 40.4 40.4 40.4 40.4 5-6 Lattice Semiconductor Commercial (Cont.) Part Number LFSCM3GA40EP1-7FFN1020C LFSCM3GA40EP1-6FFN1020C LFSCM3GA40EP1-5FFN1020C LFSCM3GA40EP1-7FCN1152C LFSCM3GA40EP1-6FCN1152C LFSCM3GA40EP1-5FCN1152C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Ordering Information LatticeSC/M Family Data Sheet Balls 1020 1020 1020 1152 1152 1152 Temp. COM COM COM COM COM COM LUTs (K) 40.4 40.4 40.4 40.4 40.4 40.4 Part Number LFSC3GA80E-7FCN1152C LFSC3GA80E-6FCN1152C LFSC3GA80E-5FCN1152C LFSC3GA80E-7FCN1704C LFSC3GA80E-6FCN1704C LFSC3GA80E-5FCN1704C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1152 1704 1704 1704 Temp. COM COM COM COM COM COM LUTs (K) 80.1 80.1 80.1 80.1 80.1 80.1 Part Number LFSCM3GA80EP1-7FCN1152C LFSCM3GA80EP1-6FCN1152C LFSCM3GA80EP1-5FCN1152C LFSCM3GA80EP1-7FCN1704C LFSCM3GA80EP1-6FCN1704C LFSCM3GA80EP1-5FCN1704C Grade -7 -6 -5 -7 -6 -5 Package fcBGA fcBGA fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1152 1704 1704 1704 Temp. COM COM COM COM COM COM LUTs (K) 80.1 80.1 80.1 80.1 80.1 80.1 Part Number LFSC3GA115E-6FCN1152C LFSC3GA115E-5FCN1152C LFSC3GA115E-6FCN1704C LFSC3GA115E-5FCN1704C Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. COM COM COM COM LUTs (K) 115.2 115.2 115.2 115.2 Part Number LFSCM3GA115EP1-6FCN1152C LFSCM3GA115EP1-5FCN1152C LFSCM3GA115EP1-6FCN1704C LFSCM3GA115EP1-5FCN1704C Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. COM COM COM COM LUTs (K) 115.2 115.2 115.2 115.2 5-7 Lattice Semiconductor Industrial Part Number LFSC3GA15E-6FN256I LFSC3GA15E-5FN256I LFSC3GA15E-6FN900I LFSC3GA15E-5FN900I Grade -6 -5 -6 -5 Package fpBGA fpBGA fpBGA fpBGA Ordering Information LatticeSC/M Family Data Sheet Balls 256 256 900 900 Temp. IND IND IND IND LUTs (K) 15.2 15.2 15.2 15.2 Part Number LFSCM3GA15EP1-6FN256I LFSCM3GA15EP1-5FN256I LFSCM3GA15EP1-6FN900I LFSCM3GA15EP1-5FN900I Grade -6 -5 -6 -5 Package fpBGA fpBGA fpBGA fpBGA Balls 256 256 900 900 Temp. IND IND IND IND LUTs (K) 15.2 15.2 15.2 15.2 Part Number LFSC3GA25E-6FN900I LFSC3GA25E-5FN900I LFSC3GA25E-6FFN1020I LFSC3GA25E-5FFN1020I Grade -6 -5 -6 -5 Package fpBGA fpBGA fcBGA fcBGA Balls 900 900 1020 1020 Temp. IND IND IND IND LUTs (K) 25.4 25.4 25.4 25.4 Part Number LFSCM3GA25EP1-6FN900I LFSCM3GA25EP1-5FN900I LFSCM3GA25EP1-6FFN1020I LFSCM3GA25EP1-5FFN1020I Grade -6 -5 -6 -5 Package fpBGA fpBGA fcBGA fcBGA Balls 900 900 1020 1020 Temp. IND IND IND IND LUTs (K) 25.4 25.4 25.4 25.4 Part Number LFSC3GA40E-6FFN1020I LFSC3GA40E-5FFN1020I LFSC3GA40E-6FCN1152I LFSC3GA40E-5FCN1152I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1020 1020 1152 1152 Temp. IND IND IND IND LUTs (K) 40.4 40.4 40.4 40.4 Part Number LFSCM3GA40EP1-6FFN1020I LFSCM3GA40EP1-5FFN1020I LFSCM3GA40EP1-6FCN1152I LFSCM3GA40EP1-5FCN1152I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1020 1020 1152 1152 Temp. IND IND IND IND LUTs (K) 40.4 40.4 40.4 40.4 5-8 Lattice Semiconductor Industrial (Cont.) Part Number LFSC3GA80E-6FCN1152I LFSC3GA80E-5FCN1152I LFSC3GA80E-6FCN1704I LFSC3GA80E-5FCN1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Ordering Information LatticeSC/M Family Data Sheet Balls 1152 1152 1704 1704 Temp. IND IND IND IND LUTs (K) 80.1 80.1 80.1 80.1 Part Number LFSCM3GA80EP1-6FCN1152I LFSCM3GA80EP1-5FCN1152I LFSCM3GA80EP1-6FCN1704I LFSCM3GA80EP1-5FCN1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. IND IND IND IND LUTs (K) 80.1 80.1 80.1 80.1 Part Number LFSC3GA115E-6FCN1152I LFSC3GA115E-5FCN1152I LFSC3GA115E-6FCN1704I LFSC3GA115E-5FCN1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. IND IND IND IND LUTs (K) 115.2 115.2 115.2 115.2 Part Number LFSCM3GA115EP1-6FCN1152I LFSCM3GA115EP1-5FCN1152I LFSCM3GA115EP1-6FCN1704I LFSCM3GA115EP1-5FCN1704I Grade -6 -5 -6 -5 Package fcBGA fcBGA fcBGA fcBGA Balls 1152 1152 1704 1704 Temp. IND IND IND IND LUTs (K) 115.2 115.2 115.2 115.2 5-9 LatticeSC/M Family Data Sheet Supplemental Information January 2008 Data Sheet DS1004 For Further Information For further information about the flexiPCS see the LatticeSC/M Family flexiPCS Data Sheet available on the Lattice Semiconductor website at www.latticesemi.com. A variety of technical notes for the LatticeSC/M family are also available on the Lattice Semiconductor website at www.latticesemi.com. • • • • • • • • • • • • • • • • • LatticeSC PURESPEED I/O Usage Guide (TN1088) LatticeSC PURESPEED I/O Adaptive Input Logic User Guide (TN1158) LatticeSC sysCLOCK and PLL/DLL User’s Guide (TN1098) On-Chip Memory Usage Guide for LatticeSC Devices (TN1094) LatticeSC DDR/DDR2 SDRAM Memory Interface User’s Guide (TN1099) LatticeSC QDRII/QDRII+ SRAM Memory Interface User’s Guide (TN1096) LatticeSC sysCONFIG Usage Guide (TN1080) LatticeSC MPI/System Bus (TN1085) SPI Serial Flash Programming Using ispJTAG in LaticeSC Devices (TN1100) Power Estimation and Management for LatticeSC Devices (TN1101) LatticeSC SERDES Jitter (TN1084) LatticeSC FPGAs: Implementing 3.3V Interfaces in 2.5V VCCIO Banks (TN1110) Lattice PCI Express Demo User Guide (TN1123) LatticeSC flexiPCS/SERDES Design Guide (TN1145) Temperature Sensing Diode in LatticeSC Devices (TN1115) SPI4.2 Interoperability with ORSPI4 in LatticeSC Devices (TN1116) LatticeSC/M Hold Time Optimization (TN1117) For further information on Interface standards refer to the following websites: • • • • • JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org Hyper Transport: www.hyper transpor t.org Optical Interface (SPI-4.2, XSBI, CSIX and XGMII): www.oiforum.com RAPIDIO: www.rapidio.org PCI/PCIX: ww.pcisig.com © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 6-1 DS 1004 Further Information_01.2 LatticeSC/M Family Data Sheet Revision History June 2008 Date February 2006 March 2006 Version 01.0 01.1 Section — Introduction Architecture Initial release. SC25 1020 I/O count changed to 476. Changed ROM 16X4 to ROM 16X2. Changed “X2 or X4” to “DIV2 or DIV4”. Added Global Set/Reset Section. DC and Switching Characteristics Added notes 5 and 6 to Recommended Operating Conditions table. Added Power Supply Ramp Rates table. Removed -5 and -6 speed grades from Typical Building Block Performance table. Added Input Delay Timing table. Added Synchronous GSR Timing table. Pinout Information Expanded PROBE_VCC and PROBE_GND description. Removed A-RXREFCLKP_[L/R] from Signal Description table. Added RESP_[ULC/URC] to Signal Description table. Added notes 1 and 2 to Signal Description table. Changed number of NCs to 28. Changed number of SERDES (signal + power supply) to 74. Removed RESP balls from NC list (B2, C2, B29, C29). Added note to VTT table. Changed RxRefclk (B2 and C2) to NC. Added RESP_ULC. Added RESP_URC. Changed RxRefclk (B29 and C29) to NC. June 2006 01.2 Introduction Changed SERDES min bandwidth from 622 Mbps to 600 Mbps. Changed max SERDES bandwidth from 3.4 Gbps to 3.8 Gbps. Corrected number of package I/Os for the SC80 and SC115 1704 pin packages. Updated speed performance for typical functions with ispLEVER 6.0 values. Architecture Changed “When these pins are not used they should be left unconnected.” with “Unused VTT pins should be connected to GND if the internal or external VCMT function is not used in the bank. If the internal or external VCMT function for differential input termination is used, the VTT pins should be unconnected and allowed to float.” Added “SERDES Power Supply Sequencing Requirements” section. Changed total bandwidth per quad from 13.6 Gbps to 15.2 Gbps. Added the accuracy of the temperature-sensing diode to be typically +/10 °C. Also referred to a temperature-sensing diode application note for more information. DC and Switching Characteristics Changed “CTAP” to “internal or external VCMT”. Changed VCC12 parameter to include VDDP, VDDTX and VDDRX. Changed typical values to match ispLEVER 6.0 Power Calculator. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Data Sheet DS1004 Change Summary www.latticesemi.com 7-1 DS 1004 Revision History Lattice Semiconductor Date June 2006 (cont.) Version 01.2 (cont.) Section Revision History LatticeSC/M Family Data Sheet Change Summary DC and Switching Updated Typical Building Block Performance with ispLEVER 6.0 values. Characteristics (cont.) Updated LatticeSC External Switching Characteristics with ispLEVER 6.0 values. Updated Lattice SC Internal Timing Parameters with ispLEVER 6.0 values. Updated Lattice SC Family Timing Adders with ispLEVER 6.0 values Changed % spread from 1 to 0.5 min and from 3 to 1.5 max. Changed conditions to refer to “with multiplication” and “without multiplication”. Changed the formula for tOPJIT with multiplication (same result, different representation). Pinout Information Expanded definition of NC. Expanded definition of GND. Expanded definition of VTT_x. Expanded definition of VCC12. Added accuracy of TEMP pin. Added RESPN_[ULC/URC]. Updated Pin Information Summary with additional devices and packages. Added additional devices and packages pinouts. Removed Power Supply and NC connections table Removed VTT table Removed LFSC25 Logic Signal Connections: 900-Ball ffBGA1 table Changed all VDDP, VDDTX and VDDRX to VCC12. Ordering Information Added dual marking. Added lead free packaging information to part number description. Added SC40 1152 information to Table 1-1. Updated Table 1-3 with ispLEVER 6.0 SP1 results. Architecture Added SSTL18 II to Table 2-8. Changed Table 2-10 VCCIO column to “N/A” for LVDS, mini-LVDS, BLVDS25, MLVDS25, HYPT and RSDS. Changed Hypertransport performance to 700 MHz (1400 Mbps) in Table 2-11. Changed SPI4.2 performance to 500 MHz (1000 Mbps) in Table 2-11 Added “On packages that include PROBE_GND, the most accurate measurements will occur between the TEMP pin and the PROBE_GND pin. On packages that do not include PROBE_GND, measurements should be made between the TEMP pin and board ground.” Added VCCIO of 2.5 V for LVPECL33 in table 2-9. DC and Switching Characteristics Updated Typical Building Block Performance with ispLEVER 6.0 SP1 results. Updated Initialization and Standby Supply Current table to break out ICC and ICC12. Updated LatticeSC External Switching Characteristics with ispLEVER 6.0 SP1 results. Updated LatticeSC Internal Timing Parameters with ispLEVER 6.0 SP1 results. August 2006 01.3 Introduction 7-2 Lattice Semiconductor Date August 2006 (cont.) Version 01.3 (cont.) Section DC and Switching Characteristics (cont.) Revision History LatticeSC/M Family Data Sheet Change Summary Updated LatticeSC Family Timing Adders with ispLEVER 6.0 SP1 results Updated PLL Timing Parameters based on PDE testing results Removed RDDATA parameter from sysCONFIG readback timing table Multiple Pinout Information Changed TDO/RDDATA to TDO Removed all MPI signals from SC15 256 pin package Dual Function Column Added note to SC15, SC25 900 pin package that the package supports a 16 bit MPI Added note that pin D3 in an SC15 and SC25 900 pin package should not be used for single-ended outputs Added note that pin D28 in an SC15 and SC25 900 pin package should not be used for single-ended outputs Added note to SC25 1020 pin package that the package supports a 16 bit MPI Added note to SC80 1152 pin package that the package supports a 32 bit MPI Added note to SC80 1704 pin package that the package supports a 32 bit MPI Ordering Information November 2006 01.4 Introduction Changed “fcBGA” for the 1020 packages to “ffBGA” LatticeSC Family Selection Guide table – I/O count for SC80 device, 1704 fcBGA package changed to 904/32. I/O count for SC115 device, 1704 fcBGA package changed to 942/32. DC Electrical Characteristics table – Updated the initialization and standby supply current values. DC Electrical Characteristics table – Updated the sysCONFIG Master Parallel mode RCLK low and RCLK high time specifications. DC Electrical Characteristics table – Updated VCCIO values for LVPECL33 I/Os. DC and Switching Characteristics Pin Information Pin Information Summary table - Changed number of single ended user I/Os from 906 to 904 for 1704 fcBGA. Removed the single-ended only output restriction on pins D3 and D28 in an SC15 and SC25 900 pin package. Ordering Information Ordering Information tables - Changed number of I/Os from 906 to 904 for 1704 fcBGA. Added ordering part numbers for LatticeSC/SCM 40K and 115K LUT devices. Added lead-free ordering part numbers. Multiple January 2007 February 2007 March 2007 01.4a 01.4b 01.5 Architecture Architecture Architecture DC and Switching Characteristics Changed number of available SC80 I/O from 906 to 904. Changed number of available SC115 I/O from 944 to 942. Added EBR Asynchronous Reset section. Updated EBR Asynchronous Reset section. Added EBR asynchronous reset clarification Clarified that differential drivers are not supported in banks 1, 4 and 5 Added clarification for the description of the junction temperature specification in the Absolute Maximum Ratings section. Updated Initialization and Standby Current table. Updated LatticeSC External Switching Characteristics with ispLEVER 6.1 SP1 results. 7-3 Lattice Semiconductor Date March 2007 (cont.) Version 01.5 (cont.) Section Revision History LatticeSC/M Family Data Sheet Change Summary DC and Switching Updated LatticeSC Internal Timing Parameters with ispLEVER 6.1 SP1 Characteristics (cont.) results. Updated tFDEL and tCDEL specifications. Updated LatticeSC Family Timing Adders with ispLEVER 6.1 SP1 results. Updated PLL specifications to expand frequency range down to 2 MHz and break out jitter for the different ranges. Added footnote to sysCLOCK PLL Timing table specifying the conditions for the jitter measurements. Added tDLL specification to sysCLOCK DLL Timing table. Added footnote to sysCLOCK DLL Timing table specifying the conditions for the jitter measurements. Added sysCONFIG Master Parallel Configuration Mode and sysCONFIG SPI Port to LatticeSC sysCONFIG Port Timing table. Pin Information Updated Pin Information Summary with SC40 information. Updated LFSC25 Logic Signal Connections: FF1020 with SC40 information. Updated LFSC80 Logic Signal Connections: FC1152 with SC40 information. August 2007 01.6 General Changed references of "HDC" to "HDC/SI". Changed references of "LDCN" to "LDCN/SCS". Changed references of "BUSYN/RCLK" to "BUSYN/RCLK/SCK". Changed references of "RDCFGN" to "TSALLN". Changed references of "TDO/RDDATA" to "TDO". Architecture Updated text in Ripple Mode section. Added information to Global Set/Reset. Added information for Spread Spectrum Clocking Modified information for PLL/DLL Cascading. DLL to PLL is now supported. Modified AIL Block text and figure. Modified Figure 2-20 DDR/Shift Register Block. Added Information to Hot Socketing. Added new information for I/O Architecture Rules. Added information to SERDES Power Supply Sequencing Requirements. DC and Switching Characteristics Added footnote to Hot Socketing Specifications table. Modified Initialization and Standby Supply Current table. Modified GSR Timing table. Modified sysCLOCK DLL Timing table to include IDUTY. Deleted Readback Timing information from sysCONFIG Port Timing table. Modified data in External Switching Characteristics table. Pin Information Added information to the Signal Descriptions table for HDC/SI, LDCN/ SCS. Added footnote to Signal Descriptions table. Modified Description for signal BUSYN/RCLK/SCK. Modified data in Pin Information Summary and device-specific Pinout Information tables. 7-4 Lattice Semiconductor Date September 2007 Version 01.7 Section Pinout Information Supplemental Information November 2007 January 2008 01.8 01.9 Ordering Information Introduction Architecture Updated title list. Revision History LatticeSC/M Family Data Sheet Change Summary Added Thermal Management text section. Removed -7 speed grade information for 115K LUT devices in the Ordering Information tables. Corrections/Additions to memory controller list (Tables 1-2). AIL Overview – Modified power used by AIL block. PURESPEED I/O Buffer Banks – Modified VTT termination info. Added info about complimentary drivers for all banks. Supported Source Synchronous Interfaces – Modified data for DDRII in Table 2-11. DC and Switching Characteristics Recommended Operating Conditions – Changed footnote 3. Initialization and Standby Supply Current – Inserted a paragraph with info regarding the table. Also updated the table. Typical Building Block Function Performance – Added VCC=1.2V=1.2V+/-5% above Pin to Pin Performance table. LatticeSC External Switching Characteristics – Added VCC=1.2V=1.2V+/-5% above table. Reworded footnote 3. LatticeSC Family Timing Adders – Added VCC=1.2V=1.2V+/-5% above table. LatticeSC Internal Timing Parameters – Added VCC=1.2V=1.2V+/-5% above table. Reworded footnote 1. GSR Timing – Added a new table for Internal System Bus Timing after GSR Timing. LatticeSC sysCONFIG Port Timing – Corrected sysCONFIG SPI Port information. Pinout Information Supplemental Information March 2008 02.0 DC and Switching Characteristics Signal Descriptions – Modified info for VTT_x, PROBE_VCC, and PROBE_GND. Modified info for [LOC]_DLL[T,C]_IN[C,D,E,F]. Updated list of technical notes, added reference to LatticeSC/M flexiPCS Data Sheet. Updated Internal Timing Parameters table. Updated Read Mode timing diagram. Updated Read Mode with Input Registers Only timing diagram. Data sheet status changed from preliminary to final. Removed Read-Before-Write sysMEM EBR mode. Updated LatticeSC/M External Switching Characteristics table. Updated LatticeSC/M Internal Timing Parameters table. Removed Read-Before-Write sysMEM EBR mode. June 2008 02.1 — Architecture DC and Switching Characteristics 7-5