ORCA™ Series 3C and 3T FPGA Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue select devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
OR3C80
OR3T20
OR3T30
OR3T55
Ordering Part Number
OR3C805PS208-DB
OR3C804PS208-DB
OR3C804PS208I-DB
OR3C804BA352-DB
OR3T206T144-DB
OR3T207S208-DB
OR3T206S208-DB
OR3T206S208I-DB
OR3T207BA256-DB
OR3T206BA256-DB
OR3T307S208-DB
OR3T306S208-DB
OR3T306S208I-DB
OR3T307S240-DB
OR3T306S240-DB
OR3T306S240I-DB
OR3T307BA256-DB
OR3T306BA256-DB
OR3T306BA256I-DB
OR3T557S208-DB
OR3T556S208-DB
OR3T556S208I-DB
OR3T557PS240-DB
OR3T556PS240-DB
OR3T556PS240I-DB
Product Status
Reference PCN
Discontinued
PCN#02-06
Discontinued
PCN#09-10
Active / Orderable
Discontinued
PCN#12A-09
Active / Orderable
Active / Orderable
Discontinued
PCN#06-07
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
OR3T55
(Cont’d)
OR3T80
OR3T125
Ordering Part Number
OR3T557BA256-DB
OR3T556BA256-DB
OR3T556BA256I-DB
OR3T557BA352-DB
OR3T556BA352-DB
OR3T556BA352I-DB
OR3T807S208-DB
OR3T806S208-DB
OR3T806S208I-DB
OR3T807PS240-DB
OR3T806PS240-DB
OR3T806PS240I-DB
OR3T807BA352-DB
OR3T806BA352-DB
OR3T806BA352I-DB
OR3T807BC432-DB
OR3T806BC432-DB
OR3T806BC432I-DB
OR3T1257PS208-DB
OR3T1256PS208-DB
OR3T1256PS208I-DB
OR3T1257PS240-DB
OR3T1256PS240-DB
OR3T1256PS240I-DB
OR3T1257BA352-DB
OR3T1256BA352-DB
OR3T1256BA352I-DB
OR3T1257BC432-DB
OR3T1256BC432-DB
OR3T1256BC432I-DB
Product Status
Reference PCN
Active / Orderable
Discontinued
PCN#09-10
Discontinued
PCN#09-10
Discontinued
PCN#06-07
Discontinued
PCN#09-10
PCN#06-07
Discontinued
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Data Sheet
November 2006
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ORCA® Series 3C and 3T
Field-Programmable Gate Arrays
Features
■
■
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■
■
■
■
■
■
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■
High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 µm).
Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See ORCA
Series 3L FPGA documentation.)
Up to 186,000 usable gates.
Up to 342 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be disabled per PFU.
Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic flexibility of LUTs with independent inputs.
Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers, up to 10-bit decoder, and PAL*like AND-OR with optional INVERT in each programma-
■
■
■
■
■
■
■
■
■
ble logic cell (PLC), with over 50% speed improvement
typical.
Abundant hierarchical routing resources based on routing two data nibbles and two control lines per set provide
for faster place and route implementations and less routing delay.
TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan (IEEE † 1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
Up to four ExpressCLK inputs allow extremely fast clocking of signals on- and off-chip plus access to internal
general clock routing.
StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF) latch
for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain dive capability
— Capability to register 3-state enable signal.
Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
* PAL is a trademark of Advanced Micro Devices, Inc.
† IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA Series 3 (3C and 3T) FPGAs
Device
System
Gates‡
LUTs
Registers
Max User RAM
Max User
I/Os
Array Size
Process
Technology
OR3T20
36K
1152
1872
18K
192
12 x 12
0.3 µm/4 LM
OR3T30
48K
1568
2436
25K
221
14 x 14
0.3 µm/4 LM
OR3T55
80K
2592
3780
42K
288
18 x 18
0.3 µm/4 LM
OR3C/3T80
116K
3872
5412
62K
342
22 x 22
0.3 µm/4 LM
OR3T125
186K
6272
8400
100K
342
28 x 28
0.3 µm/4 LM
‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table of Contents
Contents
Page
Page
PCM Detailed Programming .................................... 78
PCM Applications .................................................... 81
PCM Cautions ......................................................... 82
FPGA States of Operation........................................ 83
Initialization .............................................................. 83
Configuration ........................................................... 84
Start-Up ................................................................... 85
Reconfiguration ....................................................... 86
Partial Reconfiguration ............................................ 86
Other Configuration Options .................................... 86
Using ispLEVER to Generate
Configuration RAM Data ....................................... 87
Configuration Data Frame ....................................... 87
Bit Stream Error Checking ....................................... 89
FPGA Configuration Modes...................................... 90
Master Parallel Mode ............................................... 90
Master Serial Mode ................................................. 91
Asynchronous Peripheral Mode .............................. 92
Microprocessor Interface (MPI) Mode ..................... 92
Slave Serial Mode ................................................... 95
Slave Parallel Mode ................................................. 95
Daisy-Chaining ........................................................ 96
Daisy-Chaining with Boundary Scan ....................... 97
Absolute Maximum Ratings...................................... 98
Recommended Operating Conditions ..................... 98
Electrical Characteristics .......................................... 99
Timing Characteristic Description .......................... 101
Description ............................................................. 101
PFU Timing ........................................................... 102
PLC Timing ............................................................ 109
SLIC Timing ........................................................... 109
PIO Timing ............................................................. 110
Special Function Blocks Timing ............................. 113
Clock Timing .......................................................... 121
Configuration Timing ............................................. 131
Readback Timing ................................................... 140
Input/Output Buffer Measurement Conditions ........ 141
Output Buffer Characteristics ................................. 142
OR3Cxx ................................................................. 142
OR3Txxx ................................................................ 143
Estimating Power Dissipation ................................. 144
OR3Cxx ................................................................. 144
OR3Txxx................................................................. 145
Pin Information ....................................................... 147
Pin Descriptions...................................................... 147
Package Compatibility ........................................... 151
Compatibility with OR2C/TxxA Series .................... 152
Package Thermal Characteristics........................... 188
FPGA Maximum Junction Temperature ................ 190
Package Coplanarity .............................................. 191
Package Parasitics ................................................. 191
Package Outline Diagrams..................................... 192
Lattice Semiconductor
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Features ......................................................................1
System-Level Features................................................4
Description...................................................................5
FPGA Overview ..........................................................5
PLC Logic ...................................................................5
Description (continued)................................................6
PIC Logic ....................................................................6
System Features ........................................................6
Routing .......................................................................6
Configuration ..............................................................6
Description (continued)................................................7
ispLEVER Development System ................................7
Architecture .................................................................7
Programmable Logic Cells ..........................................9
Programmable Function Unit ......................................9
Look-Up Table Operating Modes .............................11
Supplemental Logic and Interconnect Cell (SLIC).....19
PLC Latches/Flip-Flops ............................................23
PLC Routing Resources ...........................................25
PLC Architectural Description ...................................32
rogrammable Input/Output Cells................................34
5 V Tolerant I/O ........................................................35
PCI Compliant I/O .....................................................35
Inputs ........................................................................36
Outputs .....................................................................39
PIC Routing Resources ............................................42
PIC Architectural Description ....................................43
High-Level Routing Resources..................................45
Interquad Routing .....................................................45
Programmable Corner Cell Routing .........................46
PIC Interquad (MID) Routing ....................................47
Clock Distribution Network ........................................48
PFU Clock Sources ..................................................48
Clock Distribution in the PLC Array ..........................49
Clock Sources to the PLC Array ...............................50
Clocks in the PICs ....................................................50
ExpressCLK Inputs ...................................................51
Selecting Clock Input Pins ........................................51
Special Function Blocks ............................................52
Single Function Blocks .............................................52
Boundary Scan .........................................................55
Microprocessor Interface (MPI) .................................62
PowerPC System .....................................................63
i960 System ..............................................................64
MPI Interface to FPGA .............................................65
MPI Setup and Control .............................................66
Programmable Clock Manager (PCM) ......................70
PCM Registers .........................................................71
Delay-Locked Loop (DLL) Mode ...............................73
Phase-Locked Loop (PLL) Mode ..............................74
PCM/FPGA Internal Interface ...................................77
PCM Operation .........................................................77
2
Contents
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table of Contents
Contents
Page
Contents
Page
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Terms and Definitions .............................................192
144-Pin TQFP .........................................................193
208-Pin SQFP ........................................................194
208-Pin SQFP2 ......................................................195
240-Pin SQFP .........................................................196
240-Pin SQFP2 .......................................................197
256-Pin PBGA ........................................................198
352-Pin PBGA ........................................................199
432-Pin EBGA ........................................................200
Ordering Information................................................201
Lattice Semiconductor
3
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
System-Level Features
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as digital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCA Series 3 include:
Full PCI local bus compliance.
■
True, internal, 3-state, bidirectional buses with simple
control provided by the SLIC.
■
32 x 4 RAM per PFU, configurable as single- or dualport at >176 MHz. Create large, fast RAM/ROM
blocks (128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
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Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose interface to the FPGA. Glueless interface to i960 * and
PowerPC† processors with user-configurable
address space provided.
Parallel readback of configuration data capability with
the built-in microprocessor interface.
Programmable clock manager (PCM) adjusts clock
* i960 is a registered trademark of Intel Corporation.
† PowerPC is a registered trademark of International Business
Machines Corporation.
Table 2. ORCA Series 3 System Performance
Parameter
16-bit Loadable Up/Down Counter
16-bit Accumulator
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1
ROM Mode, Unpipelined2
Multiplier Mode, Pipelined3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
128 x 8 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs6
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs7
36-bit Parity Check (internal)
# PFUs
-4
Speed
-6
-5
-7
Unit
2
2
78
78
102
102
131
131
168
168
MHz
MHz
11.5
8
15
19
51
76
25
66
104
30
80
127
38
102
166
MHz
MHz
MHz
4
4
97
127
127
166
151
203
192
253
MHz
MHz
8
8
88
88
116
116
139
139
176
176
MHz
MHz
0.25
0
4.87
2.35
3.66
1.82
2.58
1.23
2.03
0.99
ns
ns
2
0
2
16.06
6.91
16.06
12.07
5.41
12.07
9.01
4.21
9.01
7.03
3.37
7.03
ns
ns
ns
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
4
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Description
PLC Logic
FPGA Overview
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used independently or with arithmetic functions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
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The ORCA Series 3 FPGAs are a new generation of
SRAM-based FPGAs built on the successful OR2C/
TxxA FPGA Series, with enhancements and innovations geared toward today’s high-speed designs and
tomorrow’s systems on a single chip. Designed from
the start to be synthesis friendly and to reduce place
and route times while maintaining the complete
routability of the ORCA 2C/2T devices, Series 3 more
than doubles the logic available in each logic block and
incorporates system-level features that can further
reduce logic requirements and increase system speed.
ORCA Series 3 devices contain many new patented
enhancements and are offered in a variety of packages, speed grades, and temperature ranges.
The ORCA Series 3 FPGAs consist of three basic elements: programmable logic cells (PLCs), programmable input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), local routing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU, but decoders,
PAL-like functions, and 3-state buffering can be performed in the SLIC. The PICs provide device inputs and
outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the system-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
Lattice Semiconductor
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT
(AOI) to perform PAL-like functions. The 3-state drivers
in the SLIC and their direct connections to the PFU outputs make fast, true 3-state buses possible within the
FPGA, reducing required routing and allowing for realworld system performance.
5
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Description (continued)
PIC Logic
Routing
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Series 3 PIC addresses the demand for ever-increasing system clock speeds. Each PIC contains four programmable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fastcapture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a system clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA 2C/2T capability to use any input
pin as a clock or other global input is maintained.
innovative programmable clock manager. These functional blocks allow for easy glueless system interfacing
and the capability to adjust to varying conditions in
today’s high-speed systems.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output signals.
The output FF in combination with output signal multiplexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
ORCA 2C/2T Series buffer with a new, fast, open-drain
option for ease of use on system buses.
System Features
The abundant routing resources of the ORCA Series 3
FPGAs are organized to route signals individually or as
buses with related control signals. Clocks are routed on
a low-skew, high-speed distribution network and may
be sourced from PLC logic, externally from any I/O
pad, or from the very fast ExpressCLK pins. ExpressCLKs may be glitchlessly and independently enabled
and disabled with a programmable control signal using
the new StopCLK feature. The improved PIC routing
resources are now similar to the patented intra-PLC
routing resources and provide great flexibility in moving
signals to and from the PIOs. This flexibility translates
into an improved capability to route designs at the
required speeds when the I/O signals have been
locked to specific pins.
Configuration
The FPGA’s functionality is determined by internal
configuration RAM. The FPGA’s internal initialization/
configuration circuitry loads the configuration data at
powerup or under system control. The RAM is loaded
by using one of several configuration modes. The configuration data resides externally in an EEPROM or any
other storage media. Serial EEPROMs provide a simple, low pin count method for configuring FPGAs. A
new, easy method for configuring the devices is
through the microprocessor interface.
Series 3 also provides system-level functionality by
means of its dual-use microprocessor interface and its
6
Lattice Semiconductor
Data Sheet
November 2006
Description (continued)
ispLEVER Development System
The OR3T55 array in Figure 1 has PLCs arranged in
an array of 18 rows and 18 columns. The location of a
PLC is indicated by its row and column so that a PLC in
the second row and the third column is R2C3. PICs are
located on all four sides of the FPGA between the
PLCs and the device edge. PICs are indicated using
PT and PB to designate PICs on the top and bottom
sides of the array, respectively, and PL and PR to designate PICs along the left and right sides of the array,
respectively. The position of a PIC on an edge of the
array is indicated by a number, counting from left to
right for PT and PB and top to bottom for PL and PR
PICs.
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The ispLEVER Development System is used to process a design from a netlist to a configured FPGA. This
system is used to map a design onto the ORCA architecture and then place and route it using ispLEVER’s
timing-driven tools. The development system also
includes interfaces to, and libraries for, other popular
CAE tools for design entry, synthesis, simulation, and
timing analysis.
ORCA Series 3C and 3T FPGAs
The ispLEVER Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPGA. In the design flow, the
user defines the functionality of the FPGA at two points
in the design flow: at design entry and at the bit stream
generation stage.
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPGA. A static timing analysis tool is provided to determine device speed and a back-annotated netlist can be
created to allow simulation. Timing and simulation output files from ispLEVER are also compatible with many
third-party analysis tools. Its bit stream generator is
then used to generate the configuration data which is
loaded into the FPGA’s internal configuration RAM.
When using the bit stream generator, the user selects
options that affect the functionality of the FPGA. Combined with the front-end tools, ispLEVER produces
configuration data that implements the various logic
and routing options discussed in this data sheet.
Architecture
The ORCA Series 3 FPGA comprises three basic elements: PLCs, PICs, and system-level functions. Figure
1 shows an array of programmable logic cells (PLCs)
surrounded by programmable input/output cells (PICs).
Also shown are the interquad routing blocks (hIQ, vIQ)
present in Series 3. System-level functions (located in
the corners of the array) and the routing resources and
configuration RAM are not shown in Figure 1.
Lattice Semiconductor
Each PIC contains routing resources and four programmable I/Os (PIOs). Each PIO contains the necessary
I/O buffers to interface to bond pads. PIOs in Series 3
FPGAs also contain input and output FFs, fast opendrain capability on output buffers, special output logic
functions, and signal multiplexing/demultiplexing capabilities.
PLCs comprise a programmable function unit (PFU), a
supplemental logic and interconnect cell (SLIC), and
routing resources. The PFU is the main logic element
of the PLC, containing elements for both combinatorial
and sequential logic. Combinatorial logic is done in
look-up tables (LUTs) located in the PFU. The PFU can
be used in different modes to meet different logic
requirements. The LUT’s twin-quad architecture provides a configurable medium-/large-grain architecture
that can be used to implement from one to eight independent combinatorial logic functions or a large number of complex logic functions using multiple LUTs. The
flexibility of the LUT to handle wide input functions, as
well as multiple smaller input functions, maximizes the
gate count per PFU while increasing system speed.
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In combinatorial mode, the LUTs can realize any 4- or 5-input
logic function and many multilevel logic functions using
ORCA’s softwired LUT (SWL) connections. In ripple
mode, the high-speed carry logic is used for arithmetic
functions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32 x 4 synchronous read/write or read-only memory, in
either single- or dual-port mode.
7
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Architecture (continued)
PT2
PT3
PT4
PT5
PT6
PT7
PT8
PT9
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
TMID
PT10
PT11
PT12
PT13
PT14
PT15
PT16
PT17
R1C10 R1C11 R1C12 R1C13 R1C14 R1C15 R1C16 R1C17
PT18
R1C18
PL2
R2C9
PL3
R3C1
R3C2
R3C3
R3C4
R3C5
R3C6
R3C7
R3C8
PL4
R4C1
R4C2
R4C3
R4C4
R4C5
R4C6
R4C7
PL5
R5C1
R5C2
R5C3
R5C4
R5C5
R5C6
PL6
R6C1
R6C2
R6C3
R6C4
R6C5
PL7
R7C1
R7C2
R7C3
R7C4
PL8
R8C1
R8C2
R8C3
R9C1
R9C2
R9C3
R2C10 R2C11 R2C12 R2C13 R2C14 R2C15 R2C16 R2C17
R2C18
R3C9
R3C10 R3C11 R3C12 R3C13 R3C14 R3C15 R13C16 R3C17
R3C18
R4C8
R4C9
R4C10 R4C11 R4C12 R4C13 R4C14 R4C15 R4C16 R4C17
R4C18
R5C7
R5C8
R5C9
R5C10 R5C11 R5C12 R5C13 R5C14 R5C15 R5C16 R5C17
R5C18
R6C6
R6C7
R6C8
R6C9
R6C10 R6C11 R6C12 R6C13 R6C14 R6C15 R6C16 R6C17
R6C18
R7C5
R7C6
R7C7
R7C8
R7C9
R7C10 R7C11 R7C12 R7C13 R7C14 R7C15 R7C16 R7C17
R7C18
R8C4
R8C5
R8C6
R8C7
R8C8
R8C9
R8C10 R8C11 R8C12 R8C13 R8C14 R8C15 R8C16 R8C17
R8C18
R9C4
R9C5
R9C6
R9C7
R9C8
R9C9
R9C10 R9C11 R9C12 R9C13 R9C14 R9C15 R9C16 R9C17
R9C18
PR9
R2C8
PR8
R2C7
PR7
R2C6
PR6
R2C5
PR5
R2C4
PR4
R2C3
PR3
R2C2
PR2
R2C1
PL9
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PT1
PR1
PL1
VI
vIQ
LMID
PL10
R10C1 R10C2 R10C3
R10C4 R10C5 R10C6
R10C7 R10C8 R10C9
R10C10 R10C11 R10C12 R10C13 R10C14 R10C15 R10C16 R10C17 R10C18
RMID
PL11
R11C1 R11C2 R11C3
R11C4 R11C5 R11C6 R11C7 R11C8 R11C9
R11C10 R11C11 R11C12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18
PR11
PL12
R12C1 R12C2 R12C3
R12C4 R12C5 R12C6 R12C7 R12C8 R12C9
R12C10 R12C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18
PR12
PL13
R13C1 R13C2 R13C3
R13C4 R13C5 R13C6 R13C7 R13C8 R13C9
R13C10 R13C11 R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18
PR13
PL14
R14C1 R14C2 R14C3
R14C4 R14C5 R14C6 R14C7 R14C8 R14C9
R14C10 R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18
PR14
PL15
R15C1 R15C2 R15C3
R15C4 R15C5 R15C6 R15C7 R15C8 R15C9
R15C10 R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18
PR15
PL16
R16C1 R16C2 R16C3
R16C4 R16C5 R16C6 R16C7 R16C8 R16C9
R16C10 R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18
PR16
PL17
R17C1 R17C2 R17C3
R17C4 R17C5 R17C6 R17C7 R17C8 R17C9
R17C10 R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18
PR17
PL18
R18C1 R18C2 R18C3
R18C4 R18C5 R18C6 R18C7 R18C8 R18C9
R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18
PR18
PR10
hIQ
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
BMID
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
5-4489(F)
Figure 1. OR3T55 Array
8
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
F5D
K7_0
K7_1
K7_2
K7_3
K6_0
K6_1
K6_2
K6_3
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The programmable logic cell (PLC) consists of a programmable function unit (PFU), a supplemental logic
and interconnect cell (SLIC), and routing resources. All
PLCs in the array are functionally identical with only
minor differences in routing connectivity for improved
routability. The PFU, which contains eight 4-input LUTs,
eight latches/FFs, and one FF for logic implementation,
is discussed in the next section, followed by discussions of the SLIC and PLC routing resources.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 50 external
inputs and 18 outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
The PFU uses 36 data input lines for the LUTs, eight
data input lines for the latches/FFs, five control inputs
(ASWE, CLK, CE, LSR, SEL), and a carry input (CIN)
for fast arithmetic functions and general-purpose data
input for the ninth FF. There are eight combinatorial data
outputs (one from each LUT), eight latched/registered
outputs (one from each latch/FF), a carry-out (COUT),
and a registered carry-out (REGCOUT) that comes from
the ninth FF. The carry-out signals are used principally
for fast arithmetic functions.
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The eight
sets of LUT inputs are labeled as K0 through K7 with
each of the four inputs to each LUT having a suffix of
_x, where x is a number from 0 to 3. There are four F5
inputs labeled A through D. These inputs are used for a
fifth LUT input for 5-input LUTs or as a selector for multiplexing two 4-input LUTs. The eight direct data inputs to
the latches/FFs are labeled as DIN[7:0]. Registered LUT
outputs are shown as Q[7:0], and combinatorial LUT
outputs are labeled as F[7:0].
The PFU implements combinatorial logic in the LUTs
and sequential logic in the latches/FFs. The LUTs are
static random access memory (SRAM) and can be used
for read/write or read-only memory.
Each latch/FF can accept data from its associated LUT.
Alternatively, the latches/FFs can accept direct data
from DIN[7:0], eliminating the LUT delay if no combinatorial function is needed. Additionally, the CIN input can
be used as a direct data source for the ninth FF. The
LUT outputs can bypass the latches/FFs, which reduces
the delay out of the PFU. It is possible to use the LUTs
and latches/FFs more or less independently, allowing,
for instance, a comparator function in the LUTs simultaneously with a shift register in the FFs.
Lattice Semiconductor
K5_0
K5_1
K5_2
K5_3
K4_0
K4_1
K4_2
K4_3
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
F5C
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
PROGRAMMABLE
FUNCTION UNIT
(PFU)
COUT
REGCOUT
CIN
F7
F6
F5
F4
F3
F2
F1
F0
F5B
K3_0
K3_1
K3_2
K3_3
K2_0
K2_1
K2_2
K2_3
K1_0
K1_1
K1_2
K1_3
K0_0
K0_1
K0_2
K0_3
F5A
LSR
CLK
CE
SEL ASWE
5-5752(F)
5-5752(F)
Figure 2. PFU Ports
The PFU can be configured to operate in four modes:
logic mode, half-logic mode, ripple mode, and memory
(RAM/ROM) mode. In addition, ripple mode has four
submodes and RAM mode can be used in either a
single- or dual-port memory fashion. These submodes
of operation are discussed in the following sections.
9
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
F7
F5D
0
K7_0
DIN7
K7
A
B
K7_1
K7_2
0
Q7
F6
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C
D
REG7
D0
D1
DSEL
CE
CK
S/R
K7_3
K6_0
K6_1
K6_2
K6
A
B
C
K6_3
D
F5MODE67
K5
A
B
C
D
K4
A
B
C
D
K5_0
K5_1
K5_2
K5_3
K4_0
K4_1
K4_2
K4_3
DIN6
0
1
0
REG6
D0
D1
DSEL
CE
CK
S/R
F5
DIN5
0
Q5
F4
DIN4
0
F5MODE45
0
REG5
D0
D1
DSEL
CE
CK
S/R
1
0
F5C
Q6
CLK
REG4
D0
D1
DSEL
CE
CK
S/R
Q4
0
SEL
0
CIN
COUT
0
CE
1
1
FF8
1
D
CE
CK
S/R
ASWE
REGCOUT
1
0
LSR
0
0
0
F3
F5B
0
K3_0
DIN3
K3
A
B
C
D
K3_1
K3_2
K3_3
K2_0
K2
A
B
C
K2_1
K2_2
K2_3
D
K1_0
K1_1
K1_2
K1_3
K1
A
B
C
D
K0_0
K0_1
K0_2
K0_3
K0
A
B
C
D
0
DIN2
0
1
0
REG2
D0
D1
DSEL
CE
CK
S/R
F5MODE23
REG1
D0
D1
DSEL
CE
CK
S/R
1
0
F2
Q2
Q1
F0
DIN0
F5MODE01
Q3
F1
DIN1
0
F5A
0
REG3
D0
D1
DSEL
CE
CK
S/R
0
REG0
D0
D1
DSEL
CE
CK
S/R
Q0
5-5743(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram
10
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Look-Up Table Operating Modes
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The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For example, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT
memory.
Table 3 lists the basic operating modes of the LUT. Figure 4—Figure 10 show block diagrams of the LUT operating
modes. The accompanying descriptions demonstrate each mode’s use for generating logic.
Table 3. Look-Up Table Operating Modes
Mode
Function
Logic
4- and 5-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to
ninth FF or as pass through to COUT.
Half Logic/ Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; CIN
Half Rip- and ninth FF for logic or ripple functions.
ple
Ripple
All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in
use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode
are adder/subtractor, counter, multiplier, and comparator.
Memory All LUTs and latches/FFs used to create a 32 x 4 synchronous dual-port RAM. Can be used as singleport or as ROM.
PFU Control Inputs
Each PFU has five routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that
affects all latches and FFs in the device. The five control inputs are CLK, LSR, CE, ASWE, and SEL, and their
functionality for each logic mode of the PFU (discussed subsequently) is shown in Table 4. The clock signal to the
PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be
configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a
function of the signal itself. ASWE stands for add/subtract/write enable, which are its functions, along with being an
optional clock enable, and SEL is used to dynamically select between direct PFU input and LUT output data as the
input to the latches/FFs.
All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from
GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. For logic and ripple
modes of the PFU, the LSR, CE, and ASWE (as a clock enable) inputs can be disabled individually for each nibble
(latch/FF[3:0], latch/FF[7:4]) and for the ninth FF.
Lattice Semiconductor
11
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Table 4. Control Input Functionality
Mode
LSR
CLK to all latches/ LSR to all latches/
FFs
FFs, enabled per nibble and for ninth FF
Half Logic/ CLK to all latches/ LSR to all latches/FF,
Half Ripple FFs
enabled per nibble
and for ninth FF
Ripple
CLK to all latches/ LSR to all latches/
FFs
FFs, enabled per nibble and for ninth FF
Memory CLK to RAM
Port enable 2
(RAM)
Memory Optional for sync. Not used
(ROM)
outputs
CE
ASWE
SEL
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Port enable 1
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Ripple logic control
input
Write enable
Select between LUT
input and direct input
for eight latches/FFs
Select between LUT
input and direct input
for eight latches/FFs
Select between LUT
input and direct input
for eight latches/FFs
Not used
Not used
Not used
Not used
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Logic
CLK
Ripple logic control
input
Logic Mode
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in flexible groups to implement user
logic functions. The latches/FFs may be used in conjunction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of
LUT operation in PFU logic mode: F4 mode, F5 mode,
and softwired LUT (SWL) mode. Combinations of these
submodes are possible in each PFU.
F4 mode, shown simplified in Figure 4, illustrates the
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured
at the LUTs associated latch/FF, or multiplexed with the
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU. Only adjacent LUT pairs (K0 and K1, K2
and K3, K4 and K5, K6 and K7) can be multiplexed, and
the output always goes to the even-numbered output of
the pair.
The F5 submode of the LUT operation, shown simplified in Figure 4, indicates the use of 5-input LUTs to
implement logic. 5-input LUTs are created from two
4-input LUTs and a multiplexer. The F5 LUT is the
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to the F4
LUTs be the same. The F5[A:D] input is then used as
the fifth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT. Any combination
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5
LUTs, and a combination of four F4 plus two F5 LUTs.
F5D
K7
F7
K7
F6
K6
K5
K6
F6
F5
F6
K5/K4
F4
K3/K2
F2
K1/K0
F0
K5
F4
K4
K7/K6
F4
K4
F5C
F5B
K3
F3
K3
F2
K2
F2
K2
K1
F1
F5 MODE
K1
F0
K0
K0
F0
F5A
F4 MODE
MULTIPLEXED F4 MODE
5-5970(F)
Figure 4. Simplified F4 and F5 Logic Modes
12
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
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Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic functions up to three LUT-levels deep. Figure 3 shows multiplexers between the KZ[3:0] inputs to the PFU and the
LUTs. These multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs.
In this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single PFU at
greatly enhanced speeds.
Figure 5 shows several softwired LUT topologies. In this figure, each circle represents either an F4 or F5 LUT. It is
important to note that an LUT output that is fed back for softwired use is still available to be registered or output
from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equation need only be generated once and PLC routing resources will not be required to use it in the larger equation.
F4
F4
F4
F4
F5
F5
F4
F4
F4
F4
F5
F5
FOUR 7-INPUT FUNCTIONS IN ONE PFU
F5
F5
TWO 9-INPUT FUNCTIONS IN ONE PFU
F4
F4
F5
F5
ONE 17-INPUT FUNCTION IN ONE PFU
ONE 21-INPUT FUNCTION IN ONE PFU
F4
3
5-5753(F)
F4
F4
F4
F4
F4
F5
F5
F4
F4
F4
F4
TWO OF FOUR 10-INPUT FUNCTIONS IN ONE PFU
ONE OF TWO 12-INPUT FUNCTIONS IN ONE PFU
5-5754(F)
KEY:
F4
4-INPUT LUT
F5
5-INPUT LUT
Figure 5. Softwired LUT Topology Examples
Lattice Semiconductor
13
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
with half-logic ripple connections shown as dashed
lines.
Half-Logic Mode
The result output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
two operands are input into KZ[1] and KZ[0] of each
LUT. The result bits, one per LUT, are F[7:0]/F[3:0] (see
Figure 6). The ripple output from LUT K7/K3 can be
routed on dedicated carry circuitry into any of four adjacent PLCs, and it can be placed on the PFU COUT/
FCOUT outputs. This allows the PLCs to be cascaded
in the ripple mode so that nibble-wide ripple functions
can be expanded easily to any length.
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Series 3 FPGAs are based upon a twin-quad architecture in the PFUs. The byte-wide nature (eight LUTs,
eight latches/FFs) may just as easily be viewed as two
nibbles (two sets of four LUTs, four latches/FFs). The
two nibbles of the PFU are organized so that any nibble-wide feature (excluding some softwired LUT topologies) can be swapped with any other nibble-wide
feature in another PFU. This provides for very flexible
use of logic and for extremely flexible routing. The halflogic mode of the PFU takes advantage of the twinquad architecture and allows half of a PFU, K[7:4] and
associated latches/FFs, to be used in logic mode while
the other half of the PFU, K[3:0] and associated latches/
FFs, is used in ripple mode. In half-logic mode, the
ninth FF may be used as a general-purpose FF or as a
register in the ripple mode carry chain.
Result outputs and the carry-out may optionally be registered within the PFU. The capability to register the ripple results, including the carry output, provides for
improved counter performance and simplified pipelining in arithmetic functions.
Ripple Mode
The PFU LUTs can be combined to do byte-wide ripple
functions with high-speed carry logic. Each LUT has a
dedicated carry-out net to route the carry to/from any
adjacent LUT. Using the internal carry circuits, fast
arithmetic, counter, and comparison functions can be
implemented in one PFU. Similarly, each PFU has
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT)
ports for fast-carry routing between adjacent PFUs.
The ripple mode is generally used in operations on two
data buses. A single PFU can support an 8-bit ripple
function. Data buses of 4 bits and less can use the
nibble-wide ripple chain that is available in half-logic
mode. This nibble-wide ripple chain is also useful for
longer ripple chains where the length modulo 8 is four
or less. For example, a 12-bit adder (12 modulo 8 = 4)
can be implemented in one PFU in ripple mode (8 bits)
and one PFU in half-logic mode (4 bits), freeing half of
a PFU for general logic mode functions.
Each LUT has two operands and a ripple (generally
carry) input, and provides a result and ripple (generally
carry) output. A single bit is rippled from the previous
LUT and is used as input into the current LUT. For LUT
K0, the ripple input is from the PFU CIN or FCIN port.
The CIN/FCIN data can come from either the fast-carry
routing (FCIN) or the PFU input (CIN), or it can be tied
to logic 1 or logic 0.
In the following discussions, the notations LUT K7/K3
and F[7:0]/F[3:0] are used to denote the LUT that provides the carry-out and the data outputs for full PFU
ripple operation (K7, F[7:0]) and half-logic ripple
operation (K3, F[3:0]), respectively. The ripple mode
diagram in Figure 6 shows full PFU ripple operation,
14
C
D Q
REGCOUT
FCOUT
COUT
C
F7
K7[1]
K7[0]
K7
D
K6[1]
K6[0]
K6
D
K5[1]
K5[0]
K5
D
K4[1]
K4[0]
K4
D
K3[1]
K3[0]
K3
D
K2[1]
K2[0]
K2
D
K1[1]
K1[0]
K1
D
K0[1]
K0[0]
K0
D
Q
Q7
F6
Q
Q6
F5
Q
Q5
F4
Q
Q4
Q
Q3
Q
Q2
F3
F2
F1
Q
Q1
F0
Q
Q0
CIN/FCIN
5-5755(F)
Figure 6. Ripple Mode
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
C
D
Q
The third LUT output creates the result bit for each LUT
output connected to F[7:0]/F[3:0]. If an adder/subtractor is needed, the control signal to select addition or
subtraction is input on ASWE, with a logic 0 indicating
subtraction and a logic 1 indicating addition. The result
bit is created in one-half of the LUT from a single bit
from each input bus KZ[1:0], along with the ripple input
bit.
The second submode is the counter submode (see
Figure 7). The present count, which may be initialized
via the PFU DIN inputs to the latches/FFs, is supplied
to input KZ[0], and then output F[7:0]/F[3:0] will either
be incremented by one for an up counter or decremented by one for a down counter. If an up/down
counter is needed, the control signal to select the direction (up or down) is input on ASWE with a logic 1 indicating an up counter and a logic 0 indicating a down
counter. Generally, the latches/FFs in the same PFU
are used to hold the present count value.
Lattice Semiconductor
REGCOUT
FCOUT
COUT
C
K7[0]
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
The ripple mode can be used in one of four submodes.
The first of these is adder-subtractor submode. In
this submode, each LUT generates three separate outputs. One of the three outputs selects whether the
carry-in is to be propagated to the carry-out of the current LUT or if the carry-out needs to be generated. If
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is
placed on the carry-out signal, which is connected to
the next LUT carry-in or the COUT/FCOUT signal, if it
is the last LUT (K7/K3). Both of these outputs can be
any equation created from KZ[1] and KZ[0], but in this
case, they have been set to the propagate and generate functions.
K7
D
K6
D
K5
D
K4
D
K3
D
K2
D
Q
K1
D
Q
K0
D
Q
K6[0]
Q
K5[0]
Q
K4[0]
Q
K3[0]
Q
K2[0]
K1[0]
K0[0]
Q
CIN/FCIN
F7
Q7
F6
Q6
F5
Q5
F4
Q4
F3
Q3
F2
Q2
F1
Q1
F0
Q0
5-5756(F)
Figure 7. Counter Submode
15
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
C
ASWE
D Q
COUT
C
K7[1]
0
1
0
REGCOUT
F7
D Q
+
Q7
SE
L
D E
IS C
C T
O D
N E
TI VI
N C
U E
ED S
In the third submode, multiplier submode, a single
PFU can affect an 8 x 1 bit (4 x 1 for half-ripple mode)
multiply and sum with a partial product (see Figure 8).
The multiplier bit is input at ASWE, and the multiplicand
bits are input at KZ[1], where K7[1] is the most significant bit (MSB). KZ[0] contains the partial product (or
other input to be summed) from a previous stage. If
ASWE is logical 1, the multiplicand is added to the partial product. If ASWE is logical 0, 0 is added to the partial product, which is the same as passing the partial
product. CIN/FCIN can bring the carry-in from the less
significant PFUs if the multiplicand is wider than 8 bits,
and COUT/FCOUT holds any carry-out from the multiplication, which may then be used as part of the product or routed to another PFU in multiplier mode for
multiplicand width expansion.
Ripple mode’s fourth submode features equality
comparators. The functions that are explicitly available
are A > B, A ≠ B, and A < B, where the value for A is
input on KZ[0], and the value for B is input on KZ[1]. A
value of 1 on the carry-out signals valid argument. For
example, a carry-out equal to 1 in AB submode indicates that the value on KZ[0] is greater than or equal to
the value on KZ[1]. Conversely, the functions A < B, A +
B, and A > B are available using the same functions but
with a 0 output expected. For example, A > B with a 0
output indicates A < B. Table 5 shows each function
and the output expected.
K7[0]
K7
K6[1]
0
1
0
F6
K6[0]
Q6
K6
K5[1]
0
1
0
F5
D Q
+
K5[0]
Q5
K5
K4[1]
0
1
0
F4
D Q
+
K4[0]
Q4
K4
K3[1]
0
1
0
F3
D Q
+
K3[0]
Q3
K3
K2[1]
0
1
0
F2
D Q
+
K2[0]
Q2
K2
K1[1]
0
1
0
F1
D Q
+
K1[0]
Q1
K1
K0[1]
0
K0[0]
D Q
+
1
0
F0
D Q
+
Q0
K0
5-5757(F)
Key: C = configuration data.
Figure 8. Multiplier Submode
If larger than 8 bits, the carry-out signal can be cascaded using fast-carry logic to the carry-in of any adjacent PFU. The use of this submode could be shown
using Figure 6, except that the CIN/FCIN input for the
least significant PFU is controlled via configuration.
Table 5. Ripple Mode Equality Comparator
Functions and Outputs
Equality
Function
ispLEVER
Submode
True, if
Carry-Out Is:
A>B
A>B
1
A
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