OR4E04

Data Sheet May, 2006 ORCA® Series 4 FPGAs Introduction Built on the Series 4 reconfigurable embedded system-on-a-chip (SoC) architecture, Lattice introduces its new family of generic Field-Programmable Gate Arrays (FPGAs). The high-performance and highly versatile architecture brings a new dimension to bringing network system designs to market in less time than ever before. This new device family offers many new features and architectural enhancements not available in any earlier FPGA generations. Bringing together highly flexible SRAM-based programmable logic, powerful system features, a rich hierarchy of routing and interconnect resources, and meeting multiple interface standards, the Series 4 FPGA accommodates the most complex and high-performance intellectual property (IP) network designs. ■ ■ Traditional I/O selections: — LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V) I/Os. — Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. — Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. — Two slew rates supported (fast and slew-limited). — Fast-capture input latch and input flip-flop (FF)/latch for reduced input setup time and zero hold time. — Fast open-drain drive capability. — Capability to register 3-state enable signal. — Off-chip clock drive capability. — Two-input function generator in output path. New programmable high-speed I/O: — Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I and II), HSTL (Class I, III, and IV), ZBT, and DDR. — Double-ended: LDVS, bused-LVDS, and LVPECL. Programmable (on/off) internal parallel termination (100 Ω) also supported for these I/Os. Programmable Features ■ High-performance platform design: — 0.16 μm 7-level metal technology. — Internal performance of >250 MHz. — I/O performance of >420 MHz. — Meets multiple I/O interface standards. — 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. Table 1. ORCA Series 4—Available FPGA Logic Device OR4E02 OR4E04 OR4E06 Rows 26 36 46 Columns 24 36 44 PFUs 624 1,296 2,024 User I/O 405 466 466 LUTs 4,992 10,368 16,192 EBR Blocks 8 12 16 EBR Bits (K) 74 111 148 Usable* Gates (K) 201—397 333—643 471—899 * The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following: minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs. Note: Devices are not pinout compatible with ORCA Series 2/3. © 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 or4e_05 ORCA Series 4 FPGAs Data Sheet May, 2006 Table of Contents Contents Page Contents Page Introduction ................................................................ 1 Programmable Features ............................................ 1 System Features ....................................................... 4 Product Description ................................................... 5 Architecture Overview ..........................................5 Programmable Logic Cells ........................................ 6 Programmable Function Unit ...............................7 Look-Up Table Operating Modes .......................10 Supplemental Logic and Interconnect Cell ........20 PLC Latches/Flip-Flops ......................................24 Embedded Block RAM (EBR) .................................. 26 EBR Features ....................................................26 Routing Resources .................................................. 31 Clock Distribution Network ...................................... 31 Global Primary Clock Nets .................................31 Secondary Clock and Control Nets ....................31 Secondary Edge Clock Nets and Fast Edge Clock Nets ...................................31 Cycle Stealing ....................................................32 Programmable Input/Output Cells (PIC) .................. 32 Programmable I/O ..............................................32 Inputs .................................................................35 Outputs ..............................................................36 I/O Banks and Groups ....................................... 37 Special Function Blocks .......................................... 39 Single Function Blocks .......................................47 Microprocessor Interface (MPI) ............................... 49 Embedded System Bus (ESB) ...........................49 Phase-Locked Loops (PLLs) ................................... 53 FPGA States of Operation ....................................... 56 Initialization ........................................................56 Power Supply Sequencing .................................57 Configuration ......................................................57 Start-Up ..............................................................57 Reconfiguration ..................................................61 Partial Reconfiguration .......................................61 Other Configuration Options ..............................61 Configuration Data Format .................................61 Using ispLEVER to Generate Configuration RAM Data ...............................61 Configuration Data Frame ..................................62 Bit Stream Error Checking .................................64 FPGA Configuration Modes ..................................... 64 Master Parallel Mode .........................................65 Master Serial Mode ............................................66 Asynchronous Peripheral Mode .........................67 Microprocessor Interface Mode ..........................68 Slave Serial Mode ..............................................72 Slave Parallel Mode ...........................................72 Daisy-Chaining ...................................................73 Daisy-Chaining with Boundary-Scan ..................74 Absolute Maximum Ratings ..................................... 75 Recommended Operating Conditions ................75 Electrical Characteristics ......................................... 76 Power Estimation ..................................................... 77 Estimating Power Dissipation .................................. 77 Timing Characteristics ............................................. 78 Configuration Timing ..........................................92 Readback Timing ............................................ 100 Pin Information ...................................................... 101 Pin Descriptions .............................................. 101 Package Compatibility ..................................... 105 352-Pin PBGA Pinout ...................................... 107 416-Pin BGAM Pinout ..................................... 116 680-Pin PBGAM Pinout ................................... 126 Package Thermal Characteristics Summary ......... 142 ΘJA ................................................................. 142 ψJC ................................................................. 142 ΘJC ................................................................. 143 ΘJB ................................................................. 143 Package Thermal Characteristics .......................... 144 Package Coplanarity ............................................. 144 Heat Sink Vendors for BGA Packages .................. 144 Package Parasitics ................................................ 145 Package Outline Diagrams .................................... 146 Terms and Definitions ..................................... 146 352-Pin PBGA ................................................. 147 416-Pin PBGAM .............................................. 148 680-Pin PBGAM .............................................. 149 Ordering Information .............................................. 150 2 Lattice Semiconductor   Data Sheet May, 2006 ORCA Series 4 FPGAs ■ Programmable Features (continued) ■ New capability to (de)multiplex I/O signals: — New double data rate on both input and output at rates up to 350 MHz (700 MHz effective rate). — New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O). Enhanced twin-quad programmable function unit (PFU): — Eight 16-bit look-up tables (LUTs) per PFU. — Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. — New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. — New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 to 1 MUX, new 8 to 1 MUX, and ripple mode arithmetic functions in the same PFU. — 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. — Soft-wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. — Flexible fast access to PFU inputs from routing. — Fast-carry logic and routing to all four adjacent PFUs for nibble-, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out. Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. SLIC provides eight 3-statable buffers, up to 10-bit decoder, and PAL™-like and-or-invert (AOI) in each programmable logic cell. ■ Improved built-in clock management with programmable phase-locked loops (PPLLs) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of the input frequency up to 64x, and division of the input frequency down to 1/64x possible. New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as: — 1-512 x 18 (quad-port, two read/two write) with optional built in arbitration. — 1-256 x 36 (dual-port, one read/one write). — 1-1K x 9 (dual-port, one read/one write). — 2-512 x 9 (dual-port, one read/one write for each). — 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). — Supports joining of RAM blocks. — Two 16 x 8-bit content addressable memory (CAM) support. — FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9. — Constant multiply (8 x 16 or 16 x 8). — Dual-variable multiply (8 x 8). Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device. Built-in testability: — Full boundary scan (IEEE ® 1149.1 and Draft 1149.2 joint test access group (JTAG)). — Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7. — TS_ALL testability function to 3-state all I/O pins. — New temperature sensing diode. New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock-to-out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers. ■ ■ ■ ■ ■ ■ ■ Lattice Semiconductor 3           ORCA Series 4 FPGAs Data Sheet May, 2006 ■ System Features ■ ■ PCI local bus compliant. Improved PowerPC ® /PowerQUICC MPC860 and PowerPC II MPC8260 high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors with user-configurable address space provided. New embedded AMBA™ specification 2.0 AHB system bus (ARM ™ processor) facilitates communication among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard cell blocks. New network PLLs meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-3/STM-1 applications. Variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. Internal, 3-state, bidirectional buses with simple control provided by the SLIC. New clock routing structures for global and local clocking significantly increases speed and reduces skew ( B are available using the same functions but with a 0 output expected. For example, A > B with a 0 output indicates A ≤ B. Table 4 shows each function and the output expected. If larger than 8 bits, the carry-out signal can be cascaded using fast-carry logic to the carry-in of any adjacent PFU. The use of this submode could be shown using Figure 9, except that the CIN/FCIN input for the least significant PFU is controlled via configuration. Table 4. Ripple Mode Equality Comparator Functions and Outputs Equality Function A≥B A≤B A≠B AB A=B ispLEVER Submode A≥B A≤B A≠B A≥B A≤B A≠B True, if Carry-Out Is: 1 1 1 0 0 0 C DQ REGCOUT F5[A:C] K7[1] 0 K7[0] K6[1] 0 K6[0] K5[1] 0 K5[0] K4[1] 0 K4[0] K3[1] 0 K3[0] K2[1] 0 K2[0] K1[1] 0 K1[0] K0[1] 0 K0[0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 C F7 + K7 F6 + K6 F5 + K5 F4 + K4 F3 + K3 F2 + K2 F1 + K1 F0 + K0 D Q Q0 D Q Q1 D Q Q2 D Q Q3 D Q Q4 D Q Q5 D Q Q6 D Q Q7 COUT 5-5757(F) Key: C = configuration data. Note: F5[A:C] shorted together Figure 11. Multiplier Submode Lattice Semiconductor 17 ORCA Series 4 FPGAs Data Sheet May, 2006 Programmable Logic Cells (continued) Memory Mode The Series 4 PFU can be used to implement a 32x4 (128-bit) synchronous, dual-port RAM). A block diagram of a PFU in memory mode is shown in Figure 12. This RAM can also be configured to work as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be used as a ROM. F5[A:D] KZ[3:0] CIN(WA1) DQ 4 5 READ ADDRESS[4:0] WRITE ADDRESS[4:0] DIN7(WA3) DQ F6 F4 F2 F0 DIN5(WA2) DQ DQ DIN3(WA1) DQ DQ Q6 DIN1(WA0) DQ READ DATA[3:0] 4 Q4 DQ DIN6(WD3) DQ 4 WRITE DATA[3:0] DQ DIN4(WD2) DQ Q2 Q0 DIN2(WD1) DQ DIN0(WD0) DQ CE0, LSR0 (SEE NOTE 2.) CE1 DQ S/E WRITE ENABLE RAM CLOCK CLK[0:1] 5-5969(F)a 1. CLK[0:1] are commonly connected in memory mode. 2. CE1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled). CE0 = write port enable 0; CE0 = 0, wren = 0; CE0 = 1, wren = CE1. LSR0 = write port enable 1; LSR0 = 0, wren = CE0; LSR0 = 1, wren = CE1. Figure 12. Memory Mode 18 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Wider memories can be created by operating two or more memory mode PFUs in parallel, all with the same address and control signals, but each with a different nibble of data. To increase memory word depth above 32, two or more PLCs can be used. Figure 12 shows a 128x8 dual-port RAM that is implemented in eight PLCs. This figure demonstrates data path width expansion by placing two memories in parallel to achieve an 8-bit data path. Depth expansion is applied to achieve 128 words deep using the 32-word deep PFU memories. In addition to the PFU in each PLC, the SLIC (described in the next section) in each PLC is used for read address decodes and 3-state drivers. The 128x8 RAM shown could be made to operate as a single-port RAM by tying (bit-for-bit) the read and write addresses. To achieve depth expansion, one or two of the write address bits (generally the MSBs) are routed to the write port enables as in Figure 12. For 2 bits, the bits select which 32-word bank of RAM of the four available from a decode of two WPE inputs is to be written. Similarly, 2 bits of the read address are decoded in the SLIC and are used to control the 3-state buffers through which the read data passes. The write data bus is common, with separate nibbles for width expansion, across all PLCs, and the read data bus is common (again, with separate nibbles) to all PLCs at the output of the 3-state buffers. Figure 13 also shows the capability to provide a read enable for RAMs/ROMs using the SLIC cell. The read enable will 3-state the read data bus when inactive, allowing the write data and read data buses to be tied together if desired. Programmable Logic Cells (continued) The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in Figure 12. The read address is input at the KZ[3:0] and F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is the MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable controlling ports are input on CE0, CE1, and LSR0. CE1 is the activehigh write enable (CE1 = 1, RAM is write enabled). The first write port is enabled by CE0. The second write port is enabled with LSR0. The PFU CLK (CLK0) signal is used to synchronously write the data. The polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if they are not to be used. Data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the RAM until the next clock edge one-half cycle later. The read port is actually asynchronous, providing the user with read data very quickly after setting the read address, but timing is also provided so that the read port may be treated as fully synchronous for write then read applications. If the read and write address lines are tied together (maintaining MSB to MSB, etc.), then the dual-port RAM operates as a synchronous single-port RAM. If the write enable is disabled, and an initial memory contents is provided at configuration time, the memory acts as a ROM (the write data and write address ports and write port enables are not used). Lattice Semiconductor 19 ORCA Series 4 FPGAs Data Sheet May, 2006 Programmable Logic Cells (continued) WD[7:0] 8 4 PLC 4 PLC 4 PLC 4 PLC WD[7:4] 5 WA WPE 1 WPE 2 WE RD[7:4] RA 5 5 WD[3:0] WA WPE 1 WPE 2 WE RD[3:0] RA 5 5 WD[7:4] WA WPE 1 WPE 2 WE RD[7:4] RA 5 5 WD[3:0] WA WPE 1 WPE 2 WE RD[3:0] RA 5 RE 4 RD[7:0] WE WA[6:0] RA[6:0] CLK RE 7 7 8 4 RE 4 RE 4 RE 5-5749(F) Figure 13. Memory Mode Expansion Example—128x8 RAM Supplemental Logic and Interconnect Cell Each PLC contains a SLIC embedded within the PLC routing, outside of the PFU. As its name indicates, the SLIC performs both logic and interconnect (routing) functions. Its main features are 3-statable, bidirectional buffers, and a PAL-like decoder capability. Figure 14 shows a diagram of a SLIC with all of its features shown. All modes of the SLIC are not available at one time. The ten SLIC inputs can be sourced directly from the PFU or from the general routing fabric. SI[0:9] inputs can come from the horizontal or vertical routing and I[0:9} comes from the PFU outputs O[9:0]. These inputs can also be tied to a logical 1 or 0 constant. The inputs are twin-quad in nature and are segregated into two groups of four nibbles and a third group of two inputs for control. Each input nibble groups also have 3-state capability, however the third pair does not. There is one 3-state control (TRI) for each SLIC, with the capability to invert or disable the 3-state control for each group of four BIDIs. Separate 3-state control for each nibble-wide group is achievable by using the SLICs decoder (DEC) output, driven by the group of two BIDIs, to control the 3-state of one BIDI nibble 20 while using the TRI signal to control the 3-state of the other BIDI nibble. Figure 15 shows the SLIC in buffer mode with available 3-state control from the TRI and DEC signals. If the entire SLIC is acting in a buffer capacity, the DEC output may be used to generate a constant logic 1 (VHI) or logic 0 (VLO) signal for general use. The SLIC may also be used to generate PAL-like ANDOR with optional INVERT (AOI) functions or a decoder of up to 10 bits. Each group of buffers can feed into an AND gate (4-input AND for the nibble groups and 2-input AND for the other two buffers). These AND gates then feed into a 3-input gate that can be configured as either an AND gate or an OR gate. The output of the 3-input gate is invertible and is output at the DEC output of the SLIC. Figure 19 shows the SLIC in full decoder mode. The functionality of the SLIC is parsed by the two nibble-wide groups and the 2-bit buffer group. Each of these groups may operate independently as BIDI buffers (with or without 3-state capability for the nibblewide groups) or as a PAL/decoder. Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Logic Cells (continued) As discussed in the memory mode section, if the SLIC is placed into one of the modes where it contains both buffers and a decode or AOI function (e.g., BUF_BUF_DEC mode), the DEC output can be gated with the 3-state input signal. This allows up to a 6-input decode (e.g., BUF_DEC_DEC mode) plus the 3-state input to control the enable/disable of up to four buffers per SLIC Figure 15—Figure 19 show several configurations of the SLIC, while Table 5 shows all of the possible modes. Table 5. SLIC Modes Mode No. 1 2 3 4 5 6 7 8 Mode BUFFER BUF_BUF_DEC BUF_DEC_BUF BUF_DEC_DEC DEC_BUF_BUF DEC_BUF_DEC DEC_DEC_BUF DECODER BUF [3:0] Buffer Buffer Buffer Buffer Decoder Decoder Decoder Decoder BUF [7:4] Buffer Buffer Decoder Decoder Buffer Buffer Decoder Decoder BUF [9:8] Buffer Decoder Buffer Decoder Buffer Decoder Buffer Decoder SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SOUT08 SOUT09 SIN7 I7 LOGIC 1 OR 0 SIN6 I6 LOGIC 1 OR 0 SIN5 I5 LOGIC 1 OR 0 SIN4 I4 LOGIC 1 OR 0 TRI 0/1 DEC 0/1 0/1 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0 0/1 SOUT07 SOUT06 SOUT05 DEC SOUT04 SOUT03 SOUT02 SOUT01 SOUT00 5-5744(F).a. Figure 14. SLIC All Modes Diagram Lattice Semiconductor 21 ORCA Series 4 FPGAs Data Sheet May, 2006 Programmable Logic Cells (continued) SIN9 SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SIN7 SIN7 I7 LOGIC 1 OR 0 SIN6 I6 LOGIC 1 OR 0 SIN5 I5 LOGIC 1 OR 0 SIN4 I4 LOGIC 1 OR 0 1 TRI 0/1 1 0 THIS CAN BE USED TO GENERATE A VHI OR VLO 0/1 SIN3 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0 5-5745(F).a I9 SOUT09 LOGIC 1 OR 0 SIN8 I8 SOUT08 LOGIC 1 OR 0 I7 SOUT07 LOGIC 1 OR 0 SIN6 I6 SOUT06 LOGIC 1 OR 0 SIN5 I5 SOUT05 LOGIC 1 OR 0 SIN4 I4 SOUT04 LOGIC 1 OR 0 SOUT07 SOUT06 SOUT05 SOUT04 TRI 1 DEC 1 DEC 1 I3 SOUT03 SOUT03 LOGIC 1 OR 0 SIN2 I2 SOUT02 SOUT02 LOGIC 1 OR 0 SIN1 I1 SOUT01 SOUT01 LOGIC 1 OR 0 SIN0 I0 SOUT00 SOUT00 LOGIC 1 OR 0 5-5746(F).a Figure 16. Buffer-Buffer-Decoder Mode Figure 15. Buffer Mode 22 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Logic Cells (continued) SIN9 SIN9 I9 LOGIC 1 OR 0 SIN8 I8 LOGIC 1 OR 0 SIN7 SOUT08 SOUT09 LOGIC 1 OR 0 SIN8 LOGIC 1 OR 0 SIN7 LOGIC 1 OR 0 SIN6 LOGIC 1 OR 0 SIN6 LOGIC 1 OR 0 SIN5 LOGIC 1 OR 0 SIN5 LOGIC 1 OR 0 SIN4 LOGIC 1 OR 0 SIN4 LOGIC 1 OR 0 DEC TRI LOGIC 1 OR 0 1 TRI DEC 1 SIN3 I3 SOUT03 IF LOW THEN 3 STATE BUFFERS ARE HIGH Z 1 LOGIC 1 OR 0 SIN2 1 SIN3 I3 LOGIC 1 OR 0 SIN2 I2 LOGIC 1 OR 0 SIN1 I1 LOGIC 1 OR 0 SIN0 I0 LOGIC 1 OR 0 5-5747(F).a I2 LOGIC 1 OR 0 SOUT02 SOUT03 SIN1 I1 LOGIC 1 OR 0 SOUT01 SOUT02 SIN0 I0 LOGIC 1 OR 0 5-5750(F) SOUT00 SOUT01 Figure 18. Buffer-Decoder-Decoder Mode SOUT00 Figure 17. Buffer-Decoder-Buffer Mode Lattice Semiconductor 23 ORCA Series 4 FPGAs Data Sheet May, 2006 PLC Latches/Flip-Flops The eight general-purpose latches/FFs in the PFU can be used in a variety of configurations. In some cases, the configuration options apply to all eight latches/FFs in the PFU and some apply to the latches/FFs on a nibble-wide basis where the ninth FF is considered independently. For other options, each latch/FF is independently programmable. In addition, the ninth FF can be used for a variety of functions. Table 6 summarizes these latch/FF options. The latches/FFs can be configured as either positive- or negative-level sensitive latches, or positive or negative edge-triggered FFs (the ninth register can only be a FF). All latches/FFs in a given PFU share the same clock, and the clock to these latches/FFs can be inverted. The input into each latch/FF is from either the corresponding LUT output (F[7:0]) or the direct data input (DIN[7:0]). The latch/FF input can also be tied to logic 1 or to logic 0, which is the default. Table 6. Configuration RAM Controlled Latch/ Flip-Flop Operation Function Options Programmable Logic Cells (continued) SIN9 LOGIC 1 OR 0 SIN8 LOGIC 1 OR 0 SIN7 LOGIC 1 OR 0 SIN6 LOGIC 1 OR 0 SIN5 LOGIC 1 OR 0 SIN4 LOGIC 1 OR 0 DEC SIN3 LOGIC 1 OR 0 SIN2 LOGIC 1 OR 0 SIN1 LOGIC 1 OR 0 SIN0 LOGIC 1 OR 0 5-5748(F) Common to All Latches/FFs in PFU LSR Operation Asynchronous or synchronous. Clock Polarity Noninverted or inverted. Front-end Select* Direct (DIN[7:0]) or from LUT (F[7:0]). LSR Priority Either LSR or CE has priority. Latch/FF Mode Latch or FF. Enable GSRN GSRN enabled or has no effect on PFU latches/FFs. Set Individually in Each Latch/FF in PFU Set/Reset Mode Set or reset. By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8]) Clock Enable CE or none. LSR Control LSR or none. * Not available for FF[8]. Figure 19. Decoder Mode Each PFU has two independent programmable clocks, clock enable CE[1:0], local set/reset LSR[1:0], and front end data selects SEL[1:0]. When CE is disabled, each latch/FF retains its previous value when clocked. The clock enable, LSR, and SEL inputs can be inverted to be active-low. 24 24 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs latch/FF is from the output of its associated LUT, F[7:0], or direct from DIN[7:0], bypassing the LUT. In the front-end data select mode, both signals are available to the latches/FFs. If either or both of these inputs is unused or is unavailable, the latch/FF data input can be tied to a logic 0 or logic 1 instead (the default is logic 0). The latches/FFs can be configured in three basic modes: ■ Programmable Logic Cells (continued) The set/reset operation of the latch/FF is controlled by two parameters: reset mode and set/reset value. When the GSRN and local set/reset (LSR) signals are not asserted, the latch/FF operates normally. The reset mode is used to select a synchronous or asynchronous LSR operation. If synchronous, LSR has the option to be enabled only if clock enable (CE) is active or for LSR to have priority over the clock enable input, thereby setting/resetting the FF independent of the state of the clock enable. The clock enable is supported on FFs, not latches. It is implemented by using a 2-input multiplexer on the FF input, with one input being the previous state of the FF and the other input being the new data applied to the FF. The select of this 2-input multiplexer is clock enable (CE), which selects either the new data or the previous state. When the clock enable is inactive, the FF output does not change when the clock edge arrives. The GSRN signal is only asynchronous, and it sets/ resets all latches/FFs in the FPGA based upon the set/ reset configuration bit for each latch/FF. The set/reset value determines whether GSRN and LSR are set or reset inputs. The set/reset value is independent for each latch/FF. An option is available to disable the GSRN function per PFU after initial device configuration. The latch/FF can be configured to have a data frontend select. Two data inputs are possible in the front-end select mode, with the SEL signal used to select which data input is used. The data input into each Local synchronous set/reset: the input into the PFU’s LSR port is used to synchronously set or reset each latch/FF. Local asynchronous set/reset: the input into LSR asynchronously sets or resets each latch/FF. Latch/FF with front-end select, LSR either synchronous or asynchronous: the data select signal selects the input into the latches/FFs between the LUT output and direct data in. ■ ■ For all three modes, each latch/FF can be independently programmed as either set or reset. Figure 20 provides the logic functionality of the front-end select, global set/reset, and local set/reset operations. The ninth PFU FF, which is generally associated with registering the carry-out signal in ripple mode functions, can be used as a general-purpose FF. It is only an FF and is not capable of being configured as a latch. Because the ninth FF is not associated with an LUT, there is no front-end data select. The data input to the ninth FF is limited to the CIN input, logic 1, logic 0, or the carry-out in ripple and half-logic modes. CE F DIN LOGIC 1 LOGIC 0 LSR S_RESET CLK SET RESET GSRN CD CD GSRN LSR CE D S_SET Q F DIN LOGIC 1 LOGIC 0 CE CE D Q F DIN LOGIC 1 LOGIC 0 SEL D DIN CE CE Q CLK SET RESET GSRN LSR CLK SET RESET CD 5-9737(F).a Key: C = configuration data. Figure 20. Latch/FF Set/Reset Configurations Lattice Semiconductor 25 ORCA Series 4 FPGAs Data Sheet May, 2006 ■ ■ ■ Embedded Block RAM (EBR) The ORCA Series 4 devices compliment the distributed PFU RAM with large blocks of memory macrocells. The memory is available in 512 words by 18 bits/word blocks with 2 read and 2 write ports with two byte lane enables which operate with quad-port functionality. Additional logic has been incorporated for FIFO, multiplier, and CAM implementations. The RAM blocks are organized along the PLC rows and are added in proportion to the FPGA array sizes as shown in Table 7. The contents of the RAM blocks may be optionally initialized during FPGA configuration. Table 7. ORCA Series 4— Available Embedded Block RAM Device OR4E02 OR4E04 OR4E06 Number of Blocks 8 12 16 Number of EBR Bits 74K 111K 147K One 256 x 36 RAM. One 1K x 9 RAM. Two independent 512 x 9 RAMs built in one EBR with separate read clocks, write clocks and enables. Two independent RAMS with arbitrary number of words whose sum is 512 words or less by 18 bits/ word or less. ■ The joining of RAM blocks is supported to create wider deeper memories. The adjacent routing interface provided by the CIBs allow the cascading of blocks together with minimal penalties due to routing delays. It is also possible to connect any or all of the EBR RAM blocks together through the embedded system bus, which is discussed in a later section of this data sheet. Arbitration logic is optionally programmed by the user to signal occurrences of data collisions as well as to block both ports from writing at the same time. The arbitration logic prioritizes PORT1. When utilizing the arbiter, the signal BUSY indicates data is being written to PORT1. This BUSY output signals PORT1 activity by driving a high output. If the arbiter is turned off both ports could be written at the same time and the data would be corrupt. In this scenario the BUSY signal will indicate a possible error. There is also a user option which dedicates PORT 1 to communications to the system bus. In this mode the user logic only has access to PORT0 and arbitration logic is enabled. The system bus utilizes the priority given to it by the arbiter therefore the system bus will always be able to write to the EBR. Each highly flexible 512x18 (quad-port, two read/two write) RAM block can be programmed by the user to meet their particular function. Each of the EBR configurations use the physical signals as shown in Table 8. Quad-port addressing permits simultaneous read and write operations on all four ports. The EBR ports are written synchronously on the positive-edge of CKW. Synchronous read operations uses the positive-edge of CKR. Options are available to use synchronous read address registers and read output registers, or to bypass these registers and have the RAM read operate asynchronously. Detailed information about the EBR blocks is found in various application notes. ispLEVER provides SCUBA as a RAM generation tool for EBR RAMs. Many of the EBR sub-modes are supported and the initialization values can also be defined. EBR Features Quad Port RAM Modes (Two Read/Two Write) ■ One 512 x 18 RAM with optional built-in write arbitration. One 1024 x 18 RAM built on two blocks with built-in decode logic for simplified implementation. ■ Dual Port RAM Modes (One Read/One Write) 26 26 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs An 8 x 8 MULTIPLY mode is configurable to either a pipelined or combinatorial multiplier function of two 8bit numbers. Two 8-bit operands are multiplied to yield a 16-bit product. The input can be registered in pipeline mode. CAM Mode The CAM block is a binary content address memory that provides fast address searches by receiving data input and returning addresses that contain the data. Implemented in each EBR are two 16-word x 8-bit CAM function blocks. The CAM has three modes, single match, multiple match and clear, which are all achieved in one clock cycle. In single match mode, a 8-bit data input is internally decoded and reports a match when data is present in a particular RAM address. Its result is reported by a corresponding single address bit. In multiple match the same occurs with the exception of multiple address lines report the match. Clear mode is used to clear the CAM contents by erasing all locations one cycle per location. The EBR blocks in CAM mode may be cascaded to produce larger CAMs. Embedded Block RAM (EBR) (continued) FIFO Modes FIFOs can be configured to 256, 512, or 1K depths and 36, 18, or 9 widths respectively but also can be expanded using multiple blocks. FIFO works synchronously with the same read and write clock where the read port can be registered on the output or not registered. It can also be optionally configured asynchronously with different read and write clocks and the same read port register options. Integrated flags allow the user the ability to fully utilize the EBR for FIFO, without the need to dedicate an address for providing distinct full/empty status. There are four programmable flags provided for each FIFO: Empty, partially empty, full, and partially full FIFO status. The partially empty and partially full flags are programmable with the flexibility to program the flags to any value from the full or empty threshold. The programmed values can be set to a fixed value through the bitstream or a dynamic value can be controlled by input pins of the EBR FIFO. When the FIFO is in asynchronous mode, the FIFO flags use grey code counters to ensure proper glitch-free operation. Multiplier Modes The ORCA Series 4 EBR supports two variations of multiplier functions. Constant coefficient MULTIPLY [KCM] mode will produce a 24-bit output of a fixed 8-bit constant multiply of a 16-bit number or a fixed 16-bit constant multiply of an 8-bit number. This KCM multiplies a constant times a 16- or 8-bit number and produces a product as a 24-bit result. The coefficient and multiplication tables are stored in memory. The input can be configured to be registered for pipelining. Both write ports are available during MULTIPLY mode so that the user logic can update and modify the coefficients for dynamic coefficient updates. The SCUBA program in ispLEVER should be used to create the KCM multipliers, including the input of initial coefficients. Lattice Semiconductor 27 ORCA Series 4 FPGAs Data Sheet May, 2006 Embedded Block RAM (EBR) (continued) Table 8. RAM Signals Port Signals I/O Function PORT 0 AR0[#:0] AW0[#:0] BW0 I I I CKR0 CKW0 CSR0 CSW0 D [#:0] Q [#:0] PORT 1 AR1[#:0] AW1[#:0] BW1 I I I I I O Address to be read (variable width depending on RAM size). Address to be written (variable width depending on RAM size). Byte-write enable. Byte = 8-bits + parity bit. = bits[17, 15:9] = bits[16, 7:0] Positive-edge asynchronous read clock. Positive-edge synchronous write clock. Enables read to output. Active high. Enables write to output. Active high. Input data to be written to RAM (variable width depending on RAM size). Output data of memory contents at referenced address (variable width depending on RAM size). Address to be read (variable width depending on RAM size). Address to be written (variable width depending on RAM size). Byte-write enable. Byte = 8-bits + parity bit. = bits[17, 15:9] = bits[16, 7:0] Positive-edge asynchronous read clock. Positive-edge synchronous write clock. Enables read to output. Active high. Enables write to output. Active high. Input data to be written to RAM (variable width depending on RAM size). Output data of memory contents at referenced address (variable width depending on RAM size). PORT1 writing. Active high. Data output registers cleared. Memory contents unaffected. Active-low. I I I CKR1 CKW1 CSR1 CSW1 D [#:0] Q [#:0] Control BUSY RESET I I I I I O O I 28 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Embedded Block RAM (continued) CKWPL CKW CSWSU CSW AWSU AW DSU D BWSU BW d BWH c DH AWH CSWH CKWPH AR a AQH b c AQ b c CKWQ d 0308(F) Q a Figure 21. EBR Read and Write Cycles with Write Through and Nonregistered Read Port Table 9. FIFO Signals Port Signals AR0[5:0] AR1[9:0] FF PFF PEF EF D0[17:0] D1[17:0] CKW[0:1] CKR[0:1] CSW[1:0] CSR[1:0] RESET Q0[17:0] Q1[17:0] I/O I I O O O O I I I I I I I O O Function Programs FIFO flags. Used for partially empty flag size. Programs FIFO flags. Used for partially full flag size. Full Flag. Partially Full Flag. Partially Empty Flag. Empty Flag. Data inputs for all configurations. Data inputs for 256x36 configurations only. Positive-edge write port clock. Port 1 only used for 256x36 configurations. Positive-edge read port clock. Port 1 only used for 256x36 configurations. Active-high write enable. Port 1 only used for 256x36 configurations. Active-high read enable. Port 1 only used for 256x36 configurations. Active-low Resets FIFO pointers. Data outputs for all configurations. Data outputs for 256x36 configurations. Lattice Semiconductor 29 ORCA Series 4 FPGAs Data Sheet May, 2006 Embedded Block RAM (continued) Table 10. Constant Multiplier Signals Port Signals AR0[15:0] AW(1:0)[8:0] D(1:0)[17:0] CKW[0:1] CKR[0:1] CSW[1:0] CSR[1:0] Q[23:0] I/O I I I I I I I O Function Data input–operand. Address bits. Data inputs to load memory or change coefficient. Positive-edge write port clock. Positive-edge read port clock. Used for synchronous multiply mode. Active-high write enable. Active-high read enable. Data outputs–product result. Table 11. 8x8 Multiplier Signals Port Signals AR0[7:0] AR1[7:0] CKR[0:1] CSR[1:0] Q[15:0] Table 12. CAM Signals Port Signals AR(1:0)[7:0] AW(1:0)[8:0] D(1:0)[17] D(1:0)[16] D(1:0)[3:0] CSW[1:0] CSR[1:0] Q(1:0)15:0] I/O I I I I I I I O Function Data Match. Data Write. Clear data active high. Single match active high. CAM address for data write. Active-high write enable. Enable for CAM data write. Active-high read enable. Enable for CAM data match. Decoded Data outputs. “1” corresponds to a data match at that address location. I/O I I I I O Function Data input-Multiplicand. Data input-Multiplier. Positive-edge read port clock. Used for synchronous multiply mode. Active-high read enable. Data outputs-product. 30 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Global Primary Clock Nets The Series 4 FPGAs provide eight fully distributed global primary clock net routing resources. The scheme dedicates four of the eight resources to provide fast primary nets and four are available for general primary nets. The fast primary nets are targeted toward lowskew and small injection times while the general primary nets are also targeted toward low-skew but have more source connection flexibility. Fast access to the global primary nets can be sourced from two pairs of pads located in the center of each side of the device, from the programmable PLLs and dedicated network PLLs located in the corners, or from general routing at the center of the device or at the middle of any side of the device. The I/O pads are semi-dedicated in pairs for use of differential I/O clocking or single-ended I/O clock sources. However if these pads are not needed to source the clock network they can be utilized for general I/O. The clock routing scheme is patterned using vertical and horizontal routes which provide connectivity to all PLC columns. Routing Resources The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. x1 routes cross width of one PLC and provide local connectivity to PFU and SLIC inputs and outputs. x6 lines cross width of 6 PLCs and are unidirectional and buffered with taps in the middle and on the end. Segments allow connectivity to PFU/SLIC outputs (driven at one end-point), other x6 lines (at end-points), and x1 lines for access to PFU/SLIC inputs. xH lines run vertically and horizontally the distance of half the device and are useful for driving medium/long distance 3-state routing. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds even when the I/O signals have been locked to specific pins. The buffered routing capability also allows a very large fanout to be driven from each logic output, thus greatly reducing the amount of logic replication required by synthetic tools. Generally, the ispLEVER Development System is used to automatically route interconnections. Interactive routing with the ispLEVER design editor (EPIC) is also available for design optimization. The routing resources consist of switching circuitry and metal interconnect segments. Generally, the metal lines which carry the signals are designated as routing segments. The switching circuitry connects the routing segments, providing one or more of three basic functions: signal switching, amplification, and isolation. A net running from a PFU, EBR, or PIO output (source) to a PLC, EBR, or PIO input (destination) consists of one or more routing segments, connected by switching circuitry called configurable interconnect points (CIPs). Secondary Clock and Control Nets Secondary clock control and routing provides flexible clocking and control signalling for local regions. Since secondary nets usually have high fanouts and require low skew, the Series 4 devices utilize a spine and branch that uses x6 segments with high-speed connections provided from the spines to the branches. The branches then have high-speed connections to PLC, PIO, and EBR clock and control signals. This strategy provides a flexible connectivity and routes can be sourced from any I/O pin, all PLLs, or from PLC or EBR logic. Secondary Edge Clock Nets and Fast Edge Clock Nets Six secondary edge clock nets per side are distributed around the edges of the device and are available for every PIO. All PIOs and PLLs can drive the secondary edge clocks and are used in conjunction with the secondary spines discussed above to drive the same edge clock signal into the internal logic array. The edge secondary clocks provide fast injection to the PLC array and I/O registers. One of the six secondary edge clocks provided per side of the device is a special fast edge clock net that only clocks input registers for further reduced setup/hold times.This timing path can only be driven from one of the four PIO input pins in each PIC. 31 Clock Distribution Network Clock distribution is made up of three types of clock networks: primary, secondary, and edge clocks. these are described below and more information is available in the Series 4 Clocking Strategies application note. Lattice Semiconductor ORCA Series 4 FPGAs Data Sheet May, 2006 ated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be registered or nonregistered. The Series 4 I/O logic has been enhanced to include modes for high-speed uplink and downlink capabilities. These modes are supported through shift register logic which divides down incoming data or multiplies up outgoing data. This new logic block also supports highspeed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os which meet many new communication standards permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed singleended and differential pair signaling (as shown in Table 13). Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V I/O levels. The I/O on the OR4Exx Series devices allows compliance with PCI local bus (Rev. 2.2) 3.3 V signaling environments. The signaling environment used for each input buffer can be selected on a per-pin basis. The selection provides the appropriate I/O clamping diodes for PCI compliance. More information on the Series 4 programmable I/O structure is available in the various application notes. Routing Resources (continued) Cycle Stealing A new feature in Series 4 FPGAs is the ability to steal time from one register-to-register path and use that time in either the previous path before the first register or in a later path after the last register. This is done through selectable clock delays for every PLC register, EBR register, and PIO register. There are four programmable delay settings, including the default zero added delay value. This allows performance increases on typical critical paths from 15% to 40%. ispLEVER includes software to automatically take advantage of this capability to increase overall system speed. This is done after place and route is completed and uses timing driven algorithms based on the customer’s preference file. A hold time check is also performed to verify no minimum hold time issues are introduced. More information on this clocking feature, including how it can be used to improve device setup times, hold times, clock-to-out delays and can reduce ground bounce caused by switching outputs can be found in the Cycle Stealing application note. Programmable Input/Output Cells (PIC) Programmable I/O The Series 4 programmable I/O addresses the demand for the flexibility to select I/O that meets system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices with the addition of new features which allow the user the flexibility to select new I/O types that support high-speed interfaces. Each PIC contains up to four programmable I/O (PIO) pads and are interfaced through a common interface block (CIB) to the FPGA array. The PIC is split into two pairs of I/O pads with each pair having independent clocks, clock enables, local set/reset, and global set/reset enable/disable. On the input side, each PIO contains a programmable latch/FF which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. On the output side of each PIO, an output from the PLC array can be routed to each output FF, and logic can be associated with each I/O pad. The output logic associ32 32 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Input/Output Cells (continued) Table 13. Series 4 Programmable I/O Standards Standard LVTTL LVCMOS2 LVCMOS18 PCI LVDS Bused-LVDS LVPECL PECL GTL GTL+ HSTL-class I HTSL-class III and IV STTL3-class I and II SSTL2-class I and II VDDIO (V) 3.3 2.5 1.8 3.3 2.5 2.5 3.3 3.3 3.3 3.3 1.5 1.5 3.3 2.5 VREF (V) NA NA NA NA NA NA NA 2.0 0.8 1.0 0.75 0.9 1.5 1.25 General purpose. Interface Usage PCI. Point to point and multi-drop backplanes, high noise immunity. Network backplanes, high noise immunity, bus architecture backplanes. Network backplanes, differential 100 MHz+ clocking, optical transceiver, high-speed networking. Backplanes. Backplane or processor interface. High-speed SRAM and networking interfaces. Synchronous DRAM interface. Note: interfaces to DDR and ZBT memories are supported through the interface standards shown above. The PIOs are located along the perimeter of the device. The PIO name is represented by a two-letter designation to indicate the side of the device on which it is located followed by a number to indicate the row or column in which it is located. The first letter, P, designates that the cell is a PIO and not a PLC. The second letter indicates the side of the array where the PIO is located. The four sides are left (L), right (R), top (T), and bottom (B). A number follows to indicate the PIC row or column. The individual I/O pad is indicated by a single letter (either A, B, C, or D) placed at the end of the PIO name. As an example, PL10A indicates a pad located on the left side of the array in the tenth row. Each PIC interfaces to four bond pads through four PIOs and contains the necessary routing resources to provide an interface between I/O pads and the CIBs. Each PIC contains input buffers, output buffers, routing resources, latches/FFs, and logic and can be configured as an input, output, or bidirectional I/O. Any PIO is capable of supporting the I/O standards listed in Table 13. The CIBs that connect to the PICs have significant local routing resources, similar to routing in the PLCs. This new routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routability. The flexibility provided by the routing also provides for increased signal speed due to a greater variety of optimal signal paths. Included in the routing interface is a fast path from the input pins to the PFU logic. This feature allows for input signals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA. A diagram of a single PIO is shown in Figure 22, and Table 14 provides an overview of the programmable functions in an I/O cell. Lattice Semiconductor 33 ORCA Series 4 FPGAs Data Sheet May, 2006 Programmable Input/Output Cells (continued) LVDS RESISTOR LEVELMODE OUTPUT SIDE LVTTL LVCMOS2 OUTSH OUTDD CLK AND NAND OR NOR XOR XNOR OUTDDMUX OUTDD 0 OUTFFMUX OUTFF 0 EC SC CE CEMUX0 CLK4MUX DEL0 DEL1 DEL2 DEL3 OUTSH PMUX OUTMUX OUTSHMUX CLK OUTDD TSMUX OUTREG OUTREG DO CK SP LSR 1 LSR LSRMUX 0 GSR ENABLED DISABLED CE_OVER_LSR LSR_OVER_CE ASYNC 5-9732(F) RESET SET LATCH FF P2MUX OUTDD USRTS TSREG 1 DO CK LSR RESET SET 0 IOPAD CE PULLMODE UP DOWN NONE NA 1 CEMUXI DEL0 DEL1 DEL2 DEL3 LATCHFF LATCH FF EC SC NORMAL INVERTED PLOGIC BUFMODE SLEW FAST NA LVCMOS18 PCI SSTL2 SSTL3 HSTL1 HSTL3 GTL GTLPLUS PECL LVPECL LVDS DELAY CELL INMUX D0 CK D1 CK SP LSR RESET SET INDDMUX INDD LATCHFF D0 INFF MILLIAMPS SIX TWELVE TWENTYFOUR NA KEEPERMODE OFF ON FAST INPUT INCK INPUT SIDE OFF ON SRMODE Figure 22. Series 4 PIO Image from ispLEVER Design Software 34 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs FF which is clocked by a global primary system clock. The combination of input register capability with nonregistered inputs provides for input signal demultiplexing without any additional resources. The PIO input signal is sent to both the input register and directly to the unregistered input (INDD). The signal is latched and output to routing at INFF. These signals may then be registered or otherwise processed in the PLCs. Every PIO input can also perform input double data rate (DDR) functions with no PLC resources required. This type of scheme is necessary for DDR applications which require data to be clocked in from the I/O on both edges of the clock. In this scheme the input of INFF and INSH are captured on the positive and negative edges of the clock. Table 14. PIO Options Input Input Speed Float Value Register Mode Clock Sense Keeper Mode LVDS Resistor Output Output Speed Output Drive  Current Output Function  Output Sense 3-State Sense Clock Sense Logic Options I/O Controls Clock Enable  Set/Reset Level Set/Reset Type Set/Reset Priority GSR Control Option Fast, Delayed, Normal Pull-up, Pull-down, None Latch, FF, Fast Zero Hold FF,  None (direct input) Inverted, Noninverted on, off on, off Option Fast, Slew 12 mA/6 mA, 6 mA/3 mA, or 24 mA/12 mA Normal, Fast Open Drain Active-high, Active-low Active-high, Active-low Inverted, Noninverted See Table 15 Option Active-high, Active-low,  Always Enabled Active-high, Active-low,  No Local Reset Synchronous, Asynchronous CE over LSR, LSR over CE Enable GSR, Disable GSR Programmable Input/Output Cells (continued) Inputs There are many major options on the PIO inputs that can be selected in the ispLEVER tools listed in Table 14. Inputs may have a pull-up or pull-down resistor selected on an input for signal stabilization and power management. Input signals in a PIO are passed to CIB routing and/or a fast route into the clock routing system. A fast input from one PIO per PIC is also available to drive the edge clock network for fast I/O timing to other nearby PIOs. There is also a programmable delay available on the input. When enabled, this delay affects the INFF and INDD signals of each PIO, but not the clock input. The delay allows any signal to have a guaranteed zero hold time when input. Inputs should have transition times of less than 100 ns and should not be left floating. For full swing inputs, the timing characterization is done for rise/fall times of ≥ 1 V/ns. If any pin is not used, it is 3-stated with an internal pull-up resistor enabled automatically after configuration. Floating inputs increase power consumption, produce oscillations, and increase system noise. The inputs in LVTTL, LVCMOS2, and LVCMOS18 modes have a typical hysteresis of approximately 250 mV to reduce sensitivity to input noise. The PIC contains input circuitry which provides protection against latch-up and electrostatic discharge. The other features of the PIO inputs relate to the latch/ FF structure in the input path. In latch mode, the input signal is fed to a latch that is clocked by either the primary, secondary, or edge clock signal. The clock may be inverted or noninverted. There is also a local set/ reset signal to the latch. The senses of these signals are also programmable as well as the capability to enable or disable the global set/reset signal and select the set/reset priority. The same control signals may also be used to control the input latch/FF when it is configured as a FF instead of a latch, with the addition of another control signal used as a clock enable. The PIOs are paired together and have independent CE, Set/reset, and GSRN control signals per PIO pair. There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a global primary system clock. The fast zero-hold mode of the PIO input takes advantage of a latch/FF combination to latch the data quickly for zero-hold using a fast edge clock before passing the data to the Lattice Semiconductor 35 ORCA Series 4 FPGAs Data Sheet May, 2006 Table 15. PIO Logic Options  Option AND NAND OR NOR XOR XNOR Description Output logical AND of signals on OUTDD  and clock. Output logical NAND of signals on OUTDD  and clock. Output logical OR of signals on OUTDD  and clock. Output logical NOR of signals on OUTDD  and clock. Output logical XOR of signals on OUTDD  and clock. Output logical XNOR of signals on OUTDD  and clock. Programmable Input/Output Cells (continued) Outputs The PIO’s output drivers have programmable drive capability and slew rates. Two propagation delays (fast, slewlim) are available on output drivers. There are three combinations of programmable drive currents (24 mA sink/12 mA source, 12 mA sink/6 mA source, and 6 mA sink/3 mA source). At powerup, the output drivers are in slewlim mode with 12mA sink/6 mA source. If an output is not to be driven in the selected configuration mode, it is 3-stated with a pullup resistor. The output buffer signal can be inverted, and the 3-state control signal can be made active-high, activelow, or always enabled. In addition, this 3-state signal can be registered or nonregistered. Additionally, there is a fast, open-drain output option that directly connects the output signal to the 3-state control, allowing the output buffer to either drive to a logic 0 or 3-state, but never to drive to a logic 1. Every PIO output can perform output data multiplexing with no PLC resources required. This type of scheme is necessary for DDR applications which require data clocking out of the I/O on both edges of the clock. In this scheme the OUTFF and OUTSH are registered and sent out on both the positive and negative edges of the clock using an output multiplexor. This multiplexor is controlled by either the edge clock or system clock. This multiplexor can also be configured to select between one registered output from OUTFF and one nonregistered output from OUTDD. The PIC logic block can also generate logic functions based on the signals on the OUTDD and CLK ports of the PIO. The functions are AND, NAND, OR, NOR, XOR, and XNOR. Table 15 is provided as a summary of the PIO logic options. PIO Register Control Signals The PIO latches/FFs have various clock, clock enable (CE), local set/reset (LSR), and GSRN controls. Table 16 provides a summary of these control signals and their effect on the PIO latches/FFs. Note that all control signals are optionally invertible. Table 16. PIO Register Control Signals  Control  Signal Effect/Functionality Edge Clock  Clocks input fast-capture latch; option(ECLK)  ally clocks output FF, or 3-state FF, or PIO shift registers. System  Clocks input latch/FF; optionally clocks  Clock  output FF, or 3-state FF, or PIO shift  (SCLK) registers. Clock  Optionally enables/disables input FF  Enable (CE) (not available for input latch mode);  optionally enables/disables output FF;  separate CE inversion capability for  input and output. Local Set/ Option to disable; affects input latch/FF,  Reset (LSR) output FF, and 3-state FF if enabled. Global Set/ Option to enable or disable per PIO  Reset  after initial configuration. (GSRN) Set/Reset  The input latch/FF, output FF, and 3Mode state FF are individually set or reset by  both the LSR and GSRN inputs. 36 36 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Input/Output Cells (continued) I/O Banks and Groups Flexible I/O features allow the user to select the type of I/O needed to meet different high-speed interface requirements and these I/Os require different input references or supply voltages. The perimeter of the device is divided into eight banks of PIO buffers, as shown in Figure 23, and for each bank there is a separate VDDIO that supplies the correct input and output voltage for a particular standard. The user must supply the appropriate power supply to the VDDIO pin. Within a bank, several I/O standards may be mixed as long as they use a common VDDIO. The shaded section of the I/O banks in Figure 23 (banks 2, 3, and 4) are removed for FPSCs, to allow the embedded block to be placed on the side of the FPGA array. Bank 1 and bank 5 are also extended to the corners in FPSCs to incorporate more FPGA I/Os. Some interface standards require a specified threshold voltage known as VREF. To accommodate various VREF requirements, each bank is further divided into groups. In these modes, where a particular VREF is required, the device is automatically programmed to dedicate a VREF pin for each group of PIOs within a bank. The appropriate VREF voltage must be supplied by the user and connected to the VREF pin for each group. The VREF is dedicated exclusively to the group and cannot be intermixed within the group with other signaling requiring other VREF voltages. However, pins not requiring VREF can be mixed in the same group. When used to supply a reference voltage the VREF pad is no longer available to the user for general use. The VREF inputs should be well isolated to keep the reference voltage at a consistent level. Table 17. Compatible Mixed I/O Standards  VDDIO Bank Voltage 3.3 V 2.5 V 1.8 V 1.5 V Compatible Standards LVTTL, SSTL3-I, SSTL3-II, GTL+,  GTL, LVPECL, PECL LVCMOS2, SSTL2-I, SSTL2-II, LVDS LVCMOS18 HSTL I, HSTL III, HSTL IV BANK 0 (TL) BANK 1 (TC) BANK 2 (TR) BANK 7 (CL) PLC ARRAY BANK 6 (BL) BANK 5 (BC) BANK 4 (BR) BANK 3 (CR) 0205(F). Figure 23. ORCA High-Speed I/O Banks Differential I/O (LVDS and LVPECL) Series 4 devices support differential input, output, and input/output capabilities through pairs of PIOs. The two standards supported are LVDS and LVPECL. The LVDS differential pair I/O standard allows for highspeed, low-voltage swing and low-power interfaces defined by industry standards: ANSI/TIA/EIA-644 and IEEE 1596.3 SSI-LVDS. The general purpose standard is supplied without the need for an input reference supply and uses a low switching voltage which translates to low ac power dissipation. The ORCA LVDS I/O provides an integrated 100 Ω termination resistor used to provide a differential voltage across the inputs of the receiver. The on-chip integration provides termination of the LVDS receiver without the need of discrete external board resistors. The user has the programmable option to enable termination per receiver pair for point-to-point applications or in multipoint interfaces limit the use of termination to bussed pairs. If the user chooses to terminate any differential receiver, a single LVDS_R pin is dedicated to connect a single 100 Ω (± 1%) resistor to VSS which then enables an internal resistor matching circuit to provide a balance 100 Ω (± 10%) termination across all process, voltage, and temperature. Experiments have also shown that enabling this 100 Ω matching resistor for LVDS outputs also improves performance. Lattice Semiconductor 37 ORCA Series 4 FPGAs Data Sheet May, 2006 Bus Hold Each PIO can be programmed with a KEEPERMODE feature. This element is user programmed for bus hold requirements. This mode retains the last known state of a bus when the bus goes into 3-state. It prevents floating busses and saves system power. PIO Downlink/Uplink (Shift Registers) Each group of four PIOs in a PIC have access to an input/output shift register as shown in Figure 24. This feature allows high-speed input data to be divided down by 1/2 or 1/4 and output data can be multiplied by 2x or 4x its internal speed. Both the input and output shift registers can be programmed to operate at the same time and are controlled by the same clock and control signals. For input shift mode, the data from INDD from the PIO is connected to the input shift register. The input data is divided down and is driven to the routing through the INSH nodes. For output shift mode, the data from the OUTSH nodes are driven from the internal routing and connects to the output shift register. This output data is multiplied up and driven to the OUTDD signal on the PIOs. In 2x output mode or input mode, two of the four I/Os in a PIC can use the shift registers. While in 4x mode, only one I/O can use the shift registers. This also means that all differential I/Os on a Series 4 device can use 2x shift register mode, but 4x mode is only available for half of the differential I/Os. In 4x input mode, all the INSH nodes are used, while 2x mode uses INSH4 and INSH3 for one shift register and INSH2 and INSH1 for the second shift register. Similarly, the output shift register in 4x mode uses all the OUTSH signals. OUTSH2 and OUTSH1 are used for 2x output mode for one shift register and OUTSH4 and OUTSH3 are used for the other output shift register. Programmable Input/Output Cells (continued) High-Speed Memory Interfaces PIO features allow high-speed interfaces to external SRAM and/or DRAM devices. Series 4 I/O meet 200 MHz ZBT requirements when switching between write and read cycles. ZBT allows 100% use of bus cycles during back-to-back read/write and write/read cycles. However this maximum utilization of the bus increases probability of bus contention when the interfaced devices attempt to drive the bus to opposite logic values. The LVTTL I/O interfaces directly with commercial ZBT SRAMs signalling and allows the versatility to program the FPGA drive strengths from 6 mA to 24 mA. DDR allows data to be read on both the rising and the falling edge of the clock which delivers twice the bandwidth. DDR doubles the memory speed from SDRAMs or SRAMs without the need to increase clock frequency. The flexibility of the PIO allows at least 156 MHz/312 Mbits per second performance using the SSTL I/O or HSTL I/O features of the Series 4 devices. High-Speed Networking Interfaces Series 4 devices support many I/O standards used in networking. Two examples of this are the XGMII standard for 10 GbE (HSTL or SSTL I/Os) and the SPI-4 standard for various 10 Gbits/s network interfaces (LVDS I/Os). Both operate as a point-to-point link between devices that are forward clocked and transmit data on both clock edges (DDR). The XGMII interface is 36-bits wide per data flow direction and the SPI-4 interface is a 16-bit interface. The XGMII specification is 156 MHz/312 Mbits/s and the SPI-4 specification that can be met is 325 MHz/650 Mbits/s. More information about using ORCA for these applications can be found in the associated application note. 38 38 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Programmable Input/Output Cells (continued) PIO PIO PIO PIO OUTDD OUTDD OUTDD OUTDD SHIFT REGISTER INTO FPGA OUTSH OUTSH OUTSH OUTSH INDD INDD INDD INDD SHIFT REGISTER OUT FROM FPGA CLK OUTSH4 OUTSH3 OUTSH2 OUTSH1 INTSH2 INSH4 INSH3 INSH1 0204(F). Figure 24. PIO Shift Register Special Function Blocks Special function blocks in the Series 4 provide extra capabilities beyond general FPGA operation. These blocks reside in the corners and MIDs (middle interquad areas) of the FPGA array. Internal Oscillator The internal oscillator resides in the upper left corner of the FPGA array. It has output clock frequencies of 1.25 MHz and 10 MHz. The internal oscillator is the source of the internal CCLK used for configuration. It may also be used after configuration as a generalpurpose clock signal. Global Set/Reset (GSRN) The GSRN logic resides in the upper-left corner of the FPGA. GSRN is an invertible, default, active-low signal that is used to reset all of the user-accessible latches/ FFs on the device. GSRN is automatically asserted at powerup and during configuration of the device. Lattice Semiconductor The timing of the release of GSRN at the end of configuration can be programmed in the start-up logic described below. Following configuration, GSRN may be connected to the RESET pin via dedicated routing, or it may be connected to any signal via normal routing. GSRN can also be controlled via a system bus register command. Within each PFU and PIO, individual FFs and latches can be programmed to either be set or reset when GSRN is asserted. Series 4 allows individual PFUs and PIOs to turn off the GSRN signal to its latches/FFs after configuration. The RESET input pad has a special relationship to GSRN. During configuration, the RESET input pad always initiates a configuration abort, as described in the FPGA States of Operation section. After configuration, the GSRN can either be disabled (the default), directly connected to the RESET input pad, or sourced by a lower-right corner signal. If the RESET input pad is not used as a global reset after configuration, this pad can be used as a normal input pad. 39 ORCA Series 4 FPGAs Data Sheet May, 2006 test data is transmitted serially into TDI of the first BSCAN device (U1), through TDO/TDI connections between BSCAN devices (U2 and U3), and out TDO of the last BSCAN device (U4). In this configuration, the TMS and TCK signals are routed to all boundary-scan ICs in parallel so that all boundary-scan components operate in the same state. In other configurations, multiple scan paths are used instead of a single ring. When multiple scan paths are used, each ring is independently controlled by its own TMS and TCK signals. Figure 26 provides a system interface for components used in the boundary-scan testing of PCBs. The three major components shown are the test host, boundaryscan support circuit, and the devices under test (DUTs). The DUTs shown here are ORCA Series FPGAs with dedicated boundary-scan circuitry. The test host is normally one of the following: automatic test equipment (ATE), a workstation, a PC, or a microprocessor. S TMS TDI TCK TDO U1 TMS TDI TCK TDO U2 Special Function Blocks (continued) Start-Up Logic The start-up logic block can be configured to coordinate the relative timing of the release of GSRN, the activation of all user I/Os, and the assertion of the DONE signal at the end of configuration. If a start-up clock is used to time these events, the start-up clock can come from CCLK, or it can be routed into the startup block using upper-left corner routing resources. Temperature Sensing The built –in temperature sensing diodes allow junction temperature to be measured during device operation. A physical pin (PTEMP) is dedicated for monitoring device junction temperature. PTEMP works by forcing a 10 μA current in the forward direction, and then measuring the resulting voltage. A 250 kΩ resistor tied to 3.3 V will approximate the needed 10 μA. The voltage decreases with increasing temperature at a rate of approximately –1.44 mV/°C. A typical device with an 85°C device temperature will measure about 640 mV. Boundary-Scan The IEEE standards 1149.1 and 1149.2 (IEEE Standard test access port and boundary-scan architecture) are implemented in the ORCA series of FPGAs. It allows users to efficiently test the interconnection between integrated circuits on a PCB as well as test the integrated circuit itself. The IEEE 1149 standard is a well-defined protocol that ensures interoperability among boundary-scan (BSCAN) equipped devices from different vendors. Series 4 FPGAs are also compliant to IEEE standard 1532/D1. This standard for boundary-scan based insystem configuration of programmable devices provides a standardized programming access and methodology for FPGAs. A device, or set of devices, implementing this standard may be programmed, read back, erased verified, singly or concurrently, with a standard set of resources. The IEEE 1149 standards define a test access port (TAP) that consists of a four-pin interface with an optional reset pin for boundary-scan testing of integrated circuits in a system. The ORCA Series FPGA provides four interface pins: test data in (TDI), test mode select (TMS), test clock (TCK), and test data out (TDO). The PRGM pin used to reconfigure the device also resets the boundary-scan logic. The user test host serially loads test commands and test data into the FPGA through these pins to drive outputs and examine inputs. In the configuration shown in Figure 26, where boundary-scan is used to test ICs, 40 40 net a net b net c TDI TMS TCK TDO TMS TDI TCK TDO U3 TMS TDI TCK TDO U4 SEE ENLARGED VEIW BELOW TDO TCK TMS TDI PT[ij] TAPC BYPASS REGISTER INSTRUCTION REGISTER SCAN OUT p_ts p_out p_in PLC ARRAY p_in p_out p_ts SCAN IN BSC BDC p_in p_out SCAN IN PR[ij] DCC p_ts SCAN OUT BSC DCC BDC PL[ij] BSC BDC DCC SCAN IN p_ts SCAN OUT p_out p_in SCAN IN SCAN OUT BSC DCC BDC PB[ij] 5-5972(F) Key:BSC = boundary-scan cell, BDC = bidirectional data cell, and DCC = data control cell. Figure 25. Printed-Circuit Board with Boundary-Scan Circuitry Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Special Function Blocks (continued) D[7:0] D[7:0] BOUNDARYSCAN MASTER TDO TDI ORCA SERIES FPGA TDO TDI ORCA SERIES FPGA TMS (DUT) TCK TDO MICROPROCESSOR INTR CE RA R/W DAV INT SP TMS0 TCK (BSM) TDI TMS (DUT) TCK TDI ORCA SERIES FPGA TMS (DUT) TCK TDO 5-6765(F) Figure 26. Boundary-Scan Interface The boundary-scan support circuit shown in Figure 26 is the 497AA boundary-scan master (BSM). The BSM off-loads tasks from the test host to increase test throughput. To interface between the test host and the DUTs, the BSM has a general MPI and provides parallel-to-serial/serial-to-parallel conversion, as well as three 8K data buffers. The BSM also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. The PC-based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. Boundary-Scan Instructions The Series 4 boundary-scan circuitry supports a total of 18 instructions. This includes ten IEEE 1149.1, 1149.2, and 1532/D1 instructions, one optional IEEE 1149.3 instruction, two IEEE 1532/D1 optional instructions, and five ORCA-defined instructions. There are also 16 other scan chain instructions that are used only during factory device testing and will not be discussed in this data sheet. A 6-bit wide instruction register supports all the instructions listed in Table 18. The BYPASS instruction passes data intentionally from TDI to TDO after being clocked by TCK. Table 18. Boundary-Scan Instructions Code 000000 000001 000011 000100 000101 000110 001000 001001 001010 001011 001101 001110 010001 010010 010011 010100 010101 111111 Instruction EXTEST SAMPLE PRELOAD RUNBIST IDCODE USERCODE ISC_ENABLE ISC_PROGRAM ISC_NOOP ISC_DISABLE ISC_PROGRAM_USERCODE ISC_READ PLC_SCAN_RING1 PLC_SCAN_RING2 PLC_SCAN_RING3 RAM_WRITE RAM_READ BYPASS Lattice Semiconductor 41 ORCA Series 4 FPGAs Data Sheet May, 2006 defined internal scan paths using the PLC latches/FFs and routing interface. The RAM_Write Enable (RAM_W) instruction allows the user to serially configure the FPGA through TDI. The RAM_Read Enable (RAM_R) allows the user to read back RAM contents on TDO after configuration. The IDCODE instruction allows the user to capture a 32-bit identification code that is unique to each device and serially output it at TDO. The IDCODE format is shown in Table 19. An optional IEEE 1149.3 instruction RUNBIST has been implemented. This instruction is used to invoke the built in self test (BIST) of regular structures like RAMs, ROMs, FIFOs, etc., and the surrounding random logic in the circuit. The USERCODE instruction shifts out a 32-bit ID serially at TDO. At powerup, a default value of the IDCODE with the manufacturer field (11-bits) set to all zeros is loaded. The user can set this 11-bit value to a userdefined number during device configuration. It may also be changed by the ISC_PROGRAM_USERCODE instruction, described later. Also implemented in Series 4 devices is the IEEE 1532/D1 standards for in-system configuration for programmable logic devices. Included are 4 mandatory and 2 optional instructions defined in the standards. ISC_ENABLE, ISC_PROGRAM, ISC_NOOP, and ISC_DISABLE are the four mandatory instructions. ISC_ENABLE initializes the devices for all subsequent ISC instructions. The ISC_PROGRAM instruction is similar to the RAM_WRITE instruction implemented in all ORCA devices where the user must monitor the PINITN pin for a high indicating the end of initialization and a successful configuration can be started. The ISC_PROGRAM instruction is used to program the configuration memory through a dedicated ISC_Pdata register. The ISC_NOOP instruction is user when programming multiple devices in parallel. During this mode TDI and TDO behave like BYPASS. The data shifted through TDI is shifted out through TDO. However the output pins remain in control of the BSR unlike BYPASS where they are driven by the system logic. The ISC_DISABLE is used upon completion of the ISC programming. No new ISC instructions will be operable without another ISC_ENABLE instruction. Optional 1532/D1 instructions include ISC_PROGRAM_USERCODE. When this instruction is loaded, the user shifts all 32-bits of a user-defined ID (LSB first) through TDI. This overwrites any ID previously loaded into the ID register. This ID can then be read back through the USERCODE instruction defined in IEEE 1149.2. Special Function Blocks (continued) The external test (EXTEST) instruction allows the interconnections between ICs in a system to be tested for opens and stuck-at faults. If an EXTEST instruction is performed for the system shown in Figure 25, the connections between U1 and U2 (shown by nets a, b, and c) can be tested by driving a value onto the given nets from one device and then determining whether this same value is seen at the other device. This is determined by shifting 3 bits of data for each pin (one for the output value, one for captured input value, and one for the 3-state value) through a boundary scan register (BSR) until each one aligns to the appropriate pin. Then, based upon the value of the 3-state data bit for each pin, either the I/O pad is driven to the value given in the output register of the BSR, or an input signal is applied at the pin. In either case, the BSR input register is updated with the input value from the I/O pad, which allows it to be shifted out TDO. Typically, the user will use the PRELOAD instruction to shift in the first test stimulus for the EXTEST instruction. Note that Series 4 boundary scan includes the ability to perform a selfmonitor on each I/O pin by driving out a value from the output register and checking for this value at the input register of the same I/O pad. The SAMPLE instruction is useful for system debugging and fault diagnosis by allowing the data at the FPGA’s I/Os to be observed during normal operation. The data for all of the I/Os is captured simultaneously into the BSR, allowing them to be shifted-out TDO to the test host. Since each I/O buffer in the PIOs is bidirectional, two pieces of data are captured for each I/O pad: the value at the I/O pad and the value of the 3state control signal. The PRELOAD instruction is used to allow the scanning of the boundary-scan register without causing interference to the normal operation of the on-chip system logic. In turn it allows an initial data pattern to be placed at the latched parallel outputs of BSR prior to selection of another boundary scan test operation. For example, prior to selection of the EXTEST instruction, data can be loaded onto the latched parallel outputs using PRELOAD. As soon as the EXTEST instruction has been transferred to the parallel output of the instruction register, the preloaded data is driven through the system output pins. This ensures that known data, consistent at the board level, is driven immediately when the EXTEST instruction is entered. Without PRELOAD, indeterminate data would be driven until the first scan sequence had been completed. There are six ORCA-defined instructions. The PLC scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow user42 42 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Special Function Blocks (continued) ISC_READ is similar to the ORCA RAM_Read instruction which allows the user to readback the configuration RAM contents serially out on TDO. Both must monitor the PDONE signal to determine weather or not configuration is completed. ISC_READ used a 1-bit register to synchronously readback data coming from the configuration memory. The readback data is clocked into the ISC_READ data register and then clocked out TDO on the falling edge or TCK. Table 19. Series 4E Boundary-Scan Vendor-ID Codes Device OR4E02 OR4E04 OR4E06 Version (4 bit) 0000 0000 0000 Part* (10 bit) 0011100000 0001010000 0000110000 Family (6 bit) 001000 001000 001000 Manufacturer (11 bit) 00000011101 00000011101 00000011101 LSB (1 bit) 1 1 1 * PLC array size of FPGA, reverse bit order. Note: Table assumes version 0. ORCA Boundary-Scan Circuitry The ORCA Series boundary-scan circuitry includes a test access port controller (TAPC), instruction register (IR), boundary-scan register (BSR), and bypass register. It also includes circuitry to support the four predefined instructions. Figure 27 shows a functional diagram of the boundaryscan circuitry that is implemented in the ORCA Series. The input pins’ (TMS, TCK, and TDI) locations vary depending on the part, and the output pin is the dedicated TDO/RD_DATA output pad. Test data in (TDI) is the serial input data. Test mode select (TMS) controls the boundary-scan test access port controller (TAPC). Test clock (TCK) is the test clock on the board. The BSR is a series connection of boundary-scan cells (BSCs) around the periphery of the IC. Each I/O pad on the FPGA, except for CCLK, DONE, and the boundaryscan pins (TCK, TDI, TMS, and TDO), is included in the BSR. The first BSC in the BSR (connected to TDI) is located in the first PIO I/O pad on the left of the top side of the FPGA (PTA PIO). The BSR proceeds clockwise around the top, right, bottom, and left sides of the array. The last BSC in the BSR (connected to TDO) is located on the top of the left side of the array (PL1D). The bypass instruction uses a single FF, which resynchronizes test data that is not part of the current scan operation. In a bypass instruction, test data received on TDI is shifted out of the bypass register to TDO. Since the BSR (which requires a two FF delay for each pad) is bypassed, test throughput is increased when devices that are not part of a test operation are bypassed. The boundary-scan logic is enabled before and during configuration. After configuration, a configuration option determines whether or not boundary-scan logic is used. The 32-bit boundary-scan identification register contains the manufacturer’s ID number, unique part number, and version (as described earlier). The identification register is the default source for data on TDO after RESET if the TAP controller selects the shiftdata-register (SHIFT-DR) instruction. If boundary scan is not used, TMS, TDI, and TCK become user I/Os, and TDO is 3-stated or used in the readback operation. Lattice Semiconductor 43 ORCA Series 4 FPGAs Data Sheet May, 2006 Special Function Blocks (continued) I/O BUFFERS DATA REGISTERS BOUNDARY-SCAN REGISTER IDCODE/USER CODE REGISTER PSR1,PSR2,PSR3 REGISTERS (PLCs) ISC READ/WRITE REGISTERS VDD CONFIGURATION REGISTER (RAM_R, RAM_W) BYPASS AND ISC_DEFAULT REGISTER DATA MUX TDI INSTRUCTION DECODER M U X TDO INSTRUCTION REGISTER VDD RESET CLOCK DR SHIFT-DR UPDATE-DR RESET CLOCK IR SHIFT-IR UPDATE-IR TMS VDD TCK VDD PRGM TAP CONTROLLER PUR SELECT ENABLE 5-5768(F).b Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram ORCA Series TAP Controller (TAPC) The ORCA Series TAP controller (TAPC) is a 1149 compatible test access port controller. The 16 JTAG state assignments from the IEEE 1149 specification are used. The TAPC is controlled by TCK and TMS. The TAPC states are used for loading the IR to allow three basic functions in testing: providing test stimuli (Update-DR), test execution (Run-Test/Idle), and obtaining test responses (Capture-DR). The TAPC allows the test host to shift in and out both instructions and test data/results. The inputs and outputs of the TAPC are provided in the table below. The outputs are primarily the control signals to the instruction register and the data register. Table 20. TAP Controller Input/Outputs Symbol TMS TCK PUR PRGM  TRESET Select Enable Capture-DR Capture-IR Shift-DR Shift-IR Update-DR Update-IR I/O I I I I O O O O O O O O O Function Test Mode Select Test Clock Powerup Reset BSCAN Reset Test Logic Reset Select IR (High); Select-DR (Low) Test Data Out Enable Capture/Parallel Load-DR Capture/Parallel Load-IR Shift Data Register Shift Instruction Register Update/Parallel Load-DR Update/Parallel Load-IR 44 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Special Function Blocks (continued) The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data registers. In the capture operation, data is loaded into the register. In the shift operation, the captured data is shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruction decode, or the boundary-scan register is updated for control of outputs. The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This sequences the TAPC through states in order to perform the desired function on the instruction register or a data register. Figure 28 provides a diagram of the state transitions for the TAPC. The next state is determined by the TMS input value. TEST-LOGICRESET 0 0 RUN-TEST/ IDLE 1 SELECTDR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECTIR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 1 5-5370(F) Figure 28. TAP Controller State Transition Diagram Boundary-Scan Cells Figure 29 is a diagram of the boundary-scan cell (BSC) in the ORCA series PIOs. There are four BSCs in each PIC: one for each pad, except as noted above. The BSCs are connected serially to form the BSR. The BSC controls the functionality of the in, out, and 3-state signals for each I/O pad. The BSC allows the I/O to function in either the normal or test mode. Normal mode is defined as when an output buffer receives input from the PLC array and provides output at the pad or when an input buffer provides input from the pad to the PLC array. In the test mode, the BSC executes a boundary-scan operation, such as shifting in scan data from an upstream BSC in the BSR, providing test stimuli to the pad, capturing test data at the pad, etc. The primary functions of the BSC are shifting scan data serially in the BSR and observing input (p_in), output Lattice Semiconductor (p_out), and 3-state (p_ts) signals at the pads. The BSC consists of three circuits: the bidirectional data cell is used to access the input and output data, the capture cell is used to capture the status of the I/O pad, and the direction control cell is used to access the 3state value. All three cells consist of a FF used to shift scan data which feeds a FF to control the I/O buffer. The capture cell is connected serially to the bidirectional data cell, which is connected serially to the direction control cell to form a boundary-scan shift register. The TAPC signals (capture, update, shiftn, treset, and TCK) and the MODE signal control the operation of the BSC. The bidirectional data cell is also controlled by the high out/low in (HOLI) signal generated by the direction control cell. When HOLI is low, the bidirectional data cell receives input buffer data into the BSC. When HOLI is high, the BSC is loaded with functional data from the PLC. 45 ORCA Series 4 FPGAs Data Sheet May, 2006 Special Function Blocks (continued) The MODE signal is generated from the decode of the instruction register. When the MODE signal is high (EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE), functional data from the FPGA’s internal logic is propagated to the output buffer. The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the ispLEVER CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information. SCAN IN CAPTURE CELL 0 1 D Q D Q INBS (TO FPGA ARRAY) I/O BUFFER PAD_IN P_IN BIDIRECTIONAL DATA CELL 0 D Q D Q 1 PAD_OUT 0 0 1 PAD_TS P_OUT 1 HOLI 0 0 P_TS D Q 1 D Q 1 DIRECTION CONTROL CELL SHIFTN/CAPTURE TCK SCAN OUT UPDATE/TCK MODE 5-2844(F).a Figure 29. Boundary-Scan Cell Boundary-Scan Timing To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum frequency allowed for TCK is 20 MHz. Figure 30 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is clocked into the DUT on the rising edge. 46 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Special Function Blocks (continued) TEST-LOGIC-RESET SELECT-DR-SCAN SELECT-IR-SCAN RUN-TEST/IDLE RUN-TEST/IDLE CAPTURE-IR PAUSE-IR TCK TMS TDI UPDATE-IR SHIFT-IR EXIT1-IR EXIT2-IR SHIFT-IR EXIT1-IR 5-5971(F) Figure 30. Instruction Register Scan Timing Diagram Single Function Blocks Most of the special function blocks perform a specific dedicated function. These functions are data/configuration readback control, global 3-state control (TS_ALL), internal oscillator generation, GSRN, and start-up logic. Readback Logic The readback logic can be enabled via a bit stream option or by instantiation of a library readback component. Readback is used to read back the configuration data and, optionally, the state of the PFU outputs. A readback operation can be done while the FPGA is in normal system operation. The readback operation cannot be daisy-chained. To use readback, the user selects options in the bit stream generator in the ispLEVER development system. Table 21 provides readback options selected in the bit stream generator tool. The table provides the number of times that the configuration data can be read back. This is intended primarily to give the user control over the security of the FPGA’s configuration program. The user can prohibit readback (0), allow a single readback (1), or allow unrestricted readback (U). Table 21. Readback Options Option 0 1 U Function Prohibit Readback Allow One Readback Only Allow Unrestricted Number of Readbacks Readback can be performed via the Series 4 MPI or by using dedicated FPGA readback controls. If the MPI is enabled, readback via the dedicated FPGA readback logic is disabled. Readback using the MPI is discussed in the MPI section. The pins used for dedicated readback are readback data (RD_DATA), read configuration (RD_CFG), and configuration clock (CCLK). A readback operation is initiated by a high-to-low transition on RD_CFG. The RD_CFG input must remain low during the readback operation. The readback operation can be restarted at frame 0 by driving the RD_CFG pin high, applying at least two rising edges of CCLK, and then driving RD_CFG low again. One bit of data is shifted out on RD_DATA at the rising edge of CCLK. The first start bit of the readback frame is transmitted out several cycles after the first rising edge of CCLK after RD_CFG is input low (see the readback timing characteristics table in the timing characteristics section). To be certain of the start of the readback frame, the data can be monitored for the 01 frame start bit pair. Lattice Semiconductor 47 ORCA Series 4 FPGAs Data Sheet May, 2006 The readback frame has an identical format to that of the configuration data frame, which is discussed later in the Configuration Data Format section. If LUT memory is not used as RAM and there is no data capture, the readback data (not just the format) will be identical to the configuration data for the same frame. This eases a bitwise comparison between the configuration and readback data. The configuration header, including the length count field, is not part of the readback frame. The readback frame contains bits in locations not used in the configuration. These locations need to be masked out when comparing the configuration and readback frames. The development system optionally provides a readback bit stream to compare to readback data from the FPGA. Also note that if any of the LUTs are used as RAM and new data is written to them, these bits will not have the same values as the original configuration data frame either. Global 3-State Control (TS_ALL) To increase the testability of the ORCA Series FPGAs, the global 3-state function (TS_ALL) disables the device. The TS_ALL signal is driven from either an external pin or an internal signal. Before and during configuration, the TS_ALL signal is driven by the input pad RD_CFG. After configuration, the TS_ALL signal can be disabled, driven from the RD_CFG input pad, or driven by a general routing signal in the upper right corner. Before configuration, TS_ALL is active-low; after configuration, the sense of TS_ALL can be inverted. The following occur when TS_ALL is activated: ■ Special Function Blocks (continued) Readback can be initiated at an address other than frame 0 via the new MPI control registers (see the MPI section for more information). In all cases, readback is performed at sequential addresses from the start address. It should be noted that the RD_DATA output pin is also used as the dedicated boundary-scan output pin, TDO. If this pin is being used as TDO, the RD_DATA output from readback can be routed internally to any other pin desired. The RD_CFG input pin is also used to control the global 3-state (TS_ALL) function. Before and during configuration, the TS_ALL signal is always driven by the RD_CFG input and readback is disabled. After configuration, the selection as to whether this input drives the readback or global 3-state function is determined by a set of bit stream options. If used as the RD_CFG input for readback, the internal TS_ALL input can be routed internally to be driven by any input pin. The readback frame contains the configuration data and the state of the internal logic. During readback, the value of all registered PFU and PIO outputs can be captured. The following options are allowed when doing a capture of the PFU outputs. ■ Do not capture data (the data written to the RAMs, usually 0, will be read back). Capture data upon entering readback. Capture data based upon a configurable signal internal to the FPGA. If this signal is tied to logic 0, capture RAMs are written continuously. Capture data on either options two or three above. ■ ■ ■ All of the user I/O output buffers are 3-stated, the user I/O input buffers are pulled up (with the pulldown disabled), and the input buffers are configured with TTL input thresholds. The TDO/RD_DATA output buffer is 3-stated. The RD_CFG, RESET, and PRGM input buffers remain active with a pull-up. The DONE output buffer is 3-stated, and the input buffer is pulled up. ■ ■ ■ 48 48 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs nects all the FPGA elements together with a standardized bus framework. The ESB facilitates communication among MPI, configuration, EBRs, and user logic in all the generic FPGA devices. AHB serves the need for high-performance system-on-chip  (SoC) as well as aligning with current synthesis design flows. Multiple bus masters optimizes system performance by sharing resources between different bus masters such as the MPI and configuration logic. The wide data bus configuration of 32-bits with 4-bit parity supports the high-bandwidth of data-intensive applications of using the wide on-chip memory. AMBA enhances a reusable design methodology by defining a common backbone for IP modules. The ESB is a synchronous bus that is driven by either the MPI clock, internal oscillator, CCLK (slave configuration modes), TCK (JTAG configuration modes), or by a user clock from routing. In FPSCs, a clock from the embedded block can also drive the MPI clock. During initial configuration and reconfiguration the bus clock is defaulted to the configuration clock. The post configuration clock source is set during configuration. The user has the ability to program several slaves through the user logic interface. Embedded block RAM also interfaces seamlessly to the system bus. A single bus arbiter controls the traffic on the bus by ensuring only one master has access to the bus at any time. The arbiter monitors a number of different requests to use the bus and decides which request is currently the highest priority. The configuration modes have the highest priority and overrides all normal user modes. Priority can be programmed between MPI and user logic at configuration in generic FPGAs. If no priority is set a round-robin approach is used by granting the next requesting master in a rotating fixed order. Several interfaces exist between the ESB and other FPGA elements. The MPI interface acts as a bridge between the external microprocessor bus and ESB. The MPI may work in an independent clock domain from the ESB if the ESB clock is not sourced from the external microprocessor clock. Pipelined operation allows high-speed memory interface to the EBR and peripheral access without the requirement for additional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of the nature of the transfers. Table 23 is a listing of the ESB register file and brief descriptions. Table 24 shows the system interrupt registers and Table 25 and Table 26 show the FPGA status and command registers, all with brief descriptions. More information is available in the Series 4 MPI and System Bus application note. Microprocessor Interface (MPI) The Series 4 FPGAs have a dedicated synchronous MPI function block. The MPI is programmable to operate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration and readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. In addition to dedicated-function registers, the MPI bridges to the AMBA embedded system bus through which the PowerPC bus master can access the FPGA configuration logic, EBR and other user logic. There is also capability to interrupt the host processor either by a hard interrupt or by having the host processor poll the MPI and the embedded system bus. The control portion of the MPI is available following powerup of the FPGA if the mode pins specify MPI mode, even if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus can be 1-, 2-, or 4-bit. In configuration mode the data and parity bus width are related to the state of the M[0:3] mode pins. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI library element in your design from the ORCA macro library, or by setting the bit of the MPI configuration control register prior to the start of configuration. The user can also enable and disable the parity bus through the configuration bit stream. These pads can be used as general I/O when they are not needed for MPI use. Table 22 shows the interface signals that are used to interface Series 4 devices to a PowerPC MPC860/ MPC8260 device. More information is available in the Series 4 MPI and System Bus application note. The ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The MPI interfaces to the user-programmable FPGA logic using the AMBA embedded system bus.The MPI has access to a series of addressable registers made accessible by the AMBA system bus that provide MPI control and status, configuration and readback data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The address map for these registers and the user-logic address space utilize the same registers as the AMBA embedded system bus. Embedded System Bus (ESB) Implemented using the open standard, on-chip AMBAAHB 2.0 specification bus, the Series 4 devices conLattice Semiconductor 49 ORCA Series 4 FPGAs Data Sheet May, 2006 Microprocessor Interface (continued) Table 22. MPC 860 to ORCA MPI Interconnection PowerPC Signal D[0:n] DP[0:m] A[14:31] TS BURST — — CLKOUT RD/WR TA BDIP ORCA Pin Name D[0:n] DP[0:m] PPC_A[14:31] MPI_STRB MPI_BURST CS0 CS1 MPI_CLK MPI_RW MPI_ACK MPI_BDIP MPI I/O I/O I/O I I I I I I I O I 8, 16, 32-bit data bus. Selectable parity bus width from1, 2, and 4-bit. 32-bit MPI address bus. Transfer start signal. Active-low indicates burst transfer in-progress. High indicates current transfer not a burst. Active-low MPI select. Active-high MPI select. PowerPC interface clock. Read (high)/write (low) signal. Active-low transfer acknowledge signal. Active-low burst transfer in progress signal indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. Active-low interrupt request signal. Active-low indicates MPI detects a bus error on the internal system bus for current transaction. Requests the MPC860/MPC8260 to relinquish the bus and retry the cycle. Driven to indicate the data transfer size for the transaction (byte, half-word, word). Function Any of IRQ[7:0] TEA RETRY TSZ[0:1] MPI_IRQ MPI_TEA MPI_RTRY MPI_TSZ[0:1] O O O I 50 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Microprocessor Interface (continued) Table 23. Embedded System Bus/MPI Registers Register 00 01 02 03 04 Byte 03-00 07-04 0B-08 0F-0C 13 12 11 10 17-14 1B-18 1F-1C 23-20 27-24 2B-28 2F-2C 33-30 37-34 3B-38 3F-3C 43—40 47—44 53—50 63—60 67—64 73—70 Read/Write Initial Value RO R/W R/W RO R/W R/W R/W RO R/W RO R/W RO RO RO RO RO RO RO RO — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Description 32-bit device ID Scratchpad register Command register Status register Interrupt enable register – MPI Interrupt enable register – USER Interrupt enable register – FPSC (unused for FPGAs) Interrupt cause register Readback address register (14 bits) Readback data register Configuration data register Trap address register Bus error address register Interrupt vector 1 predefined by configuration bit stream Interrupt vector 2 predefined by configuration bit stream Interrupt vector 3 predefined by configuration bit stream Interrupt vector 4 predefined by configuration bit stream Interrupt vector 5 predefined by configuration bit stream Interrupt vector 6 predefined by configuration bit stream Top-left PPLL Top-left HPLL Top-right PPLL Bottom-left PPLL Bottom-left HPLL Bottom-right PPLL 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 14 18 19 1C Note: RO = Read Only, R/W = Read/Write Table 24. Interrupt Register Space Assignments Byte 13 12 11 10 bit 7-0 7-0 7-0 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W RO RO RO RO RO RO RO RO Description Interrupt Enable Register – MPI Interrupt Enable Register – USER Interrupt Enable Register – FPSC Interrupt Cause Registers USER_IRQ_GENERAL; USER_IRQ_SLAVE; USER_IRQ_MASTER; CFG_IRQ_DATA; ERR_FLAG 1 MPI_IRQ FPSC_IRQ_SLAVE; FPSC_IRQ_MASTER Note: RO = Read Only, R/W = Read/Write. For internal system bus, bit 7 is most significant bit, for MPI bit 0 is most significant bit. Lattice Semiconductor 51 ORCA Series 4 FPGAs Data Sheet May, 2006 Microprocessor Interface (continued) Table 25. Status Register Space Assignments Byte 0F 0E OD bit 7:0 7:0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Read/Write — — RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Description Reserved Reserved Configuration Write Data Acknowledge Readback Data Ready Unassigned (Zero) Unassigned (Zero) FPSC_BIT_ERR RAM_BIT_ERR Configuration Write Data Size (1, 2, or 4 bytes) Use with above for HSIZE[1:0] (byte, half-word, word) Readback Addresses Out of Range Error Response Received by CFG From System Bus Error Responses Received by CFG From System Bus CFG_DATA_LOST DONE INIT_N ERR_FLAG 1 ERR_FLAG 0 0C Notes: RO = Read Only. For internal system bus, bit 7 is most significant bit, for MPI bit 0 is most significant bit. Table 26. Command Register Space Assignments Byte 0B 0A 09 bit 7:0 7:0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Read/Write — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved Reserved SYS_GSR (GSR Input) SYS_RD_CFG (similar to FPGA pin RD_CFGN, but active high) PRGM from MPI > (similar to FPGA pin, but active high) PRGM from USER > (similar to FPGA pin, but active high) PRGM from FPSC > (similar to FPGA pin, but active high) LOCK from MPI LOCK from USER LOCK from FPSC Bus Reset from MPI (resets system bus and registers) Bus Reset from USER (resets system bus and registers) Bus Reset from FPSC (resets system bus and registers) SYS_DAISY REPEAT_RDBK (don't increment readback address) MPI_USR_ENABLE Readback Data Size (1, 2, or 4 bytes) Use with above for HSIZE[1:0] 08 Note: R/W = Read/Write. For internal system bus; bit 7 is most significant bit, for MPI bit 0 is most significant bit. 52 Lattice Semiconductor Data Sheet May, 2006 ORCA Series 4 FPGAs Phase-Locked Loops (PLLs) There are eight PLLs available to perform many clock modification and clock conditioning functions on the Series 4 FPGAs. Six of the PLLs are programmable allowing the user the flexibility to configure the PLL to manipulate the frequency, phase, and duty cycle of a clock signal. Four of the programmable PLLs (PPLLs) are capable of manipulating and conditioning clocks from 15 MHz to 200 MHz and two others (HPPLLs) are capable of manipulating and conditioning clocks from 60 MHz to 420 MHz. Frequencies can be adjusted from 1/64x to 64x the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors with the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic delay compensation mode is available for phase delay. Each PPLL and HPPLL provides two outputs that can have programmable (45 degree increments) phase differences. The PPLLs and HPPLLs can be utilized to eliminate skew between the clock input pad and the internal clock inputs across the entire device. Both the PPLLS or the HPPLLs can drive onto the primary and secondary clock networks inside the FPGA. Each can take a clock input from the dedicated pad or differential pair of pads in its corner or from general routing resources. Functionality of the PPLLs and HPPLLs is programmed during operation through a control register internal to the FPGA array or via the configuration bit stream. The embedded system bus enables access to these registers (see Table 23). There is also a PLL output signal, LOCK, that indicates a stable output clock state. Table 27. PPLL Specifications Parameter VDD15 VDD33 Operating Temp Input Clock Frequency (No division) Output Clock Frequency Min 1.425 3.0 –40 2.0 7.5 15 60 30 45 — Nom Max Unit V V C MHz MHz % % μs — — % degrees degrees PPLL HPPLL PPLL HPPLL Input Duty Cycle Output Duty Cycle Lock Time Frequency Multiplication Frequency Division Duty Cycle Adjust of Output Clock Delay Adjust of Output Clock Phase Shift Between MCLK and NCLK 1.5 1.575 3.3 3.6 — 125 — 200 — 420 — 200 — 420 — 70 50 55