TN1112

Input Hysteresis in Lattice CPLD and FPGA Devices September 2006 Technical Note TN1112 Introduction In order to optimize speed in Lattice devices such as the ispMACH™ 4000 and MachXO™, device inputs are configurable with internal pull-up, pull-down, bus-hold latch or no bus maintenance. Typically, inputs can tolerate rise and fall times in the 50ns to 100ns range. When interfacing to slow input signals with input rise and fall time in hundreds of nanoseconds, external board design techniques are necessary to make the slow input signals immune to input noise that may be injected. This technical note suggests a few such techniques. Input Circuit Techniques Simple external circuitry along with the internal bus maintenance circuit can significantly improve slow rising and falling input noise immunity. Three common methods are described below. Figure 1. Method 1: Input Series Resistor Cin 20 59 Cout Figure 2. Method 2: Input and Feedback Resistor HCout 21 Cin 20 59 Cout Figure 3. Method 3: Input Resistor and Feedback Capacitor HCout 21 Cin 20 59 Cout The following experimental data was collected to demonstrate the improvement that can be achieved with the different methods as compared to inputs without any external circuitry. The tables below highlight the maximum input rise (tRISE) and fall (tFALL) time of the results. Test Device: MachXO I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on Temperature: Room temperature External Input Circuit None Method 1 Input Series Resistor — 100Ω 470Ω 680Ω tRISE 15ms tFALL 15ms © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 tn1112_01.1 Lattice Semiconductor Test Device: ispMACH 4128V I/O Standard: LVCMOS 3.3V with input bus-hold latch turned on Temperature: Room temperature External Input Circuit None Method 1 Input Series Resistor — 100Ω 1KΩ 4.7KΩ Method 2 100Ω 1KΩ Method 3 100Ω 1KΩ Feedback Resistor or Capacitor — — — — 1KΩ 560Ω 10KΩ 33pF 100pF 33pF Input Hysteresis in Lattice CPLD and FPGA Devices tRISE