LS3956

LS3954A LS3954 LS3955 LS3956 LS3958 Linear Integrated Systems FEATURES LOW DRIFT LOW LEAKAGE LOW NOISE |∆VGS1-2 /∆T|= 5µV/°C max. IG = 20pA TYP. en= 10nV/√Hz TYP. LOW NOISE LOW DRIFT MONOLITHIC DUAL N-CHANNEL JFET ABSOLUTE MAXIMUM RATINGS NOTE 1 @ 25°C (unless otherwise noted) Maximum Temperatures Storage Temperature Operating Junction Temperature G1 -65° to +200°C +150°C D1 S1 D12 G1 G2 S2 D2 31 X 32 MILS 400mW @ 25°C BOTTOM VIEW 1 S1 7 G2 6 D2 3 5 S2 Maximum Voltage and Current for Each Transistor NOTE 1 Gate to Drain or Source Voltage 60V -VGSS -VDSO -IG(f) Drain to Source Voltage Gate Forward Current 60V 50mA Maximum Power Dissipation Device Dissipation @ Free Air - Total ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL CHARACTERISTICS LS3954A LS3954 LS3955 LS3956 LS3958 UNITS CONDITIONS 5 10 25 50 100 µV/°C VDG= 20V, ID= 200µA |∆VGS1-2 /∆T| max. Drift vs. Temperature |VGS1-2| max. SYMBOL BVGSS BVGGO Yfss Yfs |Yfs1-2/Yfs| IDSS |IDSS1-2/IDSS| VGS(off) or VP VGS -IG -IG -IG -IGSS Offset Voltage CHARACTERISTICS Breakdown Voltage Gate-to-Gate Breakdown TRANSCONDUCTANCE Full Conduction Typical Operation Mismatch DRAIN CURRENT Full Conduction Mismatch at Full Conduction GATE VOLTAGE Pinchoff Voltage Operating Range GATE CURRENT Operating High Temperature Reduced VDG At Full Conduction ----20 -5 -50 50 -100 pA nA pA pA VDG= 20V VDG= 20V VDG= 10V VDG= 20V ID= 200µA ID= 200µA ID= 200µA VDS= 0 1 0.5 2 -4.5 4 V V VDS= 20V VDS= 20V ID= 1nA ID= 200µA 0.5 -2 1 5 5 mA % VDG= 20V VGS= 0 1000 500 -2000 700 0.6 3000 1000 3 µmho µmho % VDG= 20V VDG= 20V VGS= 0 f= 1kHz ID= 200µA 5 MIN. 60 60 5 TYP. --10 MAX. --15 UNITS V V 25 mV VDG= 20V, ID= 200µA TA= -55°C to +125°C CONDITIONS VDS= 0 ID= 1µA IG= 1nA ID= 0 IS= 0 TA=+125°C Linear Integrated Systems 4042 Clipper Court, Fremont, CA 94538 • TEL: (510) 490-9160 • FAX: (510) 353-0261 SYMBOL YOSS YOS |YOS1-2| CMR CMR NF en CHARACTERISTICS OUTPUT CONDUCTANCE Full Conduction Operating Differential COMMON MODE REJECTION -20 log |∆VGS1-2/∆VDS| -20 log |∆VGS1-2/∆VDS| NOISE Figure Voltage CAPACITANCE Input Reverse Transfer Drain-to-Drain MIN. -------- TYP. -0.1 0.01 100 75 --- MAX. 5 1 0.1 --0.5 15 UNITS µmho µmho µmho dB dB dB nV/√Hz CONDITIONS VDG= 20V VDG= 20V VGS= 0 ID= 200µA ∆VDS= 10 to 20V ∆VDS= 5 to 10V ID= 200µA ID= 200µA RG= 10MΩ VDS= 20V VGS= 0 f= 100Hz NBW= 6Hz VDS= 20V ID= 200µA f= 10Hz NBW= 1Hz VDS= 20V VDG= 20V VGS= 0 f= 1MHz ID= 200µA CISS CRSS CDD ---- --0.1 6 2 -- pF pF pF TO-71 Six Lead 0.195 DIA. 0.175 0.030 MAX. 0.230 DIA. 0.209 0.150 0.115 TO-78 0.305 0.335 0.335 0.370 MAX. 0.040 0.165 0.185 MIN. 0.500 SEATING PLANE 0.200 0.100 P-DIP 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX. S1 D1 SS G1 1 2 3 4 8 7 6 5 G2 SS D2 S2 0.016 0.019 DIM. A 0.016 0.021 DIM. B 0.029 0.045 2 34 1 5 8 76 6 LEADS 0.019 DIA. 0.016 0.100 0.500 MIN. 0.050 234 1 8 5 6 7 SOIC 0.150 (3.81) 0.158 (4.01) 0.100 45° 0.046 0.036 45° 0.048 0.028 0.028 0.034 0.188 (4.78) 0.197 (5.00) S1 D1 SS G1 1 2 3 4 8 7 6 5 G2 SS D2 S2 0.228 (5.79) 0.244 (6.20) NOTES: 1. These ratings are limiting values above which the serviceability of any semiconductor may be impaired. Linear Integrated Systems 4042 Clipper Court, Fremont, CA 94538 • TEL: (510) 490-9160 • FAX: (510) 353-0261