LTC1409
12-Bit, 800ksps Sampling
A/D Converter with Shutdown
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DESCRIPTIO
FEATURES
■
■
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■
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Sample Rate: 800ksps
Power Dissipation: 80mW
72.5dB S/(N + D) and 86dB THD at Nyquist
No Pipeline Delay
Nap (4mW) and Sleep (10µW) Shutdown Modes
Operates with Internal 15ppm/°C Reference
or External Reference
True Differential Inputs Reject Common Mode Noise
20MHz Full Power Bandwidth Sampling
±2.5V Bipolar Input Range
28-Pin SO Wide and SSOP Package
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The LTC1409 full-scale input range is ±2.5V. Maximum
DC specs include ±1LSB INL and ±1LSB DNL over temperature. Outstanding AC performance includes 72.5dB
S/(N + D) at the Nyquist input frequency of 400kHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 20MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
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APPLICATI
The LTC ®1409 is a 1µs, 800ksps, sampling 12-bit A/D
converter that draws only 80mW from ±5V supplies. This
easy-to-use device includes a high dynamic range sampleand-hold and a precision reference. Two digitally selectable
power Shutdown modes provide flexibility for low power
systems.
S
Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectrum Analysis
Imaging Systems
The ADC has a µP compatible, 12-bit parallel output port.
There is no pipeline delay in the conversion results.
A separate convert start input and a data ready signal
(BUSY) ease connections to FIFOs, DSPs and microprocessors. A digital output driver power supply pin allows
direct connection to 3V logic.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATI
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
800kHz, 12-Bit Sampling A/D Converter
12
5V
74
28
26
10
–5V
25
10µF
24
23
22
µP CONTROL
LINES
21
62
NYQUIST
FREQUENCY
10µF
EFFECTIVE BITS
27
68
56
8
50
6
4
S/(N + D) (dB)
LTC1409
DIFFERENTIAL 1
AVDD
+AIN
ANALOG INPUT
(–2.5V TO 2.5V) 2
–AIN
OVDD
2.50V 3 V
VSS
VREF OUTPUT 4 REF
REFCOMP
BUSY
5
10µF
AGND
CS
6
D11(MSB) CONVST
7
D10
RD
8
D9
SHDN
9
D8
NAP/SLP
10
D7
OGND
12-BIT
11
D6
D0
PARALLEL
12
BUS
D5
D1
13
D4
D2
14
DGND
D3
20
19
2
18
17
16
15
fSAMPLE = 800ksps
0
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
10M
LTC1409 • TA02
LTC1409 • TA01
1
LTC1409
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ABSOLUTE
PACKAGE/ORDER I FOR ATIO
RATI GS
AVDD = OVDD = VDD (Notes 1, 2)
TOP VIEW
Supply Voltage (VDD) ................................................ 6V
Negative Supply Voltage (VSS)................................ – 6V
Total Supply Voltage (VDD to VSS) .......................... 12V
Analog Input Voltage
(Note 3) .................................. VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4) ............ VSS – 0.3V to 10V
Digital Output Voltage ............. VSS – 0.3V to VDD + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1409C............................................... 0°C to 70°C
LTC1409I........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
+AIN 1
28 AVDD
–AIN 2
27 OVDD
VREF 3
26 VSS
REFCOMP 4
ORDER
PART NUMBER
LTC1409CG
LTC1409CSW
LTC1409IG
LTC1409ISW
25 BUSY
AGND 5
24 CS
D11(MSB) 6
23 CONVST
D10 7
22 RD
D9 8
21 SHDN
D8 9
20 NAP/SLP
D7 10
19 OGND
D6 11
18 D0
D5 12
17 D1
D4 13
16 D2
DGND 14
15 D3
G PACKAGE
28-LEAD PLASTIC SO
SW PACKAGE
28-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 95°C/W (G)
TJMAX = 110°C, θJA = 130°C/W (SW)
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
PARAMETER
With Internal Reference (Notes 5, 6)
CONDITIONS
MIN
Resolution (No Missing Codes)
Integral Linearity Error
●
(Note 7)
Differential Linearity Error
Offset Error
TYP
MAX
12
Bits
●
±0.3
±1
LSB
●
±0.3
±1
LSB
±2
±6
±8
LSB
LSB
(Note 8)
●
±15
Full-Scale Error
Full-Scale Tempco
IOUT(REF) = 0
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A ALOG I PUT
±15
●
LSB
ppm/°C
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions
During Conversions
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Delay Time
tjitter
Sample-and-Hold Aperture Delay Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
2
UNITS
MIN
TYP
±1
50
–1.5
UNITS
V
17
5
●
– 2.5V < (–AIN = +AIN) < 2.5V
MAX
±2.5
µA
pF
pF
150
ns
ns
5
psRMS
60
dB
LTC1409
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DY A IC ACCURACY
(Note 5)
SYMBOL
PARAMETER
S/(N + D)
Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal (Note 12)
400kHz Input Signal (Note 12)
THD
Total Harmonic Distortion
IMD
CONDITIONS
●
●
MIN
TYP
70
68
73.0
72.5
MAX
UNITS
dB
dB
100kHz Input Signal, First Five Harmonics
400kHz Input Signal, First Five Harmonics
●
– 90
– 86
– 74
dB
dB
Peak Harmonic or Spurious Noise
400kHz Input Signal
●
– 90
– 74
dB
Intermodulation Distortion
fIN1 = 29.37kHz, fIN2 = 32.446kHz
– 84
15
MHz
S/(N + D) ≥ 68dB
1.6
MHz
Full Power Bandwidth
Full Linear Bandwidth
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I TER AL REFERE CE CHARACTERISTICS
dB
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VREF Output Voltage
IOUT = 0
2.480
2.500
2.520
V
VREF Output Tempco
IOUT = 0
±15
ppm/°C
VREF Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.75V
0.01
0.01
LSB/V
LSB/V
VREF Output Resistance
– 0.1mA ≤ |IOUT| ≤ 0.1mA
REFCOMP Output Voltage
IOUT = 0
4
kΩ
4.06
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DIGITAL I PUTS A D DIGITAL OUTPUTS
V
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
MIN
VDD = 4.75V
IO = – 10µA
IO = – 200µA
●
VDD = 4.75V
IO = 160µA
IO = 1.6mA
●
TYP
MAX
2.4
UNITS
V
5
pF
4.5
V
V
4.0
0.05
0.10
0.4
V
V
IOZ
High-Z Output Leakage D11 to D0
VOUT = 0V to VDD, CS High
●
±10
µA
COZ
High-Z Output Capacitance D11 to D0
CS High (Note 9 )
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
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POWER REQUIRE E TS
(Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
VDD
Positive Supply Voltage
(Notes 10, 11)
4.75
VSS
Negative Supply Voltage
(Note 10)
– 4.75
IDD
Positive Supply Current
Nap Mode
Sleep Mode
CS High
●
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
TYP
MAX
UNITS
5.25
V
– 5.25
6.0
0.8
1.0
9.0
1.2
V
mA
mA
µA
3
LTC1409
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POWER REQUIRE E TS
(Note 5)
SYMBOL PARAMETER
CONDITIONS
ISS
Negative Supply Current
Nap Mode
Sleep Mode
CS High
●
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
MIN
PDISS
Power Dissipation
Nap Mode
Sleep Mode
●
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 0V
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TI I G CHARACTERISTICS
TYP
MAX
10
10
1
15
UNITS
mA
µA
µA
80
3.8
0.01
120
6
mW
mW
mW
TYP
MAX
UNITS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
fSAMPLE(MAX)
Maximum Sampling Frequency
●
tCONV
Conversion Time
●
tACQ
Acquisition Time
●
t1
CS to RD Setup Time
(Notes 9, 10)
●
0
ns
t2
CS↓ to CONVST↓ Setup Time
(Notes 9, 10)
●
10
ns
t3
NAP/SLP↓ to SHDN↓ Setup Time
(Notes 9, 10)
●
10
ns
t4
SHDN↑ to CONVST↓ Wake-Up Time (Note 10)
t5
CONVST Low Time
(Notes 10, 11)
t6
CONVST to BUSY Delay
CL = 25pF
●
800
kHz
900
Data Ready Before BUSY↑
t8
Delay Between Conversions
t9
Wait Time RD↓ After BUSY↑
t10
Data Access Time After RD↓
(Note 10)
ns
10
ns
ns
ns
60
●
20
15
●
40
●
–5
CL = 25pF
35
ns
15
20
●
Bus Relinquish Time
ns
ns
ns
●
8
0°C ≤ TA ≤ 70°C
– 40°C ≤ TA ≤ 85°C
ns
50
CL = 100pF
t11
ns
150
200
●
t7
1250
●
●
35
45
45
60
ns
ns
ns
ns
30
35
40
ns
ns
ns
t12
RD Low Time
●
t10
ns
t13
CONVST High Time
●
50
ns
t14
Aperture Delay of Sample-and-Hold
The ● indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
4
– 1.5
ns
Note 5: VDD = 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended +AIN input with –AIN grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
LTC1409
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TI I G CHARACTERISTICS
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 650ns after
conversion start or after BUSY rises.
Note 12: Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
is measured at 400kHz. These results are used to calculate signal-to-noise
plus distortion (SINAD).
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
Signal-to-Noise Ratio vs
Input Frequency
VIN = 0dB
60
VIN = 20dB
50
40
30
20
VIN = 60dB
10
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
70
0
70
60
50
40
30
20
10
0
1k
1M
10k
100k
INPUT FREQUENCY (Hz)
10M
1M
10k
100k
INPUT FREQUENCY (Hz)
1k
LTC1409 • TPC01
0
–10
–20
–30
–40
–50
–60
–70
3RD
–80
THD
–90
2ND
–100
1k
10M
100k
1M
10k
INPUT FREQUENCY (Hz)
10M
LTC1409 • TPC03
LTC1409 • TPC02
Spurious-Free Dynamic Range vs
Input Frequency
Intermodulation Distortion Plot
0
0
fSAMPLE = 800kHz
fIN1 = 88.19580078kHz
fIN2 = 111.9995117kHz
–10
–20
–20
–30
AMPLITUDE (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
Distortion vs Input Frequency
80
SIGNAL/(NOISE + DISTORTION) (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
80
–40
–50
–60
–70
–40
–60
fb – fa
–80
2fa + fb
fa + fb
2fa – fb
2fb – fa
2fa
3fa
2fb
fa + 2fb
3fb
–80
–100
–90
–100
10k
–120
100k
1M
INPUT FREQUENCY (Hz)
10M
LTC1409 • TPC04
0
50k
100k
150k
200k
FREQUENCY (Hz)
250k
300k
350k
400k
LTC1409 • TPC05
5
LTC1409
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TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity vs
Output Code
1.00
1.00
0.50
0.50
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity vs
Output Code
0
–0.50
0
–0.50
–1.00
–1.00
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
LT1409 • TPC06
Power Supply Feedthrough vs
Ripple Frequency
Input Common Mode Rejection vs
Input Frequency
0
80
–10
70
COMMON MODE REJECTION (dB)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
LT1409 • TPC07
–20
–30
–40
–50
–60
–70
DGND
VDD
–80
VSS
–90
–100
60
50
40
30
20
10
0
1k
100k
1M
10k
RIPPLE FREQUENCY (Hz)
10M
LTC1409 • TPC08
1k
1M
10k
100k
INPUT FREQUENCY (Hz)
10M
LT1409 • TPC09
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PI FU CTIO S
+ AIN (Pin 1): Positive Analog Input, ±2.5V.
– AIN (Pin 2): Negative Analog Input, ±2.5V.
VREF (Pin 3): 2.50V Reference Output.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND using 10µF tantalum in parallel with 0.1µF or
10µF ceramic.
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
6
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
OGND (Pin 19): Digital Ground for Output Drivers. Tie
to AGND.
NAP/SLP (Pin 20): Power Shutdown Mode. Selects the
mode invoked by the SHDN pin. Low selects Sleep
mode and high selects quick wake-up Nap mode.
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
LTC1409
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PI FU CTIO S
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND
using 10µF tantalum in parallel 0.1µF or 10µF ceramic.
OVDD (Pin 27): Positive Supply for Output Drivers. For
5V logic, short to Pin 28. For 3V logic, short to supply
of the logic being driven.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
10µF tantalum in parallel with 0.1µF or 10µF ceramic.
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FU CTIO AL BLOCK DIAGRA
CSAMPLE
+AIN
AVDD
CSAMPLE
– AIN
4k
VREF
ZEROING SWITCHES
2.5V REF
+
REF AMP
COMP
12-BIT CAPACITIVE DAC
–
OVDD
REFCOMP
(4.06V)
12
SUCCESSIVE APPROXIMATION
REGISTER
AGND
D11
D0
OGND
INTERNAL
CLOCK
DGND
•
•
•
OUTPUT LATCHES
CONTROL LOGIC
LTC1409 • BD
NAP/SLP SHDN
RD CONVST CS
BUSY
TEST CIRCUITS
Load Circuits for Bus Relinquish Time
Load Circuits for Access Timing
5V
5V
1k
DBN
1k
DBN
1k
CL
DBN
DBN
CL
1k
LTC1409 • TC01
(a) Hi-Z to VOH
and VOL to VOH
(b) Hi-Z to VOL
and VOH to VOL
100pF
100pF
LTC1409 • TC02
(a) VOH to Hi-Z
(b) VOL to Hi-Z
7
LTC1409
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APPLICATIONS INFORMATION
The LTC1409 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the +AIN and –AIN inputs are
connected to the sample-and-hold capacitors (CSAMPLE)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 150ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DACs output balances the +AIN and –AIN input
charges. The SAR contents (a 12-bit data word) which
represents the difference of +AIN and –AIN are loaded into
the 12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1409 has excellent high speed sampling capability. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows typical
LTC1409 plots.
0
fSAMPLE = 800kHz
fIN = 97.45kHz
SFDR = 89.1dB
SINAD = 73.1dB
–20
AMPLITUDE (dB)
CONVERSION DETAILS
–40
–60
–80
–100
–120
0
50
100 150 200 250 300 350 400
LT1409 • F02a
FREQUENCY (kHz)
Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
+CSAMPLE
+AIN
HOLD
0
ZEROING SWITCHES
–CSAMPLE
fSAMPLE = 800kHz
fIN = 375kHz
SFDR = 89dB
SINAD = 72.5dB
HOLD
–20
–AIN
HOLD
AMPLITUDE (dB)
HOLD
+CDAC
+
+VDAC
–CDAC
COMP
–40
–60
–80
–
–100
–VDAC
12
SAR
• D11
•
• D0
OUTPUT
LATCHES
LTC1409 • F01
Figure 1. Simplified Block Diagram
8
–120
0
50
100 150 200 250 300 350 400
FREQUENCY (kHz)
LT1409 • F02b
Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
LTC1409
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APPLICATIONS INFORMATION
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
an 800kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 400kHz.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 800kHz the LTC1409 maintains near ideal ENOBs
up to the Nyquist input frequency of 400kHz. Refer to
Figure 3.
12
10
9
EFFECTIVE BITS
0
–10
–20
–30
–40
–50
–60
–70
3RD
–80
THD
–90
2ND
–100
1k
100k
1M
10k
INPUT FREQUENCY (Hz)
10M
LTC1409 • F04
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
11
8
7
6
5
4
3
2
1
0
V22 + V32 + V42 + …Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD vs input frequency is
shown in Figure 4. The LTC1409 has good distortion
performance up to the Nyquist frequency and beyond.
THD = 20 Log
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
Signal-to-Noise Ratio
fSAMPLE = 800kHz
1k
100k
1M
10k
INPUT FREQUENCY (Hz)
10M
LTC1409 • F03
Figure 3. Effective Bits and Signal/(Noise +
Distortion) vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the DC transfer function
can create distortion products at the sum and difference
frequencies of mfa + –nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb). If
the two input sine waves are equal in magnitude, the value
(in decibels) of the 2nd order IMD products can be
expressed by the following formula:
IMD( fa + fb) = 20 Log
Amplitude at (fa + fb)
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
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0
fSAMPLE = 800kHz
fIN1 = 88.19580078kHz
fIN2 = 111.9995117kHz
AMPLITUDE (dB)
–20
–40
–60
fb – fa
–80
2fa + fb
fa + fb
2fa – fb
2fb – fa
2fa
3fa
2fb
fa + 2fb
3fb
–100
–120
0
50k
100k
150k
200k
FREQUENCY (Hz)
300k
250k
400k
350k
LTC1409 • F05
Figure 5. Intermodulation Distortion Plot
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1409 has been designed to optimize input bandwidth,
allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
Driving the Analog Input
The differential analog inputs of the LTC1409 are easy to
drive. The inputs may be driven differentially or as a
single-ended input (i.e., the –AIN input is grounded). The
+AIN and –AIN inputs are sampled at the same instant.
Any unwanted signal that is common mode to both
inputs will be reduced by the common mode rejection of
the sample-and-hold circuit. The inputs draw only one
small current spike while charging the sample-and-hold
capacitors at the end of conversion. During conversion
the analog inputs draw only a small leakage current. If the
source impedance of the driving circuit is low then the
LTC1409 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For
10
minimum acquisition time, with high source impedance,
a buffer amplifier should be used. The only requirement
is that the amplifier driving the analog input(s) must
settle after the small current spike before the next conversion starts (settling time must be 150ns for full throughput rate).
10
ACQUISITION TIME (µs)
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
1
0.1
0.01
0.01
1
10
0.1
SOURCE RESISTANCE (kΩ)
100
LTC1409 • F06
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a
gain of 1 and has a unity-gain bandwidth of 50MHz, then
the output impedance at 50MHz should be less than
100Ω. The second requirement is that the closed-loop
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bandwidth must be greater than 20MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
The best choice for an op amp to drive the LTC1409 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifications are most critical, and time domain applications
where DC accuracy and settling time are most critical.
The following list is a summary of the op amps that are
suitable for driving the LTC1409, more detailed information is available in the Linear Technology databooks and
the LinearViewTM CD-ROM.
LT ® 1220: 30MHz unity-gain bandwidth voltage feedback amplifier. ±5V to ±15V supplies. Excellent DC
specifications, 90ns settling to 0.5LSB.
LT1223: 100MHz video current feedback amplifier. 6mA
supply current. ±5V to ±15V supplies. Low distortion up
to and above 400kHz. Low noise. Good for AC
applications.
width of the sample-and-hold circuit is 20MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 1000pF
capacitor from + AIN to ground and a 100Ω source resistor
to limit the input bandwidth to 1.6MHz. The 1000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors
can also generate distortion from self heating and from
damage that may occur during soldering. Metal film
surface mount resistors are much less susceptible to both
problems.
When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter
LT1227: 140MHz video current feedback amplifier. 10mA
supply current ±5V to ±15V supplies. Lowest distortion
at frequencies above 400kHz. Low noise. Best for AC
applications.
50Ω
ANALOG INPUT
2
4
LinearView is a trademark of Linear Technology Corporation.
VREF
REFCOMP
10µF
5
AGND
LTC1409 • F07b
Figure 7a. RC Input Filter
LT1363: 50MHz, 450V/µs op amps. 6.3mA supply current. Good AC/DC specs. 60ns settling to 0.5LSB.
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1409 noise and distortion. The small-signal band-
–AIN
LTC1409
3
LT1360: 37MHz voltage feedback amplifier. 3.8mA supply current. Good AC/DC specs. ±5V to ±15V supplies.
70ns settling to 0.5LSB.
Input Filtering
+AIN
1000pF
LT1229/LT1230: Dual and quad 100MHz current feedback amplifiers. ± 2V to ±15V supplies. Low noise. Good
AC specs. 6mA supply current for each amplifier.
LT1364/LT1365: Dual and quad 50MHz, 450V/µs op
amps. 6.3mA supply current per amplifier. 60ns settling
to 0.5LSB.
1
VIN
1
8
2
7
3
LTC1560-1
1
2
6
4
5
VREF
5V
4
0.1µF
–AIN
LTC1409
3
–5V
+AIN
0.1µF
10µF
5
REFCOMP
AGND
LTC1409 • F07
Figure 7b. 500kHz 5th Order Elliptic Lowpass Filter
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is required. Figure 7b shows a simple implementation using
a LTC1560 5th order elliptic continuous time filter.
5V
Input Range
VIN
1
2
The ±2.5V input range of the LTC1409 is optimized for low
noise and low distortion. Most op amps also perform best
over this same range, allowing direct coupling to the
analog inputs and eliminating the need for special translation circuitry.
+AIN
ANALOG INPUT
–AIN
LTC1409
LT1019A-2.5
VOUT
3
4
VREF
REFCOMP
10µF
5
AGND
LTC1409 • F08b
Some applications may require other input ranges. The
LTC1409 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference
and input circuitry and how they affect the input range.
Internal Reference
The LTC1409 has an on-chip, temperature compensated,
curvature corrected, bandgap reference that is factory
trimmed to 2.500V. It is connected internally to a reference
amplifier and is available at VREF (Pin 3) see Figure 8a. A
4k resistor is in series with the output so that it can be
easily overdriven by an external reference or other circuitry. The reference amplifier gains the voltage at the VREF
pin by 1.625 to create the required internal reference
voltage. This provides buffering between the VREF pin and
the high speed capacitive DAC. The reference amplifier
compensation pin, REFCOMP (Pin 4), must be bypassed
with a capacitor to ground. The reference amplifier is
stable with capacitors of 1µF or greater. For the best noise
performance, a 10µF ceramic or 10µF tantalum in parallel
with 0.1µF ceramic is recommended (see Figure 8b).
Figure 8b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1409 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for, after a reference adjustment.
1
+AIN
ANALOG INPUT
2
LTC1450
12-BIT
RAIL-TO-RAIL DAC
–AIN
LTC1409
1.25V TO 3V
3
4
VREF
REFCOMP
10µF
5
AGND
LTC1409 • F09
Figure 9.Driving VREF with a DAC
R1
4k
V
2.5V 3 REF
4.0625V
4 REFCOMP
REFERENCE
AMP
R2
40k
10µF
5 AGND
BANGAP
REFERENCE
R3
64k
LTC1409
LTC1409 • F08a
Figure 8a. LTC1409 Reference Circuit
12
Differential Inputs
The LTC1409 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of +AIN – (–AIN) independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies, see Figure 10a.
The only requirement is that both inputs can not exceed
the AVDD or AV SS power supply voltages. Integral
nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage,
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The output is two’s complement binary with 1LSB =
FS – (– FS)/4096 = 5V/4096 = 1.22mV.
70
60
50
111...111
40
111...110
111...101
30
OUTPUT CODE
COMMON MODE REJECTION (dB)
80
20
10
0
1000
10
100
INPUT FREQUENCY (Hz)
1
10000
000...010
000...001
LTC1409 • TPC09
000...000
–(FS – 1LSB)
Figure 10a. CMRR vs Input Frequency
ANALOG INPUT
1
LTC1409 • F11a
+AIN
±2.5V RANGE
2
0V TO 5V
RANGE
FS – 1LSB
INPUT RANGE
Figure 11a. LTC1409 Transfer Characteristics
–AIN
LTC1409
2.5V
3
VREF
– 5V
1µF
4
R3
24k
R1
50k
REFCOMP
ANALOG INPUT
R4
100Ω
10µF
5
1
2
AGND
LTC1409 • F10b
Figure 10b. Selectable 0V to 5V or ±2.5V Input Range
however, the bipolar zero error (BZE) will vary. The change
in BZE is typically less than 0.1% of the common mode
voltage. Dynamic performance is also affected by the
common mode voltage. THD will degrade as the inputs
approach either power supply rail, from 86dB with a
common mode of 0V to 75dB with a common mode of
2.5V or – 2.5V.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
converts a 0V to 5V analog input signal with no additional
translation circuitry.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics for
the LTC1409. The code transitions occur midway between
successive integer LSB values (i.e., –FS + 0.5LSB, –FS +
1.5LSB, –FS + 2.5LSB,. FS – 1.5LSB, FS – 0.5LSB).
+AIN
–AIN
LTC1409
R5 R2
47k 50k
3
R6
24k
4
VREF
REFCOMP
10µF
5
AGND
LTC1409 • F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the – AIN input. For zero offset error apply –
0.61mV (i.e., – 0.5LSB) at +AIN and adjust the offset at the
– AIN input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to AIN and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
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BOARD LAYOUT AND BYPASSING
The LTC1409 has differential inputs to minimize noise
coupling. Common mode noise on the +AIN and –AIN leads
will be rejected by the input CMRR. The –AIN input can be
used as a ground sense for the +AIN input; the LTC1409
will hold and convert the difference voltage between +AIN
and –AIN. The leads to +AIN (Pin 1) and –AIN (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the +AIN and –AIN traces should be run sideby-side to equalize coupling.
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1409, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
SUPPLY BYPASSING
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the OVDD bypass capacitor should also be connected to
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
width for these tracks should be as wide as possible. In
applications where the ADC data outputs and control
signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the
microprocessor into a WAIT state during conversion or by
using three-state buffers to isolate the ADC data bus. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
1
ANALOG
INPUT
CIRCUITRY
Example Layout
Figure 13a, 13b, 13c and 13d show the schematic and
layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground
plane with a two layer printed circuit board.
DIGITAL
SYSTEM
LTC1409
+AIN
–AIN REFCOMP AGND
+
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the VDD and REFCOMP pins
as shown in the Typical Application on the first page of this
data sheet. Surface mount ceramic capacitors such as
Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively 10µF tantalum
capacitors in parallel with 0.1µF ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and
bypass capacitors must be kept short and should be made
as wide as possible.
2
4
– +
26
+
10µF
0.1µF
AVDD OVDD DGND OGND
28
27
14
19
VSS
5
+
10µF
0.1µF
10µF
0.1µF
ANALOG GROUND PLANE
Figure 12. Power Supply Grounding Practice
14
LTC1409 • F12
R2
10k
J3
GND
J6
1
R5
51Ω
1
2
JP2
U3A
74HC14
2
1
1
2
VCC
3
7
5
3
1
R6
1k
D13
SS12
C11
10µF
10V
JP4
8
6
4
2
VSS
4
10µF 10V
+ C14
22µF
10V
+ C12
C2
0.1µF
SEE NOTE 3
C1
0.1µF
R4
51Ω
C9
0.001µF
NPO
10%
U3B
74HC14
C7
0.1µF
JP1
TAB GND
4
2
OUT
3
JP6
2
OUT
1
4
8
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
NAP/SLP
6
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D(0…11)
C13
22µF
10V
D2
D1
D3
D4
D10
D9
D6
D0
D5
D7
D8
D11
U2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
74HC374
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
10µF
10V
+ C10
VKK
2
5
6
9
12
15
16
19
2
5
6
9
12
15
16
19
C17
15pF
D2
D1
D3
D4
VCC
D10
D9
D6
D0
D5
D7
D8
D11
U3E
74HC14
11
10
C6
0.1µF
74HC374
VKK
D0 VCC
D1
D2
D3
D4
D5
D6
D7
0C
11 CLK
3
4
7
8
13
14
17
18
1
U1
D0 VCC
D1
D2
D3
D4
D5
D6
D7
0C
11 CLK
3
4
7
8
13
14
17
18
1
20
VKK
R6
1k
C5
0.1µF
U3F
74HC14
13
12
C4
0.1µF
DIGITAL I.C.
BYPASSING
NOTES: UNLESS OTHERWISE SPECIFIED.
1. ALL RESISTOR VALUE OHMS, 1/8W, 5%, SMT.
2. ALL CAPACITOR VALUES µF, 50V, 20%, SMT.
3. C14 MAY BE REPLACED WITH A 10µF, 25V, Z5U, CERAMIC
20
19
18
17
16
15
13
12
11
10
9
8
7
6
D14
SS12
VSS
Figure 13a. Suggested Evaluation Circuit Schematic
10µF
10V
+ C9
VCC
AVDD
DVDD
VSS
BUSY
CS
CONVST
RD
SHDN
DGND
AGND
REFCOMP
VREF
–AIN
1
5
OGND
U4
LTC1410
VSS
–
U5
LT1360
+
+AIN
2
3
7
VCC
GND
5
C3
0.1µF
28
27
26
25
24
23
22
21
14
5
4
3
2
1
IN
U6
79L05
R7
20Ω
VKK
VCC
5
9
U3C
74HC14
6
8
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA RDY
U3D
74HC14
R8 TO R15
620Ω
C15
0.1µF
R16 TO R19
620Ω
OP-AMP
DECOUPLING
C16
0.1µF
VSS
JP3
GND
RDY
GND
/D11
D1
D0
D3
D2
D5
D4
D7
D6
D9
D8
D11
D10
J7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
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R2
10k
1
E1
VREF
1 VREF
J5
J4
1
J2
–7V TO
–15V
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APPLICATI
+
U7
LT1121
+
J1
7V TO
15V
LTC1409
15
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Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board Component Side Layout
16
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Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
Digital Interface
The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.9µs, and a maximum conversion time over the
full operating temperature range of 1.15µs. No external
adjustments are required. The guaranteed maximum acquisition time is 150ns. In addition, a throughput time of
1250ns and a minimum sample rate of 800ksps is guaranteed.
from Nap to active is 200ns. In Sleep mode all bias
currents are shut down and only leakage current remains, about 1µA. Wake-up time from Sleep mode is
much slower since the reference circuit must power up
and settle to 0.01% for full 12-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
10ms with the recommended 10µF capacitor.
Shutdown is controlled by Pin 21 (SHDN). The ADC is in
shutdown when it is low. The Shutdown mode is selected
with Pin 20 (NAP/SLP); high selects Nap.
Timing and Control
Power Shutdown
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
The LTC1409 provides two power Shutdown modes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17) CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
17
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can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
NAP/SLP
t3
SHDN
In mode 2 (Figure 18) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU
databus.
LTC1409 • F14a
Figure 14a. NAP/SLP to SHDN Timing
In slow memory and ROM modes (Figures 19 and 20) CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
SHDN
t4
CONVST
LTC1409 • F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
In slow memory mode the processor applies a logic low to
RD (= CONVST) starting the conversion. BUSY goes low
forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD (= CONVST) back
high and reads the new conversion data.
CS
t2
CONVST
t1
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
RD
LTC1409 • F15
Figure 15. CS to CONVST Setup Timing
tCONV
t5
CONVST
t6
t8
BUSY
t7
DATA
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1409 • F16
Figure 16. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =
)
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tCONV
CS = RD = 0
t13
t5
CONVST
t8
t6
t6
BUSY
t7
DATA (N – 1)
DB11 TO DB0
DATA
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1409 • F17
Figure 17. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
t13
tCONV
t8
t5
CONVST
t6
BUSY
t9
t11
t12
RD
t 10
DATA N
DB11 TO DB0
DATA
LTC1409 • F18
Figure 18. Mode 2. CONVST Starts a Conversion. Data is Read by RD
t8
tCONV
RD = CONVST
t6
t11
BUSY
t10
t7
DATA (N – 1)
DB11 TO DB0
DATA
DATA N
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1409 • F19
Figure 19. Slow Memory Mode Timing
tCONV
t8
RD = CONVST
t6
t11
BUSY
t10
DATA
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
LTC1409 • F20
Figure 20. ROM Mode Timing
19
LTC1409
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0.301 – 0.311
(7.65 – 7.90)
0° – 8°
0.022 – 0.037
(0.55 – 0.95)
0.005 – 0.009
(0.13 – 0.22)
0.0256
(0.65)
BSC
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
(0.25 – 0.38)
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1 2 3 4 5 6 7 8 9 10 11 12 13 14
G28 SSOP 0694
SW Package
28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 – 0.712*
(17.70 – 18.08)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.291 – 0.299**
(7.391 – 7.595)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.093 – 0.104
(2.362 – 2.642)
0.037 – 0.045
(0.940 – 1.143)
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0° – 8° TYP
0.050
0.004 – 0.012
(1.270)
(0.102 – 0.305)
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
1
2
3
4
5
6
7
8
9
10 11 12 13 14
S28 (WIDE) 0996
RELATED PRODUCTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1273/75/76
Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Nyquist
300ksps, Single or Dual Supplies
LTC1274/77
Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown
100ksps, 8-Bit or 12-Bit Digital I/O
LTC1278/79
High Speed Sampling 12-Bit ADCs with Shutdown
500ksps/600ksps, Single or Dual Supplies
LTC1282
Complete 3V 12-Bit ADC with 12mW Power Dissipation
Fully Specified for 3V/±3V Supply
LTC1410
High Speed Sampling 12-Bit ADC
1.25Msps, 71dB SINAD at Nyquist, Low Power
LTC1415
High Speed Sampling 12-Bit ADC
1.25Msps, Single 5V Supply, Lowest Power
LTC1419
14-Bit, 800ksps Sampling ADC
81.5dB SINAD, 150mW from ±5V Supplies
LTC1605
16-Bit, 100ksps Sampling ADC
Single Supply, ±10V Input Range, Low Power
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900
FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com
1409f LT/TP 0397 7K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1995
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湘ICP备2023018690号
