LTC1543
Software-Selectable
Multiprotocol Transceiver
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FEATURES
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DESCRIPTIO
The LTC®1543 is a 3-driver/3-receiver multiprotocol
transceiver that operates from a single 5V supply. The
LTC1543 and LTC1544 form the core of a complete softwareselectable DTE or DCE interface port that supports the
RS232, RS449, EIA530, EIA530-A, V.35, V.36 or X.21
protocols. Cable termination may be implemented using the
LTC1344A software-selectable cable termination chip or by
using existing discrete designs.
Software-Selectable Transceiver Supports:
RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21
TUV/Detecon Inc. Certified NET1 and NET2
Compliant (Test Report No. NET2/102201/97)
TBR2 Compliant (Test Report No. CTR2/022701/98)
Software-Selectable Cable Termination Using
the LTC1344A
Complete DTE or DCE Port with LTC1544, LTC1344A
Operates from Single 5V Supply
The LTC1543 runs from a single 5V supply using an internal
charge pump that requires only five space-saving surface
mounted capacitors. The part is available in a 28-lead SSOP
surface mount package.
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APPLICATIO S
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Data Networking
CSU and DSU
Data Routers
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
LL
CTS
DSR
DCD
DTR
RTS
RXD
TXC
RXC
D3
R4
R2
R3
TXD
D2
D1
LTC1543
LTC1544
D4
SCTE
D2
D3
D1
R3
R1
R2
R1
LTC1344A
18
13 5
22 6
10 8
23 20 19 4
1
7
16 3
17
12 15 11 24 14
2
TXD A (103)
TXD B
SCTE A (113)
TXC A (114)
SCTE B
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
SG (102)
SHIELD (101)
RTS A (105)
RTS B
DTR A (108)
DCD A (109)
DTR B
DCD B
DSR A (107)
CTS A (106)
DSR B
CTS B
LL A (141)
DB-25 CONNECTOR
9
1543 TA01
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LTC1543
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage ....................................................... 6.5V
Input Voltage
Transmitters ........................... – 0.3V to (VCC + 0.3V)
Receivers ............................................... – 18V to 18V
Logic Pins .............................. – 0.3V to (VCC + 0.3V)
Output Voltage
Transmitters ................. (VEE – 0.3V) to (VDD + 0.3V)
Receivers ................................ – 0.3V to (VCC + 0.3V)
Logic Pins .............................. – 0.3V to (VCC + 0.3V)
VEE ........................................................ – 10V to 0.3V
VDD ....................................................... – 0.3V to 10V
Short-Circuit Duration
Transmitter Output ..................................... Indefinite
Receiver Output .......................................... Indefinite
VEE .................................................................. 30 sec
Operating Temperature Range
LTC1543C .............................................. 0°C to 70°C
LTC1543I ........................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ELECTRICAL CHARACTERISTICS
ORDER PART
NUMBER
TOP VIEW
C1–
1
C1+
2
VDD
3
VCC
4
D1
5
D2
6
28 C2
+
27 C2 –
CHARGE PUMP
26 VEE
LTC1543CG
LTC1543IG
25 GND
24 D1 A
D1
D3
7
R1
8
R2
9
23 D1 B
D2
22 D2 A
21 D2 B
D3
20 D3/R1 A
R3 10
19 D3/R1 B
R1
18 R2 A
M0 11
R2
M1 12
M2 13
17 R2 B
16 R3 A
R3
15 R3 B
DCE/DTE 14
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 90°C/ W
Consult LTC Marketing for parts specified with wider operating
temperature ranges.
The ● denotes specifications which apply over the full operating tempera-
ture range. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
VCC Supply Current (DCE Mode,
All Digital Pins = GND or VCC)
RS530, RS530-A, X.21 Modes, No Load
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode, No Load
V.35 Mode, Full Load
V.28 Mode, No Load
V.28 Mode, Full Load
No-Cable Mode
MIN
TYP
MAX
UNITS
Supplies
ICC
PD
Internal Power Dissipation (DCE Mode)
RS530, RS530-A, X.21 Modes, Full Load
V.35 Mode, Full Load
V.28 Mode, Full Load
V+
Positive Charge Pump Output Voltage
Any Mode, No Load
V.28 Mode, with Load
V.28 Mode, with Load, IDD = 10mA
V–
Negative Charge Pump Output Voltage
V.28, V.35 Modes, No Load
V.28 Mode, Full Load
V.35 Mode, Full Load
RS530, RS530-A, X.21 Modes, Full Load
fOSC
Charge Pump Oscillator Frequency
tr
Supply Rise Time
13
100
20
126
20
40
120
●
●
●
●
●
●
8.0
8.0
●
●
●
– 8.0
– 5.5
– 4.5
No-Cable Mode or Power-Up to Turn On
130
170
75
500
mA
mA
mA
mA
mA
mA
µA
230
600
140
mW
mW
mW
9.4
8.7
6.5
V
V
V
– 9.6
– 8.5
– 6.7
– 5.7
V
V
V
V
150
kHz
2
ms
Logic Inputs and Outputs
VIH
Logic Input High Voltage
●
VIL
Logic Input Low Voltage
●
2
V
0.8
V
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LTC1543
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating tempera-
ture range. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
IIN
Logic Input Current
D1, D2, D3
M0, M1, M2, DCE = GND (LTC1543C)
M0, M1, M2, DCE = GND (LTC1543I)
M0, M1, M2, DCE = VCC
●
●
●
●
MIN
VOH
Output High Voltage
IO = – 4mA
●
VOL
Output Low Voltage
IO = 4mA
●
IOSR
Output Short-Circuit Current
0V ≤ VO ≤ VCC
●
IOZR
Three-State Output Current
M0 = M1 = M2 = VCC, 0V ≤ VO ≤ VCC
VODO
Open Circuit Differential Output Voltage
RL = 1.95k (Figure 1)
●
VODL
Loaded Differential Output Voltage
RL = 50Ω (Figure 1)
RL = 50Ω (Figure 1)
●
TYP
MAX
UNITS
– 100
– 120
– 50
– 50
±10
– 30
– 30
±10
µA
µA
µA
µA
3
4.5
0.3
– 50
V
0.8
V
50
mA
±1
µA
V.11 Driver
0.5VODO
±2
±5
V
0.67VODO
V
V
∆VOD
Change in Magnitude of Differential
Output Voltage
RL = 50Ω (Figure 1)
●
0.2
V
VOC
Common Mode Output Voltage
RL = 50Ω (Figure 1)
●
3
V
∆VOC
Change in Magnitude of Common Mode
Output Voltage
RL = 50Ω (Figure 1)
●
0.2
V
ISS
Short-Circuit Current
VOUT = GND
IOZ
Output Leakage Current
– 0.25V ≤ VO ≤ 0.25V, Power Off or
No-Cable Mode or Driver Disabled
●
t r, t f
Rise or Fall Time
(Figures 2, 6) (LTC1543C)
(Figures 2, 6) (LTC1543I)
●
●
t PLH
Input to Output
(Figures 2, 6) (LTC1543C)
(Figures 2, 6) (LTC1543I)
t PHL
Input to Output
∆t
t SKEW
150
mA
±1
±100
µA
2
2
15
15
25
35
ns
ns
●
●
20
20
40
40
65
75
ns
ns
(Figures 2, 6) (LTC1543C)
(Figures 2, 6) (LTC1543I)
●
●
20
20
40
40
65
75
ns
ns
Input to Output Difference, tPLH – tPHL
(Figures 2, 6) (LTC1543C)
(Figures 2, 6) (LTC1543I)
●
●
0
0
3
3
12
17
ns
ns
Output to Output Skew
(Figures 2, 6)
3
ns
V.11 Receiver
VTH
Input Threshold Voltage
– 7V ≤ VCM ≤ 7V
●
∆VTH
Input Hysteresis
– 7V ≤ VCM ≤ 7V
●
IIN
Input Current (A, B)
– 10V ≤ VA,B ≤ 10V
●
RIN
Input Impedance
– 10V ≤ VA,B ≤ 10V
●
t r, t f
Rise or Fall Time
(Figures 2, 7)
t PLH
Input to Output
(Figures 2, 7) (LTC1543C)
(Figures 2, 7) (LTC1543I)
●
●
50
50
80
90
ns
ns
t PHL
Input to Output
(Figures 2, 7) (LTC1543C)
(Figures 2, 7) (LTC1543I)
●
●
50
50
80
90
ns
ns
∆t
Input to Output Difference, tPLH – tPHL
(Figures 2, 7) (LTC1543C)
(Figures 2, 7) (LTC1543I)
●
●
0
0
4
4
16
21
ns
ns
V
V
– 0.2
15
15
0.2
V
40
mV
±0.66
mA
30
kΩ
15
ns
V.35 Driver
VOD
Differential Output Voltage
Open Circuit
With Load, – 4V ≤ VCM ≤ 4V (Figure 3)
●
●
±0.44
±0.55
±10.00
±0.66
IOH
Transmitter Output High Current
VA, B = 0V
●
– 13
– 11
– 9.0
mA
IOL
Transmitter Output Low Current
VA, B = 0V
●
9.0
11
13
mA
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LTC1543
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating tempera-
ture range. VCC = 5V (Notes 2, 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
IOZ
Transmitter Output Leakage Current
– 0.25V ≤ VA, B ≤ 0.25V
tr, tf
Rise or Fall Time
(Figures 3, 6)
t PLH
Input to Output
(Figures 3, 6) (LTC1543C)
(Figures 3, 6) (LTC1543I)
●
●
20
20
35
35
65
75
ns
ns
t PHL
Input to Output
(Figures 3, 6) (LTC1543C)
(Figures 3, 6) (LTC1543I)
●
●
20
20
35
35
65
75
ns
ns
∆t
Input to Output Difference, tPLH – tPHL
(Figures 3, 6) (LTC1543C)
(Figures 3, 6) (LTC1543I)
●
●
0
0
4
4
16
21
ns
ns
t SKEW
Output to Output Skew
(Figures 3, 6)
●
TYP
MAX
UNITS
±1
±100
µA
5
ns
4
ns
V.35 Receiver
VTH
Differential Receiver Input Threshold Voltage
– 2V ≤ (VA + VB)/2 ≤ 2V (Figure 3)
●
∆VTH
Receiver Input Hysteresis
– 2V ≤ (VA + VB)/2 ≤ 2V (Figure 3)
●
IIN
Receiver Input Current (A, B)
– 10V ≤ VA,B ≤ 10V
●
RIN
Receiver Input Impedance
– 10V ≤ VA,B ≤ 10V
●
t r, t f
Rise or Fall Time
(Figures 3, 7)
tPLH
Input to Output
(Figures 3, 7) (LTC1543C)
(Figures 3, 7) (LTC1543I)
●
●
50
50
80
90
ns
ns
tPHL
Input to Output
(Figures 3, 7) (LTC1543C)
(Figures 3, 7) (LTC1543I)
●
●
50
50
80
90
ns
ns
∆t
Input to Output Difference, tPLH – tPHL
(Figures 3, 7) (LTC1543C)
(Figures 3, 7) (LTC1543I)
●
●
0
0
4
4
16
21
ns
ns
VO
Output Voltage
Open Circuit
RL = 3k (Figure 4)
●
●
±5
±8.5
±10
V
V
ISS
Short-Circuit Current
VOUT = GND
●
±150
mA
IOZ
Output Leakage Current
– 0.25V ≤ VO ≤ 0.25V, Power Off or
No-Cable Mode or Driver Disabled
●
±1
±100
µA
SR
Slew Rate
RL = 3k, CL = 2500pF (Figures 4, 8)
●
30
V/µs
t PLH
Input to Output
RL = 3k, CL = 2500pF (Figures 4, 8)
●
1.5
2.5
µs
t PHL
Input to Output
RL = 3k, CL = 2500pF (Figures 4, 8)
●
1.5
3
µs
1.2
0.8
V
– 0.2
0.2
15
15
V
40
mV
±0.66
mA
30
kΩ
15
ns
V.28 Driver
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V.28 Receiver
VTHL
Input Low Threshold Voltage
●
VTLH
Input High Threshold Voltage
●
2
1.2
∆VTH
Receiver Input Hysteresis
●
0
0.05
0.3
RIN
Receiver Input Impedance
– 15V ≤ VA ≤ 15V
●
3
5
7
t r, tf
tPLH
Rise or Fall Time
(Figures 5, 9)
Input to Output
(Figures 5, 9)
●
60
100
ns
tPHL
Input to Output
(Figures 5, 9)
●
160
250
ns
Note 1: Absolute Maximum Ratings are those beyond which the safety of a
device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.
V
V
kΩ
15
ns
Note 3: All typicals are given for VCC = 5V, C1 = C2 = CVCC = 1µF,
CVDD = CVEE = 3.3µF tantalum capacitors and TA = 25°C.
sn1534 1543fas
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LTC1543
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C1 –␣ (Pin 1): Capacitor C1 Negative Terminal. Connect a
1µF capacitor between C1+ and C1–.
R3 B (Pin 15): Receiver 3 Noninverting Input with Pull-Up
to VCC.
C1 + (Pin 2): Capacitor C1 Positive Terminal. Connect a
1µF capacitor between C1 + and C1 –.
R3 A (Pin 16): Receiver 3 Inverting Input.
VDD (Pin 3): Generated Positive Supply Voltage for
V.28. Connect a 1µF capacitor to ground.
R2 A (Pin 18): Receiver 2 Inverting Input.
VCC (Pin 4): Positive Supply Voltage Input. 4.75V ≤ VCC
≤ 5.25V. Bypass with a 1µF capacitor to ground.
D1 (Pin 5): TTL Level Driver 1 Input.
D2 (Pin 6): TTL Level Driver 2 Input.
R2 B (Pin 17): Receiver 2 Noninverting Input.
D3/R1 B (Pin 19): Receiver 1 Noninverting Input and
Driver 3 Noninverting Output.
D3/R1 A (Pin 20): Receiver 1 Inverting Input and Driver 3
Inverting Output.
D2 B (Pin 21): Driver 2 Noninverting Output.
D3 (Pin 7): TTL Level Driver 3 Input.
D2 A (Pin 22): Driver 2 Inverting Output.
R1 (Pin 8): CMOS Level Receiver 1 Output.
R2 (Pin 9): CMOS Level Receiver 2 Output.
R3 (Pin 10): CMOS Level Receiver 3 Output.
D1 B (Pin 23): Driver 1 Noninverting Output.
D1 A (Pin 24): Driver 1 Inverting Output.
GND (Pin 25): Ground.
M0 (Pin 11): TTL Level Mode Select Input 0 with Pull-Up
to VCC.
VEE (Pin 26): Negative Supply Voltage. Connect a 3.3µF
capacitor to GND.
M1 (Pin 12): TTL Level Mode Select Input 1 with Pull-Up
to VCC.
C2 – (Pin 27): Capacitor C2 Negative Terminal. Connect a
1µF capacitor between C2 + and C2 –.
M2 (Pin 13): TTL Level Mode Select Input 2 with Pull-Up
to VCC.
C2 + (Pin 28): Capacitor C2 Positive Terminal. Connect a
1µF capacitor between C2 + and C2 – .
DCE/DTE (Pin 14): TTL Level Mode Select Input with PullUp to VCC.
TEST CIRCUITS
A
RL
50Ω
B
VOD
A
RL
50Ω
B
RL
100Ω
CL
100pF
B
CL
100pF
A
R
VOC
1543 F01
Figure 1. V.11 Driver Test Circuit
15pF
1543 F02
Figure 2. V.11 Driver/Receiver AC Test Circuit
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LTC1543
TEST CIRCUITS
50Ω
D
B
VCM
125Ω
50Ω
B
125Ω
R
VOD
A
A
50Ω
15pF
50Ω
1543 F03
Figure 3. V.35 Driver/Receiver Test Circuit
D
A
D
A
A
R
RL
CL
15pF
1543 F04
1543 F04
Figure 5. V.10/V.28 Receiver Test Circuit
Figure 4. V.10/V.28 Driver Test Circuit
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ODE SELECTIO
LTC1543 MODE NAME
M2
M1
M0
DCE/DTE
D1
D2
D3
R1
R2
R3
Not Used (Default V.11)
0
0
0
0
V.11
V.11
Z
V.11
V.11
V.11
RS530A
0
0
1
0
V.11
V.11
Z
V.11
V.11
V.11
RS530
0
1
0
0
V.11
V.11
Z
V.11
V.11
V.11
X.21
0
1
1
0
V.11
V.11
Z
V.11
V.11
V.11
V.35
1
0
0
0
V.35
V.35
Z
V.35
V.35
V.35
RS449/V.36
1
0
1
0
V.11
V.11
Z
V.11
V.11
V.11
V.28/RS232
1
1
0
0
V.28
V.28
Z
V.28
V.28
V.28
No Cable
1
1
1
0
Z
Z
Z
Z
Z
Z
Not Used (Default V.11)
0
0
0
1
V.11
V.11
V.11
Z
V.11
V.11
RS530A
0
0
1
1
V.11
V.11
V.11
Z
V.11
V.11
RS530
0
1
0
1
V.11
V.11
V.11
Z
V.11
V.11
X.21
0
1
1
1
V.11
V.11
V.11
Z
V.11
V.11
V.35
1
0
0
1
V.35
V.35
V.35
Z
V.35
V.35
RS449/V.36
1
0
1
1
V.11
V.11
V.11
Z
V.11
V.11
V.28/RS232
1
1
0
1
V.28
V.28
V.28
Z
V.28
V.28
No Cable
1
1
1
1
Z
Z
Z
Z
Z
Z
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LTC1543
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SWITCHI G TI E WAVEFOR S
5V
f = 1MHz : t r ≤ 10ns : t f ≤ 10ns
1.5V
D
0V
1.5V
t PHL
t PLH
VO
B–A
–VO
90%
50%
90%
VDIFF = V(A) – V(B)
10%
1/2 VO
tr
50%
10%
tf
A
VO
B
t SKEW
t SKEW
1543 F06
Figure 6. V.11, V.35 Driver Propagation Delays
VOD2
B–A
–VOD2
f = 1MHz : t r ≤ 10ns : t f ≤ 10ns
0V
INPUT
0V
t PHL
t PLH
VOH
R
VOL
OUTPUT
1.5V
1.5V
1543 F07
Figure 7. V.11, V.35 Receiver Propagation Delays
3V
1.5V
1.5V
D
0V
t PHL
VO
t PLH
3V
3V
0V
A
0V
–3V
–VO
1543 F08
–3V
tf
tr
Figure 8. V.10, V.28 Driver Propagation Delays
VIH
1.7V
1.3V
A
VIL
VOH
R
VOL
t PHL
t PLH
2.4V
0.8V
1543 F09
Figure 9. V.10, V.28 Receiver Propagation Delays
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LTC1543
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APPLICATIO S I FOR ATIO
Overview
The LTC1543/LTC1544 form the core of a complete software-selectable DTE or DCE interface port that supports
the RS232, RS449, EIA530, EIA530-A, V.35, V.36 or X.21
protocols. Cable termination may be implemented using
the LTC1344A software-selectable cable termination chip
or by using existing discrete designs.
A complete DCE-to-DTE interface operating in EIA530
mode is shown in Figure 10. The LTC1543 of each port is
used to generate the clock and data signals. The LTC1544
is used to generate the control signals along with LL (Local
Loopback).The LTC1344A cable termination chip is used
only for the clock and data signals because they must
support V.35 cable termination. The control signals do not
need any external resistors.
Mode Selection
The interface protocol is selected using the mode select
pins M0, M1 and M2 (see the Mode Selection table).
For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.
For the control signals, the drivers and receivers will
operate in V.28 (RS232) electrical mode. For the clock and
data signals, the drivers and receivers will operate in V.35
electrical mode. The DCE/DTE pin will configure the port
for DCE mode when high, and DTE when low.
The interface protocol may be selected simply by plugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable as shown in
Figure 11.
The internal pull-up current sources will ensure a binary 1
when a pin is left unconnected and that the LTC1543/
LTC1544 and the LTC1344A enter the no-cable mode
when the cable is removed. In the no-cable mode the
LTC1543/LTC1544 supply current drops to less than
200µA and all LTC1543/LTC1544 driver outputs and
LTC1344A resistive terminations are forced into a high
impedance state.
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or VCC.
Cable Termination
Traditional implementations have included switching
resistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head or separate terminations are built on the board and a custom cable routes the
signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
Using the LTC1344A along with the LTC1543/LTC1544
solves the cable termination switching problem. Via software control, the LTC1344A provides termination for the
V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35
electrical protocols.
V.10 (RS423) Interface
A typical V.10 unbalanced interface is shown in Figure 12.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' connected to A, and input C' connected to the signal return
ground C. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 13.
The V.10 receiver configuration in the LTC1544 is shown
in Figure 14. In V.10 mode switch S3 inside the LTC1544
is turned off.The noninverting input is disconnected inside
the LTC1544 receiver and connected to ground. The cable
termination is then the 30k input impedance to ground of
the LTC1544 V.10 receiver.
sn1534 1543fas
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LTC1543
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APPLICATIO S I FOR ATIO
DTE
SERIAL
CONTROLLER
LTC1543
DCE
LTC1344A
LTC1344A
LTC1543
SERIAL
CONTROLLER
TXD
D1
TXD
103Ω
R3
TXD
SCTE
D2
SCTE
103Ω
R2
SCTE
R1
D3
TXC
R1
103Ω
TXC
D3
TXC
RXC
R2
103Ω
RXC
D2
RXC
RXD
R3
103Ω
RXD
D1
RXD
LTC1544
LTC1544
RTS
D1
RTS
R3
RTS
DTR
D2
DTR
R2
DTR
D3
R1
DCD
R1
DCD
D3
DCD
DSR
R2
DSR
D2
DSR
CTS
R3
CTS
D1
CTS
LL
LL
D4
R4
R4
LL
D4
1543 F10
Figure 10. Complete Multiprotocol Interface in EIA530 Mode
sn1534 1543fas
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LATCH
21
LTC1344A
DCE/
DTE M2
22
M1 M0 (DATA)
23
24
1
CONNECTOR
(DATA)
M0
LTC1543
M1
M2
DCE/DTE
11
12
13
NC
14
NC
CABLE
LTC1544
DCE/DTE
M2
M1
M0
14
13
12
11
1543 F11
(DATA)
Figure 11. Single Port DCE V.35 Mode Selection in the Cable
BALANCED
INTERCONNECTING
CABLE
GENERATOR
LOAD
CABLE
TERMINATION
A
A'
C
C'
RECEIVER
1543 F12
Figure 12. Typical V.10 Interface
sn1534 1543fas
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IZ
3.25mA
A'
A
LTC1544
R8
6k
–10V
R5
20k
R6
10k
–3V
S3
VZ
3V
RECEIVER
10V
B
B'
C'
1543 F13
R7
10k
R4
20k
GND
1543 F14
–3.25mA
Figure 14. V.10 Receiver Configuration
Figure 13. V.10 Receiver Input Impedance
GENERATOR
V.11 (RS422) Interface
A typical V.11 balanced interface is shown in Figure 15. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.11 interface has a differential termination at the receiver
end that has a minimum value of 100Ω. The termination
resistor is optional in the V.11 specification, but for the
high speed clock and data lines, the termination is required
to prevent reflections from corrupting the data. The
receiver inputs must also be compliant with the impedance curve shown in Figure 13.
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
A
A'
B
B'
C
C'
RECEIVER
100Ω
MIN
1543 F15
Figure 15. Typical V.11 Interface
A'
A
In V.11 mode, all switches are off except S1 inside the
LTC1344A which connects a 103Ω differential termination impedance to the cable as shown in Figure 16.
R1
51.5Ω
LTC1344A
R8
6k
LTC1543
LTC1544
R5
20k
R6
10k
S1
S2
R2
51.5Ω
RECEIVER
S3
R3
124Ω
R4
20k
B
R7
10k
B'
C'
GND
1543 F16
Figure 16. V.11 Receiver Configuration
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V.28 (RS232) Interface
V.35 Interface
A typical V.28 unbalanced interface is shown in Figure 17.
A V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with input A' connected to A, ground C' connected via the signal return
ground C.
A typical V.35 balanced interface is shown in Figure 19. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T or delta network termination at
the receiver end and the generator end. The receiver
differential impedance measured at the connector must be
100Ω␣ ±10Ω, and the impedance between shorted terminals (A' and B') and ground C' must be 150Ω ±15Ω.
In V.28 mode all switches are off except S3 inside the
LTC1543/LTC1544 which connects a 6k (R8) impedance
to ground in parallel with 20k (R5) plus 10k (R6) for a
combined impedance of 5k as shown in Figure 18. The
noninverting input is disconnected inside the LTC1543/
LTC1544 receiver and connected to a TTL level reference
voltage for a 1.4V receiver trip point.
BALANCED
INTERCONNECTING
CABLE
GENERATOR
In V.35 mode, both switches S1 and S2 inside the LTC1344A
are on, connecting the T network impedance as shown in
Figure 20. The switch in the LTC1543 is off. The 30k input
GENERATOR
LOAD
CABLE
TERMINATION
BALANCED
INTERCONNECTING
CABLE
RECEIVER
50Ω
C'
C
125Ω
125Ω
50Ω
1543 F17
RECEIVER
A'
A
A'
A
LOAD
CABLE
TERMINATION
50Ω
50Ω
B
B'
C
C'
Figure 17. Typical V.28 Interface
1543 F19
Figure 19. Typical V.35 Interface
A'
A
R1
51.5Ω
S1
S2
R2
51.5Ω
LTC1344A
R8
6k
A'
A
R6
10k
S3
R3
124Ω
LTC1543
LTC1544
R5
20k
RECEIVER
R1
51.5Ω
LTC1543
R8
6k
R5
20k
R6
10k
R4
20k
B
S1
R7
10k
S2
R2
51.5Ω
B'
C'
LTC1344A
GND
1543 F18
RECEIVER
S3
R3
124Ω
R4
20k
B
R7
10k
B'
Figure 18. V.28 Receiver Configuration
C'
GND
1543 F20
Figure 20. V.35 Receiver Configuration
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APPLICATIO S I FOR ATIO
impedance of the receiver is placed in parallel with the T
network termination, but does not affect the overall input
impedance significantly.
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals (A
and B) and ground C must be 150Ω ±15Ω. For the
generator termination, switches S1 and S2 are both on and
the top side of the center resistor is brought out to a pin so
it can be bypassed with an external capacitor to reduce
common mode noise as shown in Figure 21.
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground, causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable.
No-Cable Mode
The no-cable mode (M0 = M1 = M2 = 1) is intended for the
case when the cable is disconnected from the connector.
The charge pump, bias circuitry, drivers and receivers are
turned off, the driver outputs are forced into a high
impedance state, and the supply current drops to less than
200µA.
Charge Pump
The LTC1543 uses an internal capacitive charge pump to
generate VDD and VEE as shown in Figure 22. A voltage
doubler generates about 8V on VDD and a voltage inverter
generates about – 7.5V for VEE. Four 1µF surface mounted
tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The VEE capacitor C5 should be a minimum of
3.3µF. All capacitors are 16V and should be placed as close
as possible to the LTC1543 to reduce EMI.
Receiver Fail-Safe
A
LTC1344A
V.35 DRIVER
124Ω
51.5Ω
S2
ON
S1
ON
All LTC1543/LTC1544 receivers feature fail-safe operation in all modes. If the receiver inputs are left floating or
shorted together by a termination resistor, the receiver
output will always be forced to a logic high.
51.5Ω
3
B
C1
100pF
C3
1µF
C
2
C1
1µF 1
1543 F21
Figure 21. V.35 Driver Using the LTC1344A
4
5V
VDD
C2 +
28
C1+
C2 –
27
C2
1µF
LTC1543
C1–
VCC
VEE
GND
26
25
+
C5
3.3µF
C4
1µF
1543 F22
Figure 22. Charge Pump
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DTE vs DCE Operation
The DCE/DTE pin acts as an enable for Driver 3/Receiver
1 in the LTC1543, and Driver 3/Receiver 1 and Driver 4/
Receiver 4 in the LTC1544. The INVERT pin in the LTC1544
allows the Driver 4/Receiver 4 enable to be high or low true
polarity.
The LTC1543/LTC1544 can be configured for either DTE
or DCE operation in one of two ways: a dedicated DTE or
DCE port with a connector of appropriate gender or a port
with one connector that can be configured for DTE or DCE
operation by rerouting the signals to the LTC1543/LTC1544
using a dedicated DTE cable or dedicated DCE cable.
A dedicated DTE port using a DB-25 male connector is
shown in Figure 23. The interface mode is selected by logic
outputs from the controller or from jumpers to either VCC
or GND on the mode select pins. A dedicated DCE port
using a DB-25 female connector is shown in Figure 24.
A port with one DB-25 connector, but can be configured
for either DTE or DCE operation is shown in Figure 25. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. For example, in DTE
mode, the TXD signal is routed to Pins 2 and 14 via Driver
1 in the LTC1543. In DCE mode, Driver 1 now routes the
RXD signal to Pins 2 and 14.
Multiprotocol Interface with RL, LL, TM and a DB-25
Connector
If the RL, LL and TM signals are implemented, there are not
enough drivers and receivers available in the LTC1543/
LTC1544. In Figure 26, the required control signals are
handled by the LTC1544 but the clock/data signals use the
LTC1343. The LTC1343 has an additional single-ended
driver/receiver pair that can handle two more optional
control signals such as TM and LL.
Cable-Selectable Multiprotocol Interface
A cable-selectable multiprotocol DTE/DCE interface is
shown in Figure 27. The select lines M0, M1 and DCE/DTE
are brought out to the connector. The mode is selected by
the cable by wiring M0 (connector Pin 18) and M1 (connector Pin 21) and DCE/DTE (connector Pin 25) to ground
(connector Pin 7) or letting them float. If M0, M1 or DCE/
DTE is floating, internal pull-up current sources will pull
the signals to VCC. The select bit M2 is hard wired to VCC.
When the cable is pulled out, the interface will go into the
no-cable mode.
Compliance Testing
A European standard EN 45001 test report is available for
the LTC1543/LTC1544/LTC1344A chipset. A copy of the
test report is available from LTC or TUV Telecom Services
Inc. (formerly Detecon Inc.)
The title of the report is:
Test Report No. NET2/102201/97.
The address of TUV Telecom Services Inc. is:
TUV Telecom Services Inc.
Type Approval Division
1775 Old Highway 8, Ste 107
St. Paul, MN 55112 USA
Tel. +1 (612) 639-0775
Fax. +1 (612) 639-0873
sn1534 1543fas
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TYPICAL APPLICATIO S
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
CHARGE
PUMP
2
4
25
C5
1µF
LTC1543
5
TXD
D1
6
SCTE
D2
7
11
12
13
14
C9
1µF
RTS
DTR
R2
10
RXD
C10
1µF
R1
9
RXC
R3
CTS
LL
24
2
23
14
22
24
21
11
20
15
19
12
18
17
17
9
16
3
15
16
1
VEE
GND
D1
D2
TXD A (103)
TXD B
SCTE A (113)
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
SG
SHIELD
DB-25 MALE
CONNECTOR
28
C11
1µF
27
26
4
25
19
24
20
23
23
RTS A (105)
RTS B
DTR A (108)
DTR B
D3
6
R1
7
R2
8
R3
10
R4
9
14
16 15 18 17 19 20 22 23 24 1
DCE/DTE
4
13
9 10
M2
3
12
5 4 6 7
M1
VCC
1
VCC
2
VDD
11
VEE
C12
1µF
7
LTC1544
DSR
2
C4
3.3µF
M0
5
DCD
C2
1µF
D3
8
TXC
21
M0
27
26
M1
1
LATCH
M2
28
VCC
DCE/DTE
C1
1µF
3
+
C3
1µF
C13
1µF
22
8
21
10
20
6
19
22
18
5
17
13
16
18
DCD A (109)
DCD B
DSR A (107)
DSR B
CTS A (106)
CTS B
LL A (141)
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
M2
M1
M0
1543 F23
Figure 23. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
sn1534 1543fas
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LTC1543
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TYPICAL APPLICATIO S
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
4
25
C5
1µF
LTC1543
5
RXD
RXC
D2
7
R2
10
TXD
11
12
13
NC
C10
1µF
R1
9
SCTE
14
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
VCC
3
23
16
22
17
21
9
R3
20
15
19
12
18
24
17
11
16
2
15
14
M0
7
M1
M2
1
DCE/DTE
1
VCC
2
VDD
3
CTS
VEE
GND
D1
4
DSR
D2
5
LTC1544
R1
7
DTR
R2
8
RTS
R3
10
LL
R4
9
11
12
13
NC
14
RXC A (115)
RXC B
TXC A (114)
TXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
SGND (102)
SHIELD (101)
28
C11
1µF
27
26
5
25
13
24
6
23
22
CTS A (106)
CTS B
DSR A (107)
DSR B
D3
6
DCD
RXD B
DB-25 FEMALE
CONNECTOR
VCC
C9
1µF
RXD A (104)
D3
8
TXC
VEE
C12
1µF
24
D1
6
2
C4
3.3µF
M0
CHARGE
PUMP
2
21
C2
1µF
M1
27
26
LATCH
M2
1
VCC
DCE/DTE
C1
1µF
28
+
C3
1µF
3
C13
1µF
22
8
21
10
20
20
19
23
18
4
17
19
16
18
DCD A (109)
DCD B
DTR A (108)
DTR B
RTS A (105)
RTS B
LL A (141)
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
M2
M1
M0
1543 F24
Figure 24. Controller-Selectable DCE Port with DB-25 Connector
sn1534 1543fas
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LTC1543
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TYPICAL APPLICATIO S
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
4
25
C5
1µF
LTC1543
5
DTE_TXD/DCE_RXD
D1
6
DTE_SCTE/DCE_RXC
D2
7
S
R1
S
9
DTE_RXC/DCE_SCTE
R2
10
DTE_RXD/DCE_TXD
11
12
VEE
C12
1µF
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
24
2
23
14
22
24
21
11
R3
20
15
19
12
18
17
17
9
16
3
15
16
M0
7
M1
13
M2
14
DCE/DTE
C10
1µF
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
C9
1µF
1
1
VCC
2
VDD
3
VEE
GND
D1
4
D2
DTE_CTS/DCE_RTS
DTE_LL/DCE_LL
TXD B
RXD B
SCTE A
RXC A
SCTE B
RXC B
TXC A
TXC A
TXC B
TXC B
RXC A
SCTE A
RXC B
SCTE B
RXD A
TXD A
RXD B
TXD B
SG
SHIELD
DB-25
CONNECTOR
6
R1
7
R2
8
R3
10
R4
9
11
12
13
14
28
C11
1µF
27
26
4
25
19
24
20
23
23
RTS A
CTS A
RTS B
CTS B
DTR A
DSR A
DTR B
DSR B
DCD A
DCD A
D3
LTC1544
DTE_DSR/DCE_DTR
DCE
RXD A
VCC
5
DTE_DCD/DCE_DCD
DTE
TXD A
D3
8
DTE_TXC/DCE_TXC
2
C4
3.3µF
M0
CHARGE
PUMP
2
21
C2
1µF
M1
27
26
LATCH
M2
1
VCC
DCE/DTE
C1
1µF
28
+
C3
1µF
3
C13
1µF
22
8
21
10
20
6
19
22
18
5
17
13
16
18
DCD B
DCD B
DSR A
DTR A
DSR B
DTR B
CTS A
RTS A
CTS B
RTS B
LL A
LL A
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
DCE/DTE
M2
M1
M0
1543 F25
Figure 25. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
sn1534 1543fas
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TYPICAL APPLICATIO S
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
44
C5
1µF
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
LTC1343
D1
D2
7
DTE_SCTE/DCE_RXC
VEE
C12
1µF
8
6
DTE_TXD/DCE_RXD
C4
3.3µF
M0
41
5
DTE_LL/DCE_TM
2
42
CHARGE
PUMP
21
C2
1µF
43
4
3
LATCH
M1
C1
1µF
VCC
M2
2
+
C3
1µF
C13
1µF
DCE/DTE
1
D3
39
18
38
2
37
14
36
24
35
11
DTE
DCE
LL A
TM A
TXD A
RXD A
TXD B
RXD B
SCTE A
RXC A
SCTE B
RXC B
TXC A
TXC A
34
9
DTE_TXC/DCE_TXC
R1
14
DTE_RXC/DCE_SCTE
R2
15
DTE_RXD/DCE_TXD
R3
16
DTE_TM/DCE_LL
20
22
11
25
R1
100k
33
D4
10
12
13
R4
CTRL
DCE
LATCH
M2
INVERT
M1
423SET
M0
GND
EC
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
LB
DTE_CTS/DCE_RTS
DTE_RL/DCE_RL
C9
1µF
VCC
1
VCC
2
VDD
3
VEE
GND
D1
4
D2
17
29
9
28
3
27
16
26
25
21
7
19
1
18
TXC B
RXC A
SCTE A
RXC B
SCTE B
RXD A
TXD A
RXD B
TXD B
TM A
LL A
SG
SHIELD
17
24
6
R1
7
R2
8
R3
10
11
12
13
14
28
C11
1µF
27
26
4
25
19
24
20
23
23
RTS A
CTS A
RTS B
CTS B
DTR A
DSR A
DTR B
DSR B
DCD A
DCD A
D3
R4
9
DCE/DTE
M2
M1
M0
30
TXC B
DB-25
CONNECTOR
LTC1544
DTE_DSR/DCE_DTR
12
23
5
DTE_DCD/DCE_DCD
15
31
VCC
40
LB
C10
1µF
32
22
8
21
10
20
6
19
22
18
5
17
13
16
21
DCD B
DCD B
DSR A
DTR A
DSR B
DTR B
CTS A
RTS A
CTS B
RTS B
RL A
RL A
D4
M0
INVERT
15
NC
M1
M2
DCE/DTE
1543 F26
Figure 26. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and DB-25 Connector
sn1534 1543fas
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TYPICAL APPLICATIO S
C6
C7
C8
100pF 100pF 100pF
3
8
11
12
13
LTC1344A
VCC
5V
14
4
25
C5
1µF
LTC1543
5
DTE_TXD/DCE_RXD
D2
7
R1
9
DTE_RXC/DCE_SCTE
R2
10
DTE_RXD/DCE_TXD
11
12
NC
13
14
5 4 6 7
9 10
16 15 18 17 19 20 22 23 24 1
VCC
2
23
14
22
24
21
11
DTE
DCE
TXD A
RXD A
TXD B
RXD B
SCTE A
RXC A
SCTE B
RXC B
TXC A
TXC A
TXC B
TXC B
RXC A
SCTE A
RXC B
SCTE B
RXD A
TXD A
RXD B
TXD B
D3
8
DTE_TXC/DCE_TXC
VEE
C12
1µF
24
D1
6
DTE_SCTE/DCE_RXC
2
C4
3.3µF
M0
CHARGE
PUMP
2
21
C2
1µF
M1
27
26
LATCH
M2
1
VCC
DCE/DTE
C1
1µF
28
+
C3
1µF
3
C13
1µF
R3
20
15
19
12
18
17
17
9
16
3
15
16
M0
7
M1
M2
1
DCE/DTE
SG
SHIELD
DB-25
CONNECTOR
C10
1µF
C9
1µF
VCC
1
VCC
2
VDD
VEE
GND
25
DCE/DTE
21
M1
18
M0
4
RTS A
19
RTS B
20
DTR A
23
DTR B
28
C11
1µF
27
26
3
DTE_RTS/DCE_CTS
D1
24
4
DTE_DTR/DCE_DSR
D2
5
LTC1544
R1
7
DTE_DSR/DCE_DTR
R2
8
DTE_CTS/DCE_RTS
R3
10
R4
9
11
12
NC
13
14
23
CTS A
CTS B
DSR A
DSR B
D3
6
DTE_DCD/DCE_DCD
25
22
8
21
10
20
6
19
22
18
5
17
13
CABLE WIRING FOR MODE SELECTION
MODE
V.35
RS449, V.36
RS232
M0
M1
DCE/DTE INVERT
DCD A
DCD B
DCD B
DSR A
DTR A
DSR B
DTR B
CTS A
RTS A
CTS B
RTS B
16
D4
M2
DCD A
15
PIN 18
PIN 7
NC
PIN 7
PIN 21
PIN 7
PIN 7
NC
CABLE WIRING FOR
DTE/DCE SELECTION
MODE
PIN 25
DTE
PIN 7
DCE
NC
NC
1543/44 F27
Figure 27. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
sn1534 1543fas
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1543
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 – 0.407*
(10.07 – 10.33)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.301 – 0.311
(7.65 – 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.205 – 0.212**
(5.20 – 5.38)
0.068 – 0.078
(1.73 – 1.99)
0° – 8°
0.005 – 0.009
(0.13 – 0.22)
0.0256
(0.65)
BSC
0.022 – 0.037
(0.55 – 0.95)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.002 – 0.008
(0.05 – 0.21)
0.010 – 0.015
(0.25 – 0.38)
G28 SSOP 0694
RELATED PARTS
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DESCRIPTION
COMMENTS
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LTC1343
Software-Selectable Multiprotocol Transceiver
4-Driver/4-Receiver for Data and Clock Signals
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Software-Selectable Cable Terminator
Perfect for Terminating the LTC1543
LTC1345
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3-Driver/3-Receiver for Data and Clock Signals
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3-Driver/3-Receiver for Data and Clock Signals
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Software-Selectable Multiprotocol Transceiver
4-Driver/4-Receiver for Control Signals Including LL
LTC1545
Software-Selectable Multiprotocol Transceiver
5-Driver/5-Receiver for Control Signals Including LL, RL and TM
LTC1546
Software-Selectable Multiprotocol Transceiver with
Termination
3-Driver/3-Receiver for Data and Clock Signals
LTC2844
3.3V Multiprotocol Transceiver
4-Driver/4-Receiver for Control Signals Including LL
LTC2845
3.3V Multiprotocol Transceiver
5-Driver/5-Receiver for Control Signals Including LL, RL and TM
LTC2846
3.3V Multiprotocol Transceiver with Termination
3-Driver/3-Receiver for Data and Clock Signals
sn1534 1543fas
20
Linear Technology Corporation
LW/TP 1002 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 1998
工商网监
湘ICP备2023018690号
