LTC2436-1IGN#TRPBF

LTC2436-1 2-Channel Differential Input 16-Bit No Latency ∆Σ ADC U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 2-Channel Differential Input with Automatic Channel Selection (Ping-Pong) Low Supply Current: 200µA, 4µA in Autosleep Differential Input and Differential Reference with GND to VCC Common Mode Range 0.12LSB INL, No Missing Codes 0.16LSB Full-Scale Error and 0.006LSB Offset 800nV RMS Noise, Independent of VREF No Latency: Digital Filter Settles in a Single Cycle and Each Channel Conversion is Accurate Internal Oscillator—No External Components Required 87dB Min, 50Hz and 60Hz Notch Filter Narrow SSOP-16 Package Single Supply 2.7V to 5.5V Operation Pin Compatible with the 24-Bit LTC2412 U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Gas Analyzers Strain-Gage Transducers Instrumentation Data Acquisition Industrial Process Control The converter accepts any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The fullscale differential input range is from – 0.5 •␣ VREF to 0.5 • VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set anywhere between GND and VCC. The DC common mode input rejection is better than 140dB. The LTC2436-1 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRETM protocols. , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. U ■ The LTC®2436-1 is a 2-channel differential input micropower 16-bit No Latency ∆ΣTM analog-to-digital converter with an integrated oscillator. It provides 0.5LSB INL and 800nV RMS noise independent of VREF. The two differential channels convert alternately with a channel identification included in the conversion result. It uses delta-sigma technology and provides single conversion settling of the digital filter. Through a single pin, the LTC2436-1 can be configured for better than 87dB input differential mode rejection at 50Hz and 60Hz ±2%, or it can be driven by an external oscillator for a user defined rejection frequency. The internal oscillator requires no external frequency setting components. TYPICAL APPLICATIO Effective Resolution vs VREF 90 1µF 1 4.9k (100mV) 100Ω 2 4 5 THERMOCOUPLE VCC FO + REF CH0+ LTC2436-1 CH0– SCK 3 REF – SDO 6 + 7 8, 9, 10, 15, 16 14 CH1 CS = EXTERNAL CLOCK SOURCE = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION 13 12 3-WIRE SPI INTERFACE EFFECTIVE RESOLUTION (µV)* 80 5V REF 70 60 50 40 30 20 10 11 0 CH1– 5 4 3 2 VREF (V) 24361 TA02 *COMBINES EFFECTS OF PEAK-TO-PEAK NOISE AND 16-BIT STEP SIZE (VREF/216) 0 GND 24361 TA01 1 24361f 1 LTC2436-1 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2436-1C ............................................ 0°C to 70°C LTC2436-1I ........................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW VCC 1 16 GND REF + 2 15 GND REF – 3 14 FO CH0+ 4 13 SCK CH0– 5 12 SDO CH1+ 6 11 CS CH1– 7 10 GND GND 8 9 LTC2436-1CGN LTC2436-1IGN GN PART MARKING 24361 24361I GND GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 110°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) ● 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6) REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 0.06 0.12 0.30 3 LSB LSB LSB Offset Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC, (Note 13) 0.006 1 LSB Offset Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC Positive Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ Negative Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 0.03 Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 0.20 0.20 0.25 Output Noise 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF – = GND, GND ≤ IN– = IN+ ≤ VCC, (Note 13) 0.8 ● ● 16 Bits 10 ● 0.16 nV/°C 3 0.03 ● 0.16 LSB ppm of VREF/°C 3 LSB ppm of VREF/°C 3 3 3 LSB LSB LSB µVRMS 24361f 2 LTC2436-1 U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN– = IN+ ≤ VCC (Note 5) ● 130 140 MAX UNITS Input Common Mode Rejection 49Hz to 61.2Hz 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN – = IN+ ≤ VCC, (Notes 5, 7) ● 140 dB Input Normal Mode Rejection 49Hz to 61.2Hz (Note 5, 7) ● 87 dB Reference Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V, VREF = 2.5V, IN– = IN+ = GND (Note 5) ● 130 Power Supply Rejection, DC Power Supply Rejection, Simultaneous 50Hz/60Hz ±2% dB 140 dB REF+ = 2.5V, REF– = GND, IN– = IN+ = GND 120 dB REF+ 120 dB = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) U U U U A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER IN+ Absolute/Common Mode IN+ Voltage CONDITIONS MIN TYP MAX UNITS ● GND – 0.3 VCC + 0.3 IN– Absolute/Common Mode IN– Voltage ● GND – 0.3 VCC + 0.3 V VIN Input Differential Voltage Range (IN+ – IN–) ● –VREF/2 VREF/2 V REF+ Absolute/Common Mode REF+ Voltage ● 0.1 VCC V REF– Absolute/Common Mode REF– Voltage ● GND VCC – 0.1 V VREF Reference Differential Voltage Range (REF+ – REF–) ● 0.1 VCC V CS (IN+) V IN+ Sampling Capacitance 18 pF CS (IN–) IN– 18 pF CS (REF+) REF+ Sampling Capacitance 18 pF CS (REF–) REF– Sampling Capacitance 18 pF IDC_LEAK (IN+) IN+ IDC_LEAK (IN–) IN– Sampling Capacitance DC Leakage Current ● –10 1 10 nA CS = VCC = 5V, IN – = 5.5V ● –10 1 10 nA IDC_LEAK (REF+) REF+ DC Leakage Current CS = VCC = 5V, REF+ = 5.5V ● –10 1 10 nA (REF–) REF– DC Leakage Current = 5V, REF – = GND ● –10 1 10 nA IDC_LEAK DC Leakage Current CS = VCC = 5V, IN+ = GND CS = VCC 24361f 3 LTC2436-1 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage CS, FO 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V ● VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 2.7V ≤ VCC ≤ 5.5V (Note 8) 2.7V ≤ VCC ≤ 3.3V (Note 8) ● VIL Low Level Input Voltage SCK 4.5V ≤ VCC ≤ 5.5V (Note 8) 2.7V ≤ VCC ≤ 5.5V (Note 8) ● IIN Digital Input Current CS, FO 0V ≤ VIN ≤ VCC ● IIN Digital Input Current SCK 0V ≤ VIN ≤ VCC (Note 8) ● CIN Digital Input Capacitance CS, FO CIN Digital Input Capacitance SCK (Note 8) VOH High Level Output Voltage SDO IO = –800µA ● VOL Low Level Output Voltage SDO IO = 1.6mA ● VOH High Level Output Voltage SCK IO = –800µA (Note 9) ● VOL Low Level Output Voltage SCK IO = 1.6mA (Note 9) ● IOZ Hi-Z Output Leakage SDO ● TYP MAX UNITS 2.5 2.0 V V 0.8 0.6 V V 2.5 2.0 V V 0.8 0.6 V V –10 10 µA –10 10 µA 10 pF 10 pF VCC – 0.5 V 0.4 V VCC – 0.5 V –10 0.4 V 10 µA U W POWER REQUIRE E TS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER VCC Supply Voltage ICC Supply Current Conversion Mode Sleep Mode Sleep Mode CONDITIONS MIN ● CS = 0V (Note 14) CS = VCC (Notes 11, 14) CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Notes 11, 14) ● ● TYP 2.7 200 4 2 MAX UNITS 5.5 V 300 13 µA µA µA 24361f 4 LTC2436-1 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN fEOSC External Oscillator Frequency Range ● tHEO External Oscillator High Period ● tLEO External Oscillator Low Period tCONV Conversion Time FO = 0V External Oscillator (Note 10) fISCK Internal SCK Frequency Internal Oscillator (Note 9) External Oscillator (Notes 9, 10) DISCK Internal SCK Duty Cycle (Note 9) ● fESCK External SCK Frequency Range (Note 8) ● tLESCK External SCK Low Period (Note 8) ● tHESCK External SCK High Period (Note 8) ● 250 tDOUT_ISCK Internal SCK 19-Bit Data Output Time Internal Oscillator (Notes 9, 11) External Oscillator (Notes 9, 10) ● ● 1.06 tDOUT_ESCK External SCK 19-Bit Data Output Time (Note 8) ● t1 CS ↓ to SDO Low Z ● 0 200 ns t2 CS ↑ to SDO High Z ● 0 200 ns t3 CS ↓ to SCK ↓ (Note 9) ● 0 200 ns t4 CS ↓ to SCK ↑ (Note 8) ● 50 tKQMAX SCK ↓ to SDO Valid MAX UNITS 2.56 2000 kHz 0.25 390 µs ● 0.25 390 µs ● ● 143.8 tKQMIN SDO Hold After SCK ↓ ● 15 ns t5 SCK Set-Up Before CS ↓ ● 50 ns t6 SCK Hold After CS ↓ ● Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF + – REF –, VREFCM = (REF + + REF –)/2; VIN = IN+ – IN –, VINCM = (IN + + IN –)/2, IN+ and IN– are defined as the selected positive (CH0+ or CH1+) and negative (CH0– or CH1–) input respectively. Note 4: FO pin tied to GND or to an external conversion clock source with fEOSC = 139,800Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size (VREF/216) and the single shot measurement. Typical specifications are measured from the center of the quantization band. Note 7: FO = GND (internal oscillator) or fEOSC = 139,800Hz ±2% (external oscillator). 146.7 149.6 20510/fEOSC (in kHz) 17.5 fEOSC/8 45 ms ms kHz kHz 55 % 2000 kHz 250 ns ns 1.09 1.11 152/fEOSC (in kHz) ms ms 19/fESCK (in kHz) ms ns 220 ● (Note 5) TYP 50 ns ns Note 8: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 9: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. FO = 0V. Note 12: 800nV RMS noise is independent of VREF. Since the noise performance is limited by the quantization, lowering VREF improves the effective resolution. Note 13: Guaranteed by design and test correlation. Note 14: The low sleep mode current is valid only when CS is high. 24361f 5 LTC2436-1 U U U PI FU CTIO S VCC (Pin 1): Positive Supply Voltage. Bypass to GND with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. REF + (Pin 2), REF – (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF –, by at least 0.1V. SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. CH0+ (Pin 4): Positive Input for Differential Channel 0. CH0 – (Pin 5): Negative Input for Differential Channel 0. CH1+ (Pin 6): Positive Input for Differential Channel 1. CH1– (Pin 7): Negative Input for Differential Channel 1. The voltage on these four analog inputs (Pins 4 to 7) can have any value between GND and VCC. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from – 0.5 • (VREF ) to 0.5 • (VREF ). Outside this input range the converter produces unique overrange and underrange output codes. GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All five pins must be connected to ground for proper operation. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 14): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to GND (FO = 0V), the converter uses its internal oscillator and rejects 50Hz and 60Hz simultaneously. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter has 87dB minimum rejection in the range fEOSC/2560 ±14% and 110dB minimum rejection at fEOSC/2560 ±4%. 24361f 6 LTC2436-1 W FU CTIO AL BLOCK DIAGRA U INTERNAL OSCILLATOR U VCC GND FO (INT/EXT) AUTOCALIBRATION AND CONTROL CH0+ CH0– IN + MUX CH1+ CH1– SCK DIFFERENTIAL 3RD ORDER ∆Σ MODULATOR IN – + – SERIAL INTERFACE SDO CS DECIMATING FIR CH0/CH1 PING-PONG REF + 24361 FD REF – Figure 1. Functional Block Diagram TEST CIRCUITS VCC 1.69k SDO SDO 1.69k Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z CLOAD = 20pF 24361 TA03 CLOAD = 20pF Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 24361 TA04 24361f 7 LTC2436-1 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2436-1 is a low power, ∆Σ ADC with automatic alternate channel selection between the two differential channels and an easy-to-use 3-wire serial interface (see Figure 1). Channel 0 is selected automatically at power up and the two channels are selected alternately afterwards (ping-pong). Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2436-1 performs a conversion. Once the conversion is complete, the device enters the sleep state. The part remains in the sleep state as long as CS is HIGH. While in this sleep state, power consumption is reduced by nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device exits the low power mode and enters the data output state. If CS is pulled HIGH before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. If CS remains LOW POWER UP IN+ = CH0 +, IN – = CH0 – CONVERT SLEEP FALSE CS = LOW AND SCK TRUE DATA OUTPUT SWITCH CHANNEL after the first rising edge of SCK, the device begins outputting the conversion result. Taking CS high at this point will terminate the data output state and start a new conversion. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 19 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. In order to maintain compatibility with 24-/32-bit data transfers, it is possible to clock the LTC2436-1 with additional serial clock pulses. This results in additional data bits which are always logic HIGH. Through timing control of the CS and SCK pins, the LTC2436-1 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz and 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2436-1 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2436-1 achieves a minimum of 87dB rejection over the range 49Hz to 61.2Hz. Ease of Use 24361 F02 Figure 2. LTC2436-1 State Transition Diagram The LTC2436-1 data output has no latency, filter settling delay or redundant data associated with the conversion 24361f 8 LTC2436-1 U W U U APPLICATIO S I FOR ATIO cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. The LTC2436-1 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2436-1 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a typical duration of 1ms. The POR signal clears all internal registers and selects channel 0. Following the POR signal, the LTC2436-1 starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF – pin. The LTC2436-1 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will significantly improve the converter’s effective resolution, since the thermal noise (800nV) is well below the quantization level of the device (75.6µV for a 5V reference). At the minimum reference (100mV) the thermal noise remains constant at 800nV RMS (or 4.8µVP-P), while the quantization is reduced to 1.5µV per LSB. As a result, lower the reference improves the effective resolution for low level input voltages. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the CH0+/CH0– or CH1+/CH1– input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2436-1 converts the bipolar differential input signal, VIN = IN+ – IN–, from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–, with the selected channel referred as IN+ and IN–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to the analog input pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the pins without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 10nA input leakage current will develop a 1LSB offset error on an 8k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2436-1 serial output data stream is 19 bits long. The first 3 bits represent status information indicating the conversion state, selected channel and sign. The next 16 bits are the conversion result, MSB first. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS). 24361f 9 LTC2436-1 U W U U APPLICATIO S I FOR ATIO Bit 18 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 17 (second output bit) is the selected channel indicator. The bit is LOW for channel 0 and HIGH for channel 1 selected. Bit 16 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is 0.01µF) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), the typical differential input resistance is 2MΩ which will generate a gain error of approximately 1LSB at full scale for each 60Ω of source resistance driving IN+ or IN –. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential input resistance is 0.28 • 1012/fEOSCΩ and each ohm of source resistance driving IN+ or IN – will result in 1.11 • 10 –7 • fEOSCLSB gain error at full scale. The effect of the source resistance on the two input pins is additive with respect to this gain error. The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown in Figures 16 and 17. 24361f 21 LTC2436-1 U W U U APPLICATIO S I FOR ATIO In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN+ and IN– and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW (internal oscillator and 50Hz/60Hz notch), every 60Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1LSB. When FO is driven by an external oscillator with a frequency fEOSC, every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1.11 • 10–7 • fEOSCLSB. Figure 18 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used. 8 VCC = 5V REF + = 5V REF – = GND IN + = IN – = VINCM OFFSET ERROR (LSB) A 4 B E F –8 FO = GND TA = 25°C RSOURCEIN – = 500Ω CIN = 10µF G 0 0.5 1 1.5 A: ∆RIN = +400Ω B: ∆RIN = +200Ω C: ∆RIN = +100Ω D: ∆RIN = 0Ω 2 2.5 3 VINCM (V) 3.5 In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 15k source resistance will create a 0LSB typical and 1LSB maximum offset voltage. In a similar fashion, the LTC2436-1 samples the differential reference pins REF+ and REF– transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. D –4 The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by IN+ and IN–, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. Reference Current C 0 If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. 4 4.5 5 E: ∆RIN = –100Ω F: ∆RIN = –200Ω G: ∆RIN = –400Ω 24361 F18 Figure 18. Offset Error vs Common Mode Voltage (VINCM = IN+ = IN–) and Input Source Resistance Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF) For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. 24361f 22 LTC2436-1 U W U U APPLICATIO S I FOR ATIO Larger values of reference capacitors (CREF > 0.01µF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), the typical differential reference resistance is 1.4MΩ which will generate a gain error of approximately 1LSB full scale for each 40Ω of source resistance driving REF+ or REF–. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.20 • 1012/fEOSCΩ and each ohm of source resistance drving REF+ or REF– will result in 1.54 • 10–7 • fEOSCLSB gain error at full scale. The effect 3 VCC = 5V REF + = 5V REF – = GND IN + = 5V IN – = 2.5V FO = GND TA = 25°C –1 In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 50Hz/60Hz notch), every 1000Ω of source resistance driving REF+ or REF– translates into about 1LSB additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 100Ω of source resistance driving REF+ or REF– CREF = 0.01µF CREF = 0.001µF CREF = 100pF –FS ERROR (LSB) +FS ERROR (LSB) 0 of the source resistance on the two reference pins is additive with respect to this gain error. The typical +FS and –FS errors for various combinations of source resistance seen by the REF+ and REF– pins and external capacitance CREF connected to these pins are shown in Figures 19, 20, 21 and␣ 22. CREF = 0.01µF –2 2 CREF = 0pF VCC = 5V REF + = 5V REF – = GND IN + = GND IN – = 2.5V FO = GND TA = 25°C 1 CREF = 0.001µF CREF = 100pF CREF = 0pF –3 1 10 0 100 1k RSOURCE (Ω) 10k 1 100k 10 30 CREF = 0.01µF 22 17 22 30 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C –FS ERROR (LSB) +FS ERROR (LSB) 6 CREF = 0.1µF 100k Figure 20. –FS Error vs RSOURCE at REF+ or REF– (Small CIN) 0 11 10k 2412 F19 24361 F19 Figure 19. +FS Error vs RSOURCE at REF+ or REF– (Small CIN) 100 1k RSOURCE (Ω) 17 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = GND TA = 25°C CREF = 1µF, 10µF CREF = 0.1µF 11 6 CREF = 0.01µF CREF = 1µF, 10µF 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 24361 F21 Figure 21. +FS Error vs RSOURCE at REF+ and REF– (Large CREF) 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 24361 F22 Figure 22. –FS Error vs RSOURCE at REF+ and REF– (Large CREF) 24361f 23 LTC2436-1 U W U U APPLICATIO S I FOR ATIO translates into about 5.5 • 10–7 • fEOSCLSB additional INL error. Figure␣ 23 shows the typical INL error due to the source resistance driving the REF+ or REF– pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF+ and REF– pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF– pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/°C) are used for the external source impedance seen by REF+ and REF–, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. INL (LSB) 1 RSOURCE = 1000Ω 0 –1 –0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF VCC = 5V FO = GND REF+ = 5V CREF = 10µF TA = 25°C REF– = GND 24361 F23 VINCM = 0.5 • (IN + + IN –) = 2.5V Figure 23. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1µF) In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a small gain error. A 100Ω source resistance will create a 0.05µV typical and 0.5µV maximum full-scale error. Output Data Rate When using its internal oscillator, the LTC2436-1 can produce up to 6.8 readings per second. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2436-1 output data rate can be increased as desired. The duration of the conversion phase is 20510/fEOSC. If fEOSC = 139,800Hz, the converter behaves as if the internal oscillator is used with simultaneous 50Hz/60Hz. There is no significant difference in the LTC2436-1 performance between these two operation modes. An increase in fEOSC over the nominal 139,800Hz will translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered. First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2436-1’s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN– pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external 24361f 24 LTC2436-1 U W U U APPLICATIO S I FOR ATIO input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/ or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2436-1 typical performance can be inferred from Figures 14, 15, 19 and 20 in which the horizontal axis is scaled by 139,800/fEOSC. 420 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = EXTERNAL OSCILLATOR 360 +FS ERROR (LSB) OFFSET ERROR (LSB) 30 Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures␣ 24, 25, 26, 27, 28 and 29. In order to obtain the 15 TA = 85°C 300 240 180 TA = 85°C 120 TA = 25°C TA = 25°C 60 0 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24361 F25 24361 F24 Figure 24. Offset Error vs Output Data Rate and Temperature Figure 25. +FS Error vs Output Data Rate and Temperature 0 17 60 16 RESOLUTION (BITS) –FS ERROR (LSB) TA = 85°C 120 TA = 25°C 180 240 VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = EXTERNAL OSCILLATOR 300 360 420 0 TA = 25°C 15 TA = 85°C VCC = 5V + = 5V REF REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/NOISERMS) 14 13 12 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24361 F26 Figure 26. –FS Error vs Output Data Rate and Temperature 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24361 F27 Figure 27. Resolution (NoiseRMS ≤ 1LSB) vs Output Data Rate and Temperature 24361f 25 LTC2436-1 U W U U APPLICATIO S I FOR ATIO 18 16 TA = 85°C TA = 25°C OFFSET ERROR (LSB) RESOLUTION (BITS) 16 14 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V –2.5V < VIN < 2.5V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/INLMAX) 12 10 8 0 VCC = 5V REF + = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 25°C 8 VREF = 5V VREF = 2.5V 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24361 F28 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 24361 F29 Figure 28. Resolution (INLMAX ≤ 1LSB) vs Output Data Rate and Temperature Figure 29. Offset Error vs Output Data Rate and Reference Voltage highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial. output code will be stable to ±1LSB for a fixed input. As the reference is decreased further, the measured noise will approach 800nVRMS. Increasing Input Resolution by Reducing Reference Voltage The resolution of the LTC2436-1 can be increased by reducing the reference voltage. It is often necessary to amplify low level signals to increase the voltage resolution of ADCs that cannot operate with a low reference voltage. The LTC2436-1 can be used with reference voltages as low as 100mV, corresponding to a ±50mV input range with full 16-bit resolution. Reducing the reference voltage is functionally equivalent to amplifying the input signal, however no amplifier is required. The LTC2436-1 has a 76µV LSB when used with a 5V reference, however the thermal noise of the inputs is 800nVRMS and is independent of reference voltage. Thus reducing the reference voltage will increase the resolution at the inputs as long as the LSB voltage is significantly larger than 800nVRMS. A 325mV reference corresponds to a 5µV LSB, which is approximately the peak-to-peak value of the 800nVRMS input thermal noise. At this point, the Figure 30 shows two methods of dividing down the reference voltage to the LTC2436-1. Where absolute accuracy is required, a precision divider such as the Vishay MPM series dividers in a SOT-23 package may be used. A 51:1 divider provides a 98mV reference to the LTC24361 from a 5V source. The resulting ±49mV input range and 1.5µV LSB is suitable for thermocouple and 10mV fullscale strain gauge measurements. If high initial accuracy is not critical, a standard 2% resistor array such as the Panasonic EXB series may be used. Single package resistor arrays provide better temperature stability than discrete resistors. An array of eight resistors can be configured as shown to provide a 294mV reference to the LTC2436-1 from a 5V source. The fully differential property of the LTC2436-1 reference terminals allow the reference voltage to be taken from four central resistors in the network connected in parallel, minimizing drift in the presence of thermal gradients. This is an ideal reference for medium accuracy sensors such as silicon micromachined pressure and force sensors. These devices typically have accuracies on the order of 2% and fullscale outputs of 50mV to 200mV. 24361f 26 LTC2436-1 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .053 – .068 (1.351 – 1.727) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 0502 24361f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC2436-1 U TYPICAL APPLICATIO PANASONIC EXB-2HV202G REF + 5V 5V 8 × 2k ARRAY 0.1µF 1 REF – VREF = 294mV ±147mV INPUT RANGE 4.5µV LSB 2 3 5V VISHAY MPM1001/5002B 5V 50k REF + HONEYWELL FSL05N2C 500 GRAM FORCE SENSOR 4.7µF VCC REF FO REF – 4 CH0+ LTC2436-1 5 CH0– SCK SDO THERMOCOUPLE 1k 6 CH1+ 7 CH1– 8, 9, 10, 15, 16 REF – 14 + CS 13 12 11 GND 24361 F30 VREF = 95.04mV ±49mV INPUT RANGE 1.5µV LSB Figure 30. Increased Resolution Bridge/Temperature Measurement RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max LTC1043 Dual Precision Instrumentation Switched Capacitor Building Block Precise Charge, Balanced Switching, Low Power LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µVP-P Noise LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift LT1461 Micropower Precision LDO Reference High Accuracy 0.04% Max, 3ppm/°C Max Drift LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2410 24-Bit, Fully Differential, No Latency ∆Σ ADC 0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA LTC2411 24-Bit, No Latency ∆Σ ADC in MSOP 1.45µVRMS Noise, 2ppm INL LTC2411-1 24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC 0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411 LTC2412 2-Channel, 24-Bit, Pin Compatible with LTC2436-1 800nV Noise, 2ppm INL, 3ppm TUE, 200µA LTC2413 24-Bit, No Latency ∆Σ ADC Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise LTC2414/LTC2418 8-/16-Channel, 24-Bit No Latency ∆Σ ADC 0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA LTC2415 24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate Pin Compatible with the LTC2410 LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408 LTC2440 High Speed, Low Noise 24-Bit ADC 4kHz Output Rate, 200nV Noise, 24.6 ENOBs 24361f 28 Linear Technology Corporation LT/TP 0103 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2003