LTC2636
Octal 12-/10-/8-Bit SPI VOUT
DACs with10ppm/°C Reference
DESCRIPTION
FEATURES
n
n
n
n
n
n
n
n
n
n
n
Integrated Precision Reference
2.5V Full-Scale 10ppm/°C (LTC2636-L)
4.096V Full-Scale 10ppm/°C (LTC2636-H)
Maximum INL Error: 2.5LSB (LTC2636-12)
Low Noise: 0.75mVP-P 0.1Hz to 200KHz
Guaranteed Monotonic Over –40°C to 125°C
Temperature Range
Selectable Internal or External Reference
2.7V to 5.5V Supply Range (LTC2636-L)
Ultralow Crosstalk Between DACs ( 4V requires
VCC slew rates to be no greater than 110mV/µs.
Note 4: Linearity and monotonicity are defined from code kL to code 2N–1,
where N is the resolution and kL is given by kL = 0.016•(2N/VFS), rounded
to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity
is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL =
16 and linearity is defined from code 16 to code 4,095.
Note 5: Inferred from measurement at code 16 (LTC2636-12), code 4
(LTC2636-10) or code 1 (LTC2636-8), and at full-scale.
ns
50
l
200
MHz
ns
Note 6: This IC includes current limiting that is intended to protect the
device during momentary overload conditions. Junction temperature can
exceed the rated maximum during current limiting. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 7: Digital inputs at 0V or VCC.
Note 8: Guaranteed by design and not production tested.
Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND.
Note 10: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 11: Thermal resistance of MSOP package limits IOUT to
–5mA ≤ IOUT ≤ 5mA for H-grade MSOP parts and VCC = 5V ±10%.
Rev D
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9
LTC2636
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted. LTC2636-L12 (Internal Reference, VFS = 2.5V)
Integral Nonlinearity (INL)
1.0
Differential Nonlinearity (DNL)
1.0
VCC = 3V
0.5
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
VCC = 3V
0
–0.5
0
1024
3072
2048
CODE
–1.0
4095
1024
0
2048
CODE
3072
2636 G01
INL vs Temperature
INL (POS)
1.260
VCC = 3V
0.5
0
INL (NEG)
–0.5
–1.0
–50 –25
Reference Output Voltage
vs Temperature
DNL (POS)
0
DNL (NEG)
–0.5
0
25 50 75 100 125 150
TEMPERATURE (°C)
VCC = 3V
1.255
VREF (V)
INL (LSB)
1.0
VCC = 3V
0.5
2636 G02
DNL vs Temperature
DNL (LSB)
1.0
4095
1.250
1.245
–1.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2636 G03
1.240
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2636 G04
Settling to ±1LSB Rising
2636 G05
Settling to ±1LSB Falling
CS/LD
5V/DIV
3/4 SCALE TO
1/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
VOUT
1LSB/DIV
3.6µs
4.4µs
VOUT
1LSB/DIV
1/4 SCALE TO
3/4 SCALE STEP
VCC = 3V, VFS = 2.5V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
CS/LD
5V/DIV
2µs/DIV
2µs/DIV
2636 G06
2636 G07
Rev D
10
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LTC2636
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted. LTC2636-H12 (Internal Reference, VFS = 4.096V)
Integral Nonlinearity (INL)
1.0
Differential Nonlinearity (DNL)
1.0
VCC = 5V
0.5
DNL (LSB)
INL (LSB)
0.5
0
0
–0.5
–0.5
–1.0
VCC = 5V
0
1024
3072
2048
CODE
–1.0
4095
1024
0
2048
CODE
3072
2636 G09
2636 G08
INL vs Temperature
1.0
VCC = 5V
INL (POS)
INL (NEG)
–0.5
DNL (POS)
0
DNL (NEG)
25 50 75 100 125 150
TEMPERATURE (°C)
–1.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2636 G10
2.028
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2636 G12
2636 G11
Settling to ±1LSB Rising
Settling to ±1LSB Falling
CS/LD
5V/DIV
1/4 SCALE TO
3/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
VOUT
1LSB/DIV
4.0µs
VOUT
1LSB/DIV
2.048
2.038
–0.5
0
VCC = 5V
2.058
0.5
0
–1.0
–50 –25
2.068
VCC = 5V
VREF (V)
INL (LSB)
0.5
Reference Output Voltage
vs Temperature
DNL vs Temperature
DNL (LSB)
1.0
4095
4.8µs
1/4 SCALE TO
3/4 SCALE STEP
VCC = 5V, VFS = 4.095V
RL = 2k, CL = 100pF
AVERAGE OF 256 EVENTS
CS/LD
5V/DIV
2µs/DIV
2µs/DIV
2636 G13
2636 G14
Rev D
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11
LTC2636
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
LTC2636-10
Integral Nonlinearity (INL)
1.0
Differential Nonlinearity (DNL)
1.0
VCC = 3V
VFS = 2.5V
INTERNAL REF.
0.5
DNL (LSB)
INL (LSB)
0.5
0
–0.5
–1.0
VCC = 3V
VFS = 2.5V
INTERNAL REF.
0
–0.5
256
0
768
512
CODE
–1.0
1023
256
0
512
CODE
768
2636 G15
1023
2636 G16
LTC2636-8
Integral Nonlinearity (INL)
0.50
Differential Nonlinearity (DNL)
0.50
VCC = 3V
VFS = 2.5V
INTERNAL REF.
0.25
DNL (LSB)
INL (LSB)
0.25
0
0
–0.25
–0.25
–0.50
VCC = 3V
VFS = 2.5V
INTERNAL REF.
64
0
192
128
CODE
–0.50
255
64
0
128
CODE
192
255
2636 G18
2636 G17
LTC2636
8
6
Current Limiting
0.20
VCC = 5V (LTC2636-H)
VCC = 5V (LTC2636-L)
VCC = 3V (LTC2636-L)
0.15
0.10
2
ΔVOUT (V)
ΔVOUT (mV)
4
0
–2
–4
VCC = 5V (LTC2636-H)
VCC = 5V (LTC2636-L)
VCC = 3V (LTC2636-L)
2
0.05
0
–0.05
–0.01
–6
INTERNAL REF.
CODE = MIDSCALE
–8
–10
–30
Offset Error vs Temperature
3
OFFSET ERROR (mV)
Load Regulation
10
–20
–10
0
10
IOUT (mA)
20
30
2636 G19
–0.15
–0.20
–30
INTERNAL REF.
CODE = MIDSCALE
–20
–10
0
10
IOUT (mA)
20
30
2636 G20
1
0
–1
–2
–3
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2636 G21
Rev D
12
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LTC2636
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
LTC2636
Large-Signal Response
Mid-Scale Glitch Impulse
Power-On Reset Glitch
LTC2636-L
CS/LD
5V/DIV
VOUT
0.5V/DIV
VCC
2V/DIV
LTC2636-H12, VCC = 5V
3.0nV•s TYP
VOUT
5mV/DIV
LTC2636-L12, VCC = 3V
2.1nV•s TYP
VFS = VCC = 5V
1/4 SCALE to 3/4 SCALE
2µs/DIV
2µs/DIV
200µs/DIV
2636 G22
2636 G23
Headroom at Rails
vs Output Current
LTC2636-H
5V SOURCING
VCC = 5V
INTERNAL REF.
4.0
VOUT (V)
3.5
Power-On Reset to Mid-Scale
VCC
2V/DIV
CS/LD
2V/DIV
3V (LTC2636-L) SOURCING
3.0
2636 G24
Exiting Power-Down to Mid-Scale
5.0
4.5
LTC2636-H
2.5
2.0
1.5
DACs A-G IN
VOUT POWER-DOWN MODE
0.5V/DIV
5V SINKING
VOUT
0.5V/DIV
1.0
0
LTC2636-L
3V (LTC2636-L) SINKING
0.5
0
1
2
3
4 5 6
IOUT (mA)
7
8
9
5µs/DIV
10
200µs/DIV
2636 G26
2636 G27
2636 G25
Supply Current vs Logic Voltage
1.5
Hardware CLR
Hardware CLR to Mid-Scale
VCC = 5V
VREF = 4.096V
CODE = FULL-SCALE
SWEEP SCK, SDI, CS/LD
BETWEEN 0V AND VCC
1.4
VOUT
1V/DIV
ICC (mA)
ZERO-SCALE
VOUT
5mV/DIV
VOUT
1V/DIV
VCC = 5V
VREF = 4.096V
CODE = FULL-SCALE
1.2
VCC = 5V
1.0
VCC = 3V
(LTC2636-L)
0.8
0.6
0
1
2
3
LOGIC VOLTAGE (V)
CLR
5V/DIV
CLR
5V/DIV
4
5
1µs/DIV
1µs/DIV
2636 G29
2636 G30
2636 G28
Rev D
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13
LTC2636
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
LTC2636
Multiplying Bandwidth
Noise Voltage vs Frequency
2
500
0
NOISE VOLTAGE (nV/√Hz)
–2
–4
dB
–6
–8
–10
–12
VCC = 5V
VREF(DC) = 2V
VREF(AC) = 0.2VP-P
CODE = FULL-SCALE
–14
–16
–18
1k
10k
100k
FREQUENCY (Hz)
400
VCC = 5V
CODE = MID-SCALE
INTERNAL REF.
300
LTC2636-H
200
LTC2636-L
100
0
100
1M
1k
10k
100k
FREQUENCY (Hz)
2636 G31
2636 G32
Gain Error vs Reference Input
0.1Hz to 10Hz Voltage Noise
1.0
VCC = 5V, VFS = 2.5V
CODE = MIDSCALE
INTERNAL REF.
VCC = 5.5V
0.8 GAIN ERROR OF 8 CHANNELS
0.6
GAIN ERROR (%FSR)
1M
0.4
0.2
10µV/DIV
0
–0.2
–0.4
–0.6
–0.8
–1.0
1
1.5
2 2.5 3 3.5 4 4.5
REFERENCE VOLTAGE (V)
5
1s/DIV
5.5
2636 G34
2636 G33
DAC to DAC Crosstalk (Dynamic)
Gain Error vs Temperature
1.0
GAIN ERROR (%FSR)
CS/LD
5V/DIV
1 DAC
SWITCH 0-FS
2V/DIV
VOUT
1mV/DIV
LTC2636-H12, VCC = 5V
2.4nV•s TYP
CREF = 0.1µF
2µs/DIV
2636 G35
0.5
0
–0.5
–1.0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
2636 G36
Rev D
14
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LTC2636
PIN FUNCTIONS
(DFN/MSOP)
VCC (Pin 1/1): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V
(LTC2636-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2636-H). Bypass
to GND with a 0.1μF capacitor.
VOUT A to VOUT H (Pins 2-5, 10-13/2-5, 12-15): DAC
Analog Voltage Outputs.
CS/LD (Pin 6/7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specified command (see Table 1) is
executed.
SCK (Pin 7/8): Serial Interface Clock Input. CMOS and
TTL compatible.
SDI (Pin 8/9): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK. The
LTC2636 accepts input word lengths of either 24 or 32 bits.
REF (Pin 9/11): Reference Voltage Input or Output. When
External Reference mode is selected, REF is an input
(1V ≤ VREF ≤ VCC) where the voltage supplied sets the
full-scale DAC output voltage. When Internal Reference
is selected, the 10ppm/°C 1.25V (LTC2636-L) or 2.048V
(LTC2636-H) internal reference (half full-scale) is available at REF. This output may be bypassed to GND with up
to 10μF, and must be buffered when driving external DC
load current.
GND (Pin 14/16): Ground.
LDAC (Pin 6, MSOP only): Asynchronous DAC Update
Pin. If CS/LD is high, a falling edge on LDAC immediately
updates the DAC registers with the contents of the input
registers (similar to a software update). If CS/LD is low
when LDAC goes low, the DAC registers are updated after
CS/LD returns high. A low on the LDAC pin powers up
the DACs. A software power down command is ignored if
LDAC is low. If the LDAC functionality is not being used,
the LDAC pin should be tied high.
CLR (Pin 10, MSOP only): Asynchronous Clear Input.
A logic low at this level-triggered input clears all registers and causes the DAC voltage output to reset to Zero
(LTC2636-Z) or Mid-scale (LTC2636-MI/-MX). CMOS and
TTL compatible.
Exposed Pad (Pin 15, DFN Only): Ground. Must be soldered to PCB Ground.
Rev D
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15
LTC2636
BLOCK DIAGRAM
SWITCH
INTERNAL REFERENCE
REF
VREF
GND
REGISTER
REGISTER
DAC A
REGISTER
VOUTA
REGISTER
VCC
DAC H
VREF
REGISTER
REGISTER
DAC B
REGISTER
REGISTER
VREF
VOUTB
DAC G
REGISTER
REGISTER
REGISTER
REGISTER
DAC C
DAC F
VOUTF
VREF
REGISTER
REGISTER
DAC D
REGISTER
REGISTER
VREF
VOUTD
VOUTG
VREF
VREF
VOUTC
VOUTH
DAC E
VOUTE
CS/LD
CONTROL LOGIC
SDI
DECODE
SCK
(LDAC)
32-BIT SHIFT REGISTER
(CLR)
POWER-ON RESET
2636 BD
( ) MSOP PACKAGE ONLY
TIMING DIAGRAMS
t1
t2
SCK
t3
1
t6
t4
2
3
23
24
t10
SDI
t5
t7
CS/LD
t11
t9
LDAC
2636 F01a
Figure 1a
CS/LD
t11
LDAC
2636 F01b
Figure 1b
Rev D
16
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LTC2636
OPERATION
The LTC2636 is a family of octal voltage output DACs in
14-lead DFN and 16-lead MSOP packages. Each DAC can
operate rail-to-rail using an external reference, or with its
full-scale voltage set by an integrated reference. Eighteen
combinations of accuracy (12-, 10-, and 8-bit), poweron reset value (zero-scale, mid-scale in internal reference mode, or mid-scale in external reference mode),
and full-scale voltage (2.5V or 4.096V) are available. The
LTC2636 is controlled using a 3-wire SPI/MICROWIRE
compatible interface.
Power-On Reset
Transfer Function
The digital-to-analog transfer function is:
⎛k ⎞
VOUT(IDEAL) = ⎜ n ⎟ VREF
⎝2 ⎠
where k is the decimal equivalent of the binary DAC
input code, n is the resolution, and VREF is either 2.5V
(LTC2636-LMI/-LMX/-LZ) or 4.096V (LTC2636-HMI/HMX/-HZ) when in Internal Reference mode, and the
voltage at REF when in External Reference mode.
Table 1. Command Codes
The LTC2636-HZ/-LZ clear the output to zero-scale when
power is first applied, making system initialization consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2636
contains circuitry to reduce the power-on glitch: the
analog output typically rises less than 5mV above zeroscale during power on. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See “Power-On Reset Glitch” in the Typical Performance
Characteristics section.
The LTC2636-HMI/-HMX/-LMI/-LMX provide an alternative reset, setting the output to mid-scale when power is
first applied. The LTC2636-LMI and LTC2636-HMI power
up in internal reference mode, with the output set to a
mid-scale voltage of 1.25V and 2.048V respectively. The
LTC2636-LMX and LTC2636-HMX power-up in external
reference mode, with the output set to mid-scale of the
external reference. Default reference mode selection is
described in the Reference Modes section.
COMMAND*
C3
C2
C1
C0
0
0
0
0
Write to Input Register n
0
0
0
1
Update (Power-Up) DAC Register n
0
0
1
0
Write to Input Register n, Update (Power-Up) All
0
0
1
1
Write to and Update (Power-Up) DAC Register n
0
1
0
0
Power-Down DAC n
0
1
0
1
Power-Down Chip (All DAC’s and Reference)
0
1
1
0
Select Internal Reference (Power-Up Reference)
0
1
1
1
Select External Reference (Power-Down Internal
Reference)
1
1
1
1
No Operation
*Command codes not shown are reserved and should not be used.
Table 2. Address Codes
ADDRESS (n)*
A3
A2
A1
A0
0
0
0
0
DAC A
0
0
0
1
DAC B
0
0
1
0
DAC C
0
0
1
1
DAC D
0
1
0
0
DAC E
Power Supply Sequencing
0
1
0
1
DAC F
The voltage at REF (Pin 9-DFN, Pin 11-MSOP) must be
kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see
Absolute Maximum Ratings). Particular care should be
taken to observe these limits during power supply turnon and turn-off sequences, when the voltage at VCC is in
transition.
0
1
1
0
DAC G
0
1
1
1
DAC H
1
1
1
1
ALL DACS
*Address codes not shown are reserved and should not be used.
Rev D
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17
LTC2636
OPERATION
INPUT WORD (LTC2636-12)
COMMAND
C3
C2
C1
ADDRESS
C0
A3
A2
A1
DATA (12 BITS + 4 DON'T-CARE BITS)
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
LSB
INPUT WORD (LTC2636-10)
COMMAND
C3
C2
C1
ADDRESS
C0
A3
A2
A1
DATA (10 BITS + 6 DON'T-CARE BITS)
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
LSB
INPUT WORD (LTC2636-8)
COMMAND
C3
C2
C1
ADDRESS
C0
A3
A2
A1
DATA (8 BITS + 8 DON'T-CARE BITS)
A0
D7
D6
D5
D4
D3
D2
D1
MSB
D0
X
LSB
X
X
2636 F02
Figure 2. Command and Data Input Format
Serial Interface
The CS/LD input is level triggered. When this input is
taken low, it acts as a chip-select signal, enabling the SDI
and SCK buffers and the input shift register. Data (SDI
input) is transferred into the LTC2636 on the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first;
then the 4-bit DAC address, A3-A0; and finally the 16-bit
data word. The data word comprises the 12-, 10- or 8-bit
input code, ordered MSB-to-LSB, followed by 4, 6 or 8
don’t-care bits (LTC2636-12, -10 and -8 respectively; see
Figure 2). Data can only be transferred to the device when
the CS/LD signal is low, beginning on the first rising edge
of SCK. SCK may be high or low at the falling edge of
CS/LD. The rising edge of CS/LD ends the data transfer
and causes the device to execute the command specified
in the 24-bit input sequence. The complete sequence is
shown in Figure 3a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Tables 1 and 2. The first four commands in
Table 1 consist of write and update operations. A Write
operation loads a 16-bit data word from the 24-bit shift
register into the input register of the selected DAC, n. An
Update operation copies the data word from the input
register to the DAC register. Once copied into the DAC
register, the data word becomes the active 12-, 10-, or
8-bit input code, and is converted to an analog voltage at
the DAC output. Write to and Update combines the first
18
two commands. The Update operation also powers up the
DAC if it had been in power-down mode. The data path
and registers are shown in the Block Diagram.
While the minimum input sequence is 24 bits, it may
optionally be extended to 32 bits to accommodate microprocessors that have a minimum word width of 16 bits
(2 bytes). To use the 32-bit width, 8 don’t-care bits must
be transferred to the device first, followed by the 24-bit
sequence described. Figure 3b shows the 32-bit sequence.
The 16-bit data word is ignored for all commands that do
not include a Write operation.
Reference Modes
For applications where an accurate external reference is
either not available, or not desirable due to limited space,
the LTC2636 has a user-selectable, integrated reference.
The integrated reference voltage is internally amplified
by 2x to provide the full-scale DAC output voltage range.
The LTC2636-LMI/-LMX/-LZ provides a full-scale DAC
output of 2.5V. The LTC2636-HMI/-HMX/-HZ provides a
full-scale DAC output of 4.096V. The internal reference
can be useful in applications where the supply voltage is
poorly regulated. Internal Reference mode can be selected
by using command 0110b, and is the power-on default
for LTC2636-HZ/-LZ, as well as for LTC2636-HMI/-LMI.
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Rev D
SDI
SCK
CS/LD
X
1
X
2
X
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X
4
X
5
C2
X
8 DON’T-CARE BITS
3
C3
SDI
2
C1
3
6
X
7
4
8
C0
X
COMMAND WORD
1
SCK
CS/LD
7
A1
ADDRESS
A2
6
A0
8
D11
9
D10
10
D9
D8
12
D7
13
D6
14
24-BIT INPUT WORD
11
D5
15
D3
17
DATA WORD
D4
16
D2
18
D1
19
C3
C2
10
C1
11
C0
12
A1
15
ADDRESS
A2
14
A0
16
32-BIT INPUT WORD
A3
13
D11
17
D10
18
D9
19
D8
20
D7
21
D6
22
D5
23
D3
25
X
21
DATA WORD
D4
24
D0
20
D2
26
X
22
D1
27
X
23
D0
28
X
24
X
29
30
X
2636 F03a
X
31
X
32
2636 F03b
OPERATION
Figure 3b. LTC2636-12 32-Bit Load Sequence.
LTC2636-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2636-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
COMMAND WORD
9
Figure 3a. LTC2636-12 24-Bit Load Sequence (Minimum Input Word).
LTC2636-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;
LTC2636-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits
A3
5
LTC2636
Rev D
19
LTC2636
OPERATION
The 10ppm/°C, 1.25V (LTC2636-LMI/-LMX/-LZ) or 2.048V
(LTC2636-HMI/-HMX/-HZ) internal reference is available
at the REF pin. Adding bypass capacitance to the REF pin
will improve noise performance; and up to 10μF can be
driven without oscillation. The REF output must be buffered when driving an external DC load current.
Alternatively, the DAC can operate in External Reference
mode using command 0111b. In this mode, an input
voltage supplied externally to the REF pin provides the
reference (1V ≤ VREF ≤ VCC) and the supply current is
reduced. The external reference voltage supplied sets the
full-scale DAC output voltage. External Reference mode is
the power-on default for LTC2636-HMX/-LMX.
The reference mode of LTC2636-HZ/-LZ/-HMI/-LMI (Internal
Reference power-on default), can be changed by software
command after power-up. The same is true for LTC2636HMX/-LMX (External Reference power-on default).
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight DAC outputs are needed. When in powerdown, the buffer amplifiers, bias circuits, and integrated
reference circuits are disabled, and draw essentially zero
current. The DAC outputs are put into a high-impedance
state, and the output pins are passively pulled to ground
through individual 200k resistors. Input- and DAC-register
contents are not disturbed during power-down.
Any DAC channel or combination of channels can be put
into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The supply current is reduced approximately 10% for each DAC
powered down. The integrated reference is automatically
powered down when external reference is selected using
command 0111b. In addition, all the DAC channels and
the integrated reference together can be put into powerdown mode using Power Down Chip command 0101b.
When the integrated reference and all DAC channels are
in power-down mode, the REF pin becomes high impedance (typically > 1GΩ). For all power-down commands
the 16- bit data word is ignored.
Normal operation resumes after executing any command
that includes a DAC update, (as shown in Table 1) or using
the asynchronous LDAC pin. The selected DAC is powered
up as its voltage output is updated. When a DAC which
is in a powered-down state is powered up and updated,
normal settling is delayed. If less than eight DACs are in
a powered-down state prior to the update command, the
power-up delay time is 10μs. However, if all eight DACs
and the integrated reference are powered down, then the
main bias generation circuit block has been automatically
shut down in addition to the DAC amplifiers and reference buffers. In this case, the power up delay time is
12μs. The power-up of the integrated reference depends
on the command that powered it down. If the reference
is powered down using the Select External Reference
Command (0111b), then it can only be powered back
up using Select Internal Reference Command (0110b).
However, if the reference was powered down using Power
Down Chip Command (0101b), then in addition to Select
Internal Reference Command (0110b), any command (in
software or using the LDAC pin) that powers up the DACs
will also power up the integrated reference.
Voltage Outputs
The LTC2636’s integrated rail-to-rail amplifiers have guaranteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to ohms. The amplifier’s DC output
impedance is 0.1Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage
is 50Ω • 1mA, or 50mV). See the graph “Headroom at
Rev D
20
For more information www.analog.com
LTC2636
OPERATION
VREF = VCC
POSITIVE
FSE
VREF = VCC
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
INPUT CODE
(c)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
0V
0
2,048
INPUT CODE
(a)
2636 F04
4,095
INPUT CODE
(b)
Figure 4. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits).
(a) Overall Transfer Function
(b) Effect of Negative Offset for Codes Near Zero
(c) Effect of Positive Full-Scale Error for Codes Near Full-Scale
Rails vs. Output Current” in the Typical Performance
Characteristics section.
The amplifier is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited to voltages within the supply range.
Since the analog output of the DAC cannot go below
ground, it may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full-scale
when the REF pin is tied to VCC. If VREF = VCC and the
DAC full-scale error (FSE) is positive, the output for the
highest codes limits at VCC, as shown in Figure 4c. No
full-scale limiting can occur if VREF is less than VCC–FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog
and digital sections of the circuit. A single, solid ground
plane should be used, with analog and digital signals carefully routed over separate areas of the plane. This keeps
digital signals away from sensitive analog signals and
minimizes the interaction between digital ground currents
and the analog section of the ground plane. The resistance
from the LTC2636 GND pin to the ground plane should
be as low as possible. Resistance here will add directly to
the effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2636 is no more susceptible to
this effect than any other parts of this type; on the contrary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
Another technique for minimizing errors is to use a separate power ground return trace on another board layer.
The trace should run between the point where the power
supply is connected to the board and the DAC ground pin.
Thus the DAC ground pin becomes the common point for
analog ground, digital ground, and power ground. When
the LTC2636 is sinking large currents, this current flows
out the ground pin and directly to the power ground trace
without affecting the analog ground plane voltage.
It is sometimes necessary to interrupt the ground plane
to confine digital ground currents to the digital portion of
the plane. When doing this, make the gap in the plane only
as long as it needs to be to serve its purpose and ensure
that no traces cross over the gap.
Rev D
For more information www.analog.com
21
LTC2636
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2636#packaging for the most recent package drawings.
DE Package
14-Lead Plastic DFN (4mm
3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
4.00 0.10
(2 SIDES)
R = 0.05
TYP
0.70 0.05
3.30 0.05
3.60 0.05
2.20 0.05
PACKAGE
OUTLINE
1.70 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 45
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DE14) DFN 0806 REV B
7
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
0.25 0.05
0.50 BSC
0.40 0.10
14
3.30 0.10
3.00 0.10
(2 SIDES)
1.70 0.05
R = 0.115
TYP
8
3.00 REF
3.00 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev A)
4.039 0.102
(.159 .004)
(NOTE 3)
0.889 0.127
(.035 .005)
5.10
(.201)
MIN
0.280 0.076
(.011 .003)
REF
16151413121110 9
0.254
(.010)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
0 – 6 TYP
GAUGE PLANE
0.305 0.038
(.0120 .0015)
TYP
0.53 0.152
(.021 .006)
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
1234567 8
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.1016 0.0508
(.004 .002)
MSOP (MS16) 0213 REV A
Rev D
22
For more information www.analog.com
LTC2636
REVISION HISTORY
REV
DATE
DESCRIPTION
A
12/09
Update Electrical Characteristics.
B
06/10
PAGE NUMBER
5, 6, 8
Added details to Note 3.
9
Revised Typical Applications circuit.
24
C
05/17
Changed VCC slew rate number in Note 3.
9
D
04/18
Edits to Note 3.
9
Rev D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
moreby
information
www.analog.com
23
LTC2636
TYPICAL APPLICATION
LTC2636 DACs Adjust LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V
5V
15
15V
0.1µF
8
7
VDD
LTC2755-16
+
5
IOUT1A 59
63 RCOM1
DAC A
1/2 LT1469
4
–
IOUT2A 2
6
0.1µF
15V
RFBA 60
0.1µF 61 ROFSA
64 RIN1
2
3
–
8
1/2 LT1469
+
LT1634-1.25
DAC D
3
1
0.1µF
LTC2636DE-LMI12
DAC A
DAC H
DAC B
DAC G
13
–
+
DAC C
DAC B
30k
OUTB
+
–
GND
1 P1
2 P3
3 P9
0.1µF
7
VCC
LT1991
OUT
6
VOUT = ±5V
REF
VEE
5
4
0.1µF
–15V
4
DAC C
DAC F
DAC D
DAC E
11
–15V
5
30k
8 M9
9 M3
10 M1
12
LT1634-1.25
–15V
LT1634-1.25
VCC
LT1634-1.25
30k
OUTC
REF
0.1µF
2
30k
–15V
5V
9
0.1µF
–15V
+
–
OUTD
OUTA
4
–15V
LT6240
15V
1
RVOSA 58
62 REFA
+
–
0.1µF
19
–15V
SERIAL
BUS
6
CS/LD
7
SCK
8
SDI
10
GND
14
2636 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1660/LTC1665
Octal 10/8-Bit VOUT DACs in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC1664
Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
LTC2600/LTC2610/ Octal 16-/14-/12-Bit VOUT DACs in 16-Lead Narrow SSOP
LTC2620
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2601/LTC2611/ Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN
LTC2621
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2602/LTC2612/ Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP
LTC2622
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2604/LTC2614/ Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP
LTC2624
250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,
SPI Serial Interface
LTC2605/LTC2615/ Octal 16-/14-/12-Bit VOUT DACs with I2C Interface
LTC2625
250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
I2C Interface
LTC2606/LTC2616/ Single 16-/14-/12-Bit VOUT DACs with I2C Interface
LTC2626
270μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output,
I2C Interface
LTC2609/LTC2619/ Quad 16-/14-/12-Bit VOUT DACs with I2C Interface
LTC2629
250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output with
Separate VREF Pins for Each DAC
LTC2630
Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference
in SC70
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Rail-to-Rail Output, SPI Interface
LTC2631
Single 12-/10-/8-Bit I2C VOUT DACs with 10ppm/°C
Reference in ThinSOT
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Selectable External Ref. Mode, Rail-to-Rail Output, I2C Interface
LTC2640
Single 12-/10-/8-Bit VOUT DACs with 10ppm/°C Reference
in ThinSOT
180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,
Selectable External Ref. Mode, Rail-to-Rail Output, SPI Interface
Rev D
24
D16868-0-5/18(D)
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