LTC2927
Single Power Supply
Tracking Controller
DESCRIPTIO
U
FEATURES
n
n
n
n
n
n
n
n
n
The LTC®2927 provides a simple solution to power supply
tracking and sequencing requirements. By selecting a few
resistors, the supply can be configured to ramp-up and
ramp-down with differing ramp rates, voltage offsets, or
time delays relative to other supplies or a master signal.
Flexible Power Supply Tracking
Tracks Both Up and Down
Power Supply Sequencing
Supply Stability is Not Affected
Low Pin Count
Controls Single Supply without Series FETs
Adjustable Ramp Rate
Supply Shutdown Output
Available in 8-Lead ThinSOT™ and 8-Lead
(3mm × 2mm) DFN Packages
By forcing current into a feedback node of an independent
supply, the LTC2927 causes the output to track a ramp
signal without inserting any pass element losses. Because
the current is controlled in an open-loop manner, the
LTC2927 does not affect the transient response or stability of the supply. The compact solution at point of load
minimizes the trace length of the DC/DC circuit sensitive
FB node. Furthermore, it presents a high impedance when
power-up is complete, effectively removing it from the
DC/DC circuit.
U
APPLICATIO S
n
n
n
n
VCORE and VI/O Supply Tracking
Microprocessor, DSP and FPGA Supplies
Multiple Supply Systems
Point-of-Load Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Patents Pending.
U
TYPICAL APPLICATIO
Track-Up and Track-Down Waveforms
EARLY VIN
3.3V
0.1μF
138k
VCC
ON
100k
RAMP
SDO
RUN/SS
RAMP
(3.3V)
IN
2.5V
1.8V
1V/DIV
DC/DC
RAMPBUF
FB
16.5k
VIN
0.1μF
LTC2927
FB = 1.235V
OUT
1.8V
TRACK
GND
13k
35.7k
16.5k
10ms/DIV
EARLY VIN
3.3V
2927 TA01b
0.1μF
VCC
ON
RAMP
VIN
RAMP
(3.3V)
IN
2.5V
1.8V
LTC2927
SDO
RUN/SS
RAMPBUF
FB
887k
1V/DIV
DC/DC
FB = 0.8V
OUT
2.5V
TRACK
412k
GND
412k
2927 TA01a
887k
10ms/DIV
2927 TA01c
2927fb
1
LTC2927
U
W W
W
ABSOLUTE
AXI U RATI GS (Note 1)
Supply Voltage (VCC) ................................. –0.3V to 10V
Input Voltages
ON ......................................................... –0.3V to 10V
TRACK .........................................–0.3V to VCC + 0.3V
Output Voltages
FB, SDO ................................................. –0.3V to 10V
RAMP, RAMPBUF .........................–0.3V to VCC + 0.3V
Average Current
TRACK .................................................................5mA
FB ........................................................................5mA
RAMPBUF ............................................................5mA
Operating Temperature Range
LTC2927C ................................................ 0°C to 70°C
LTC2927I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
ON 1
RAMP 2
RAMPBUF 3
TRACK 4
8 VCC
9
VCC 1
SDO 2
FB 3
GND 4
7 SDO
6 FB
5 GND
8 ON
7 RAMP
6 RAMPBUF
5 TRACK
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
TJMAX = 125°C, θJA = 250°C/W
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
EXPOSED PAD (PIN 9) PCB GND, CONNECTION OPTIONAL
TJMAX = 125°C, θJA = 76°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2927CDDB#PBF
LTC2927CDDB#TRPBF
LBQH
8-Lead (3mm × 2mm) Plastic DFN
0°C to 70°C
LTC2927IDDB#PBF
LTC2927IDDB#TRPBF
LBQH
8-Lead (3mm × 2mm) Plastic DFN
–40°C to 85°C
LTC2927CTS8#PBF
LTC2927CTS8#TRPBF
LTBQJ
8-Lead Plastic TSOT-23
0°C to 70°C
LTC2927ITS8#PBF
LTC2927ITS8#TRPBF
LTBQJ
8-Lead Plastic TSOT-23
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2927CDDB
LTC2927CDDB#TR
LBQH
8-Lead (3mm × 2mm) Plastic DFN
0°C to 70°C
LTC2927IDDB
LTC2927IDDB#TR
LBQH
8-Lead (3mm × 2mm) Plastic DFN
–40°C to 85°C
LTC2927CTS8
LTC2927CTS8#TR
LTBQJ
8-Lead Plastic TSOT-23
0°C to 70°C
LTC2927ITS8
LTC2927ITS8#TR
LTBQJ
8-Lead Plastic TSOT-23
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2927fb
2
LTC2927
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. 2.9V < VCC < 5.5V unless otherwise noted (Note 2).
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
CONDITIONS
VCC(UVLO)
Supply Undervoltage Lockout
ΔVCC(UVHYST)
Supply Undervoltage Lockout Hysteresis
VON(TH)
ON Pin Threshold Voltage
ΔVON(HYST)
ON Pin Hysteresis
ION
ON Pin Input Current
IRAMP
RAMP Pin Input Current
MIN
TYP
MAX
UNITS
l
2.9
5.5
V
IFB = 0mA, ITRACK = 0mA
l
0.25
0.56
1.2
mA
IFB = –1mA, ITRACK = –1mA, IRAMPBUF = –1mA
l
3
3.6
4.2
mA
VCC Rising
l
2.2
2.5
2.7
V
VON Rising
l
1.210
1.230
1.250
l
30
75
150
mV
0
±100
nA
25
l
VON = 1.2V, VCC = 5.5V
mV
V
0V < VRAMP < VCC, Ramp On
–9
–10
–11
μA
0V < VRAMP < VCC, Ramp Off
9
10
11
μA
VRAMPBUF(OL)
RAMPBUF Output Low Voltage
IRAMPBUF = 1mA
l
20
100
mV
VRAMPBUF(OH)
RAMPBUF Output High Voltage,
VRAMPBUF(OH) = VCC – VRAMPBUF
IRAMPBUF = –1mA
l
45
150
mV
VOS
Ramp Buffer Offset,
VOS = VRAMPBUF – VRAMP
VRAMP = VCC/2, IRAMPBUF = 0mA
0
30
mV
IFB to ITRACK Current Mismatch
ITRACK = –10μA
l
0
±5
%
IERROR(%) = (IFB – ITRACK)/ITRACK
ITRACK = –1mA
l
0
±5
%
IERROR(%)
TRACK Pin Voltage
VTRACK
–30
ITRACK = –10μA
l
0.77
0.800
0.82
V
ITRACK = –1mA
l
0.77
0.800
0.82
V
VFB = 2V, VCC = 5.5V
l
±1
±100
nA
IFB(LEAK)
FB Pin Leakage Current
VFB(CLAMP)
FB Pin Clamp Voltage
1μA < IFB < 1mA
l
VSDO(OL)
SDO Output Low Voltage
ISDO = 1mA, VCC = 2.3V
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
1.5
2
2.3
V
0.1
0.4
V
Note 2: All currents into the device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
TYPICAL PERFORMANCE CHARACTERISTICS
ITRACK = IFB = 0mA
IRAMBUF = 0mA
700
4.65
650
4.60
ICC (mA)
ICC (μA)
ICC vs VCC
4.70
600
4.55
550
4.50
500
2.5
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
2927 G01
4.45
VTRACK vs Temperature
820
ITRACK = IFB = –1mA
IRAMBUF = –2mA
810
VTRACK (mV)
ICC vs VCC
750
800
790
780
2.5
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
2927 G02
770
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
2927 G03
2927fb
3
LTC2927
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VON(TH) vs Temperature
VRAMPBUF(OL) vs Temperature
1.240
VRAMPBUF(OH) vs Temperature
70
28
26
1.235
65
VON(TH) (V)
1.230
1.225
1.220
VRAMPBUF(OH) (mV)
VRAMPBUF(OL) (mV)
24
22
20
18
16
60
55
50
14
1.215
45
12
1.210
–50
–25
0
25
50
TEMPERATURE (°C)
75
10
–50
100
VTRACK = 0V
ERROR =
40
–50
100
30
20
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
VTRACK
I
• FB –1
0.8V
ITRACK
100
2927 G06
0.8
3
2
0
75
VSDO(OL) vs VCC
1
2.5
0
25
50
TEMPERATURE (°C)
1.0
VSDO(OL) (V)
40
–25
2927 G05
4
ERROR (%)
ITRACK (mA)
75
Tracking Cell Error vs ITRACK
5
50
10
0
25
50
TEMPERATURE (°C)
2927 G04
MAX ITRACK vs VCC
60
–25
0.6
ISDO = 5mA
0.4
0.2
1
2
2927 G07
3
ITRACK (mA)
4
5
2927 G0
0.0
ISDO = 10μA
0
1
2
3
VCC (V)
4
5
2927 G0
PIN FUNCTIONS TSOT/DFN Packages
VCC (Pin 1/Pin 8): Supply Voltage Input. Operating range
is from 2.9V to 5.5V. An undervoltage lockout asserts SDO
until VCC > 2.5V. VCC should be bypassed to GND with a
0.1μF capacitor.
SDO (Pin 2/Pin 7): Slave Supply Shutdown Output. SDO
is an open-drain output that holds the shutdown (RUN/SS)
pin of the slave supply low until the VCC pin is pulled above
2.5V, and the ON pin is pulled above 1.23V, or RAMP is
above 200mV. SDO is pulled low again when both RAMP
< 200mV and ON < 1.23V. If the slave supply is capable
of operating with an input supply that is lower than the
LTC2927’s minimum operating voltage of 2.9V, the SDO
pin can be used to hold off the slave supply. Tie the SDO
pin to GND if unused.
FB (Pin 3/Pin 6): Feedback Control Output. FB pulls up
on the feedback node of the slave supply. Tracking is
achieved by mirroring the current from TRACK into FB.
A resistive divider connecting RAMPBUF and TRACK will
force the output voltage of the slave supply to track RAMP.
To prevent damage to the slave supply, the FB pin will not
force the slave’s feedback node above 2.3V. In addition,
the LTC2927 will not actively sink current from this node,
even when it is unpowered.
2927fb
4
LTC2927
U
U
U
PI FU CTIO S TSOT/DFN Packages
GND (Pin 4/Pin 5): Device Ground.
RAMP (Pin 7/Pin 2): Ramp Buffer Input. The RAMP pin is
the input to the voltage buffer whose output drives a resistive voltage divider connected to the TRACK pin. Connect
this input to a capacitor to set the ramp voltage generated
from internal 10μA pull-up or pull-down currents. RAMP
can also be connected to an external ramping signal for
tracking. Ground RAMP if unused.
TRACK (Pin 5/Pin 4): Tracking Control Input. A resistive
voltage divider between RAMPBUF and TRACK determines
the tracking profile of the slave supply. TRACK servos to
0.8V, and the current supplied at TRACK is mirrored at FB.
The TRACK pin is capable of supplying at least 1mA when
VCC = 2.9V. Under short circuit conditions, the TRACK pin
is capable of supplying up to 70mA. Do not connect to
GND for extended periods. Limit the capacitance at the
TRACK pin to less than 25pF.
ON (Pin 8/Pin 1): On Control Input. The voltage level of
the ON pin relative to its 1.23V threshold (with 75mV
hysteresis) controls the tracking direction of the LTC2927.
An active high causes a 10μA pull-up current to flow at
the RAMP pin, which charges an external capacitor. An
active low at the ON pin causes a 10μA pull-down current at the RAMP pin to discharge the external capacitor
relative to GND.
RAMPBUF (Pin 6/Pin 3): Ramp Buffer Output. Provides
a low impedance buffered version of the signal on the
RAMP pin. This buffered output drives the resistive voltage divider that connects to the TRACK pin. Limit the
capacitance at the RAMPBUF pin to less than 100pF. Float
RAMPBUF if unused.
Exposed Pad (NA/Pin 9): Exposed pad may be left open
or connected to device ground.
W
FU CTIO AL BLOCK DIAGRA
U
5
5
VCC
RAMPBUF
RAMP
1x
5
VCC
5
ON
1.23V
10μA
+
–
10μA
–
+
2.5V
0.2V
SDO
5
+
UVLO
VCC
–
VCC
+
0.8V
–
5
TRACK
FB
5
GND
5
2927 BD
2927fb
5
U
LTC2927
U
W
U
U
APPLICATIO S I FOR ATIO
Power Supply Tracking and Sequencing
The LTC2927 handles a variety of power-up profiles to
satisfy the requirements of digital logic circuits including
FPGAs, PLDs, DSPs and microprocessors. These requirements fall into one of the four general categories illustrated
in Figures 1 to 4.
Some applications require that the potential difference
between two power supplies must never exceed a specified voltage. This requirement applies during power-up
and power-down as well as during steady-state operation,
often to prevent destructive latch-up in a dual supply
ASIC. Typically, this is achieved by ramping the supplies
up and down together (Figure 1). In other applications it
is desirable to have supplies ramp up and down with fixed
voltage offsets between them (Figure 2) or to have them
ramp up and down ratiometrically (Figure 3).
Certain applications require one supply to come up after
another. For example, a system clock may need to start
before a block of logic. In this case, the supplies are sequenced as in Figure 4 where the 2.5V supply ramps up
after the 1.8V supply is completely powered.
Operation
The LTC2927 provides a simple solution to all of the
power supply tracking and sequencing profiles shown in
Figures 1 to 4. A single LTC2927 controls a single supply that tracks to a “master” signal. With two resistors,
a slave supply is configured to ramp up as a function of
the master signal. This master signal can be a separate
supply or it can be a ramp signal generated by tying the
RAMP pin to an external capacitor.
Tracking Cell
The LTC2927’s operation is based on the tracking cell
shown in Figure 5, which uses a proprietary wide-range
current mirror. The tracking cell shown in Figure 5 servos
the TRACK pin at 0.8V. The current supplied by the TRACK
MASTER
MASTER
SLAVE1
SLAVE1
1V/DIV
SLAVE2
10ms/DIV
1V/DIV
2927 F01
SLAVE2
10ms/DIV
Figure 1. Coincident Tracking
2927 F02
Figure 2. Offset Tracking
MASTER
MASTER
SLAVE1
SLAVE2
1V/DIV
10ms/DIV
Figure 3. Ratiometric Tracking
2927 F03
SLAVE1
1V/DIV
SLAVE2
10ms/DIV
2927 F04
Figure 4. Supply Sequencing
2927fb
6
LTC2927
U
U
W
U
APPLICATIO S I FOR ATIO
pin is mirrored at the FB pin to establish a voltage at the
output of the slave supply. The slave output voltage varies
with the master signal, enabling the slave supply to be
controlled as a function of the master signal with terms
set by RTA and RTB. By selecting appropriate values of
RTA and RTB, it is possible to generate any of the profiles
in Figures 1 to 4.
Controlling the Ramp-Up and Ramp-Down Behavior
The operation of the LTC2927 is most easily understood
by referring to the simplified functional diagram in Figure
6. When the ON pin is low, the master signal at the RAMP
pin is pulled to ground. Since the current through RTB is
at its maximum when the master signal is low, the current
from FB is also at its maximum. This current drives the
slave output to its minimum voltage.
When the ON pin rises above 1.23V, the master signal
rises and the slave supply tracks the master signal. The
ramp rate is set by an external capacitor driven by a 10μA
current source at the RAMP pin. Alternatively, the RAMP
pin can be connected to a separate supply to be used as
the master signal.
In a properly designed system, when the master signal
has reached its maximum voltage the current from the
TRACK pin is zero. In this case, there is no current from
the FB pin and the LTC2927 has no effect on the output
voltage accuracy, transient response or stability of the
slave supply.
When the ON pin falls below VON(TH) – ΔVON(HYST), typically 1.225V, the RAMP pin pulls down with 10μA and the
master signal and slave supplies will fall at the same rate
as they rose previously.
The ON pin can be controlled by a digital I/O pin or it
can be used to monitor an input supply. By connecting a
resistive divider from an input supply to the ON pin, the
supplies will ramp up only after the monitored supply has
reached a preset voltage.
If a resistive divider is used to set the ON pin voltage, choose
values that will keep this voltage above the maximum ON
pin threshold voltage of 1.25V at the lowest operating
supply level.
The Ramp Buffer
The RAMPBUF pin provides a buffered version of the
RAMP pin voltage that drives the resistive divider on the
TRACK pin. The buffered master signal provides up to
2mA to drive the resistors.
Shutdown Output
In some applications it might be necessary to control
the shutdown or RUN/SS pins of the slave supplies. The
LTC2927 may not be able to supply the rated 1mA of current
from the FB pin when VCC is below 2.9V. If the slave power
supply is capable of operating at low input voltages, use
the open-drain SDO output to drive the SHDN or RUN/SS
pin of the slave supply (see Figure 7). This will hold the
slave supply output low until the ON pin is above 1.23V
and VCC is above the 2.5V undervoltage lockout condition.
VCC
5
RONB
5
10μA
ON
+
RONA
1.2V
–
10μA
5
RAMPBUF
+
+
–
MASTER
0.8V
0.8V
–
–
RTB
DC/DC
TRACK
MASTER
VCC
+
5
5
CRAMP
VCC
RTB
RAMP
1x
FB
5
FB OUT
5
SLAVE
TRACK
FB
5
DC/DC
SLAVE
RTA
RTA
2927 F05
RFA
Figure 5. Simplified Tracking Cell
RFB
5
2927 F06
RFA
RFB
Figure 6. Simplified Functional Diagram
2927fb
7
LTC2927
U
U
W
U
APPLICATIO S I FOR ATIO
EARLY
VIN
3.3V
Choose a ramp rate for the slave supply, SS. If the slave
supply ramps up coincident with the master signal or
with a fixed voltage offset, then the ramp rate equals
the master supply’s ramp rate. Be sure to use a fast
enough ramp rate for the slave supply so that it will finish
ramping before the master signal has reached its final
supply value. If not, the slave supply will be held below
the intended regulation value by the master signal. Use
the following formulas to determine the resistor values
for the desired ramp rate, where RFB and RFA are the
feedback resistors in the slave supply and VFB is the
feedback reference voltage of the slave supply:
0.1μF
RONB
138k
VCC
ON
RAMP
RONA
100k
MASTER
CRAMP
10pF
LTC2927
SDO
RUN/SS
IN
DC/DC
RAMPBUF
RTB
16.5k
VIN
FB
FB = 1.235V
OUT
1.8V
TRACK
RTA
13k
GND
2927 F07
RFA
35.7k
RFB
16.5k
Figure 7. SDO Shutdown Application
SDO pulls low again when the ON pin is pulled below 1.23V
and the RAMP pin is below about 200mV.
RTB = RFB •
SM
SS
3-Step Design Procedure
RTA′ =
VTRACK
V
V
+ FB − TRACK
RFA
RTB
The following 3-step procedure allows one to complete
a design for any of the tracking or sequencing profiles
shown in Figures 1 to 4. A basic single supply application
circuit is shown in Figure 8.
1. Set the ramp rate of the master signal.
Solve for the value of CRAMP, the capacitor on the RAMP
pin, based on the desired ramp rate (V/s) of the master
supply, SM.
C RAMP =
IRAMP
where IRAMP ≈ 10μA
SM
(1)
2. Solve for the pair of resistors that provide the desired
ramp rate of the slave supply, assuming no delay.
EARLY
VIN
RONB
VCC
ON
RAMP
LTC2927
VIN
3. Choose RTA to obtain the desired delay.
If no delay is required, such as in coincident and ratiometric tracking, then simply set RTA = RTA’. If a delay
is desired, as in offset tracking and supply sequencing,
calculate RTA” to determine the value of RTA where tD
is the desired delay in seconds.
FB
RTB
FB
OUT
TRACK
GND
RFA
VTRACK • RTB
tD • SM
(4)
(5)
the parallel combination of RTA’ and RTA”.
IN
DC/DC
RAMPBUF
RTA
Note that large ratios of slave ramp rate to master ramp
rate, SS/SM, may result in negative values for RTA’. If
sufficiently large delay is used in step 3, RTA will be
positive, otherwise SS/SM must be reduced.
RTA = RTA′ || RTA ″
MASTER
CRAMP
RONA
(3)
where VTRACK ≈ 0.8V.
RTA ″ =
0.1μF
VFB
RFB
(2)
RFB
2927 F08
Figure 8. Single Supply Application
SLAVE
As noted in step 2, small delays and large ratios of slave ramp
rate to master ramp rate (usually only seen in sequencing)
may result in solutions with negative values for RTA. In such
cases, either the delay must be increased or the ratio of
slave ramp rate to master ramp rate must be reduced.
2927fb
8
LTC2927
U
W
U
U
APPLICATIO S I FOR ATIO
Coincident Tracking Example
MASTER
SLAVE2
1V/DIV
1V/DIV
SLAVE1
2927 F09
10ms/DIV
10ms/DIV
Figure 9. Coincident Tracking (from Figure 10)
A typical application is shown in Figure 10. The master
signal is a 3.3V ramp generated by the LTC2927. The
slave 1 supply is a 1.8V switching power supply and the
slave 2 supply is a 2.5V switching power supply. Both
slave supplies track coincidently with the 3.3V ramping
master signal. The ramp rate of the supplies is 100V/s.
The 3-step design procedure detailed previously can be
used to determine component values. Only the slave 1
supply is considered here as the procedure is the same
for the slave 2 supply.
1. Set the ramp rate of the master signal.
From Equation 1:
C RAMP
In this example, the supply remains low while the ON pin
is held below 1.23V. When the ON pin rises above 1.23V,
10μA pulls up the master signal on CRAMP at 100V/s.
The master signal is buffered from the RAMP pin to the
RAMPBUF pin. As this output and the RAMPBUF pin rise,
the current from the TRACK pin is reduced. Consequently,
the voltage at the slave supply’s output is increased, and
the slave supply tracks the master signal. When the ON
pin is again pulled below 1.23V, 10μA will pull down CRAMP
at 100V/s. If the loads on the outputs are sufficient, all
outputs will track down coincidently at 100V/s.
EARLY VIN
3.3V
10μA
=
= 0.1μF
100V / s
ON
0.1μF
LTC2927
SDO
RTB1
16.5k
RUN/SS
3. Choose RTA to obtain desired delay.
Since no delay is desired, RTA = RTA’
IN
DC/DC
FB
FB = 1.235V
RTA1
13k
RFA1
35.7k
GND
EARLY
3.3V
OUT
SLAVE1
1.8V
OUT
SLAVE2
2.5V
RFB1
16.5k
0.1μF
VCC
ON
RAMP
3.3V
LTC2927
0.8V
≈ 13kΩ
1.235V 1.235V
0.8V
+
−
16.5kΩ 35.7kΩ 16.5kΩ
3.3V
TRACK
From Equation 3:
RTA′ =
MASTER
3.3V
RAMP
RAMPBUF
From Equation 2:
100V / s
= 16.5kΩ
100V / s
VCC
RONA
100k
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
RTB = 16.5kΩ •
0.1μF
RONB
138k
SDO
RUN/SS
RTB2
887k
IN
DC/DC
RAMPBUF
FB
FB = 0.8V
TRACK
RTA2
412k
GND
2927 F10
RFA2
412k
RFB2
887k
Figure 10. Coincident Tracking Example
2927fb
9
LTC2927
U
W
U
U
APPLICATIO S I FOR ATIO
Ratiometric Tracking Example
MASTER
SLAVE2
SLAVE1
1V/DIV
1V/DIV
10ms/DIV
2927 F11
10ms/DIV
Figure 11. Ratiometric Tracking (from Figure 12)
This example converts the coincident tracking example to
the ratiometric tracking profile shown in Figure 11. The
ramp rate of the master signal remains unchanged (Step
1) and there is no delay in ratiometric tracking (Step 3),
so only the result of step 2 in the 3-step design procedure
needs to be considered. In this example, the ramp rate of the
1.8V slave 1 supply ramps up at 60V/s and the 2.5V slave 2
supply ramps up at 85V/s. Always verify that the chosen
ramp rate will allow the supplies to ramp-up completely
before RAMPBUF reaches VCC. If the 1.8V supply were
to ramp-up at 50V/s it would only reach 1.65V because
the RAMPBUF signal would reach its final value of VCC =
3.3V before the slave supply reached 1.8V.
EARLY VIN
3.3V
VCC
ON
RONA
100k
MASTER
3.3V
RAMP
0.1μF
LTC2927
SDO
RTB1
27.4k
3.3V
RUN/SS
IN
DC/DC
RAMPBUF
FB
FB = 1.235V
OUT
SLAVE1
1.8V
OUT
SLAVE2
2.5V
TRACK
RTA1
10k
RFA1
35.7k
GND
EARLY
3.3V
RFB1
16.5k
0.1μF
VCC
ON
RAMP
3.3V
LTC2927
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
From Equation 2:
0.1μF
RONB
138k
SDO
RUN/SS
RTB2
1M
IN
DC/DC
RAMPBUF
FB
FB = 0.8V
TRACK
RTB
100V / s
= 16.5kΩ •
= 27.4kΩ
60V / s
From Equation 3:
RTA′ =
RTA2
383k
GND
2927 F12
RFA2
412k
RFB2
887k
Figure 12. Ratiometric Tracking Example
0.8V
≈ 10kΩ
1.235V 1.235V
0.8V
+
−
16.5kΩ 35.7kΩ 27.4kΩ
Step 3 is unnecessary because there is no delay, so
RTA = RTA’
2927fb
10
LTC2927
U
W
U
U
APPLICATIO S I FOR ATIO
Offset Tracking Example
MASTER
SLAVE2
1V/DIV
1V/DIV
SLAVE1
10ms/DIV
2927 F13
10ms/DIV
Figure 13. Offset Tracking (from Figure 14)
Converting the circuit in the coincident tracking example
to the offset tracking shown in Figure 13 is relatively
simple. Here the 1.8V slave 1 supply ramps up 1V below
the master. The ramp rate remains the same (100V/s), so
there are no changes necessary to steps 1 and 2 of the
3-step design procedure. Only step 3 must be considered.
Be sure to verify that the chosen voltage offset will allow
the slave supply to ramp up completely. In this example,
if the voltage offset were 2V, the slave supply would only
ramp to 3.3V – 2V = 1.3V.
EARLY VIN
3.3V
0.1μF
RONB
138k
VCC
ON
RONA
100k
RAMP
0.1μF
LTC2927
SDO
FB
RTA1
6.65k
RTA ″ =
0.8V • 16.5kΩ
= 13.2kΩ
10ms • 100V / s
FB = 1.235V
RFA1
35.7k
GND
OUT
SLAVE1
1.8V
OUT
SLAVE2
2.5V
RFB1
16.5k
0.1μF
VCC
ON
RAMP
3.3V
LTC2927
SDO
From Equation 4:
IN
TRACK
First, convert the desired voltage offset, VOS, to a delay
tD, using the ramp rate:
1V
V
t D = OS =
= 10ms
S S 100 V / s
MASTER
3.3V
DC/DC
EARLY
3.3V
3. Choose RTA to obtain desired delay.
RUN/SS
RAMPBUF
RTB1
16.5k
3.3V
(6)
RUN/SS
RTB2
887k
IN
DC/DC
RAMPBUF
FB
FB = 0.8V
TRACK
RTA2
316k
GND
2927 F14
RFA2
412k
RFB2
887k
Figure 14. Offset Tracking Example
From Equation 5:
RTA = 13.1kΩ 13.2kΩ ≈ 6.65kΩ
2927fb
11
LTC2927
U
W
U
U
APPLICATIO S I FOR ATIO
Supply Sequencing Example
MASTER
SLAVE2
1V/DIV
1V/DIV
SLAVE1
10ms/DIV
2927 F15
10ms/DIV
Figure 15. Supply Sequencing (from Figure 16)
In Figure 15, the slave 1 supply and the slave 2 supply are
sequenced instead of tracking. The 3.3V master ramps up
at 100V/s. The 1.8V slave 1 supply ramps up at 1000V/s
beginning 10ms after the master signal starts to ramp up.
The 2.5V slave 2 supply ramps up at 1000V/s beginning
25ms after the master signal begins to ramp up. Note
that not every combination of ramp rates and delays is
possible. Small delays and large ratios of slave ramp rate
to master ramp rate may result in solutions that require
negative resistors. In such cases, either the delay must
be increased or the ratio of slave ramp rate to master
ramp rate must be reduced. In this example, solving for
the slave supply yields:
3. Choose RTA to obtain desired delay.
From Equation 4:
RTA ″ =
From Equation 5:
RTA = −2.13kΩ 1.32kΩ = 3.48kΩ
EARLY VIN
3.3V
VCC
ON
RTA′ =
0.8V
= −2.13kΩ
1.235V 1.235V
0.8V
+
−
16.5kΩ 35.7kΩ 1.65kΩ
IN
DC/DC
FB
FB = 1.235V
OUT
SLAVE1
1.8V
OUT
SLAVE2
2.5V
TRACK
RTA1
3.48k
RFA1
35.7k
GND
EARLY
3.3V
RFB1
16.5k
0.1μF
VCC
100V / s
= 16.5kΩ •
= 1.65kΩ
1000V / s
From Equation 3:
3.3V
RUN/SS
RAMPBUF
ON
RTB
0.1μF
LTC2927
RTB1
1.65k
10μA
= 0.1μF
100V / s
MASTER
3.3V
RAMP
SDO
From Equation 1:
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
0.1μF
RONB
138k
RONA
100k
1. Set the ramp rate of the master signal.
C RAMP =
0.8V • 1.65kΩ
= 1.32kΩ
10ms • 100V / s
RAMP
3.3V
LTC2927
SDO
RUN/SS
RTB2
88.7k
IN
DC/DC
RAMPBUF
FB
FB = 0.8V
TRACK
RTA2
36.5k
GND
2927 F16
RFA2
412k
RFB2
887k
Figure 16. Supply Sequencing Example
2927fb
12
LTC2927
U
W
U
U
APPLICATIO S I FOR ATIO
Final Sanity Checks
The collection of equations below is useful for identifying
unrealizable solutions.
As stated in step 2, the slave supply must finish ramping
before the master signal has reached its final voltage. This
can be verified by the following equation:
⎛ R ⎞
VTRACK ⎜ 1+ TB ⎟ < VMASTER
⎝ RTA ⎠
Here, VTRACK = 0.8V. VMASTER is the final voltage of the
master signal (VCC if RAMP pin).
It is possible to choose resistor values that require the
LTC2927 to supply more current than the Electrical Characteristics table guarantees. To avoid this condition, check
that ITRACK does not exceed 1mA and IRAMPBUF does not
exceed ±2mA.
To confirm that ITRACK < 1mA, the TRACK pin’s maximum
guaranteed current, verify that:
VTRACK
< 1mA
RTA RTB
Finally, check that the RAMPBUF pin will not be forced to
sink more than 2mA when it is at 0V or be forced to source
more than 2mA when it is at VMASTER.
VTRACK
V
< 2mA and MASTER < 2mA
RTB
RTA + RTB
RONB 2.9V
<
–1
RONA 1.21V
For example, if the typical application shown on page 1
has a 3.3V ±10% VIN, the lowest possible operating supply
voltage will be 2.97.
RONB 2.97V
>
– 1 = 1.376
RONA 1.25V
If RONA is 100k then RONB must be greater than 137.6k.
Therefore, 138k is chosen. These values must be checked
to ensure the supply reaches the LTC2927 minimum operating supply voltage of 2.9V before the ON pin is above
the minimum threshold.
1.38 <
2.9V
– 1= 1.389
1.21V
Load Requirements
When the supply is ramped down quickly, either the load
or the supply itself must be capable of sinking enough
current to support the ramp rate. For example, if there
is a large output capacitance on the supply and a weak
resistive load, supplies that do not sink current will have
their falling ramp rate limited by the RC time constant of
the load and the output capacitance. Figure 17 shows the
case when the slave supply does not track the master
near ground.
ON Pin Resistive Divider
MASTER
Check that the ON pin voltage is above the 1.25V maximum
threshold at the lowest possible supply voltage value.
RONB VCC(MIN)
<
–1
RONA
1.25V
Also check that the supply voltage is above the minimum
LTC2927 operating supply voltage of 2.9V before the ON
pin is above the 1.21V minimum threshold voltage.
1V/DIV
SLAVE
10ms/DIV
2927 F17
Figure 17. Weak Resistive Load
2927fb
13
LTC2927
U
W
U
U
APPLICATIO S I FOR ATIO
Start-Up Delays
Layout Considerations
Often power supplies do not start-up immediately when
their input supplies are applied. If the LTC2927 tries to
ramp-up these power supplies as soon as the input supply is present, the start-up of the outputs may be delayed,
defeating the tracking circuit (Figure 18). Often this delay is
intentionally configured by a soft-start capacitor. This can
be remedied either by reducing the soft-start capacitor on
the slave supply or by including a capacitor in the ON pin’s
resistive divider to delay the ramp up. See Figure 19.
Be sure to place a 0.1μF bypass capacitor as near as possible to the supply pin of the LTC2927.
To minimize the noise on the slave supply’s output, keep
the trace connecting the FB pin of the LTC2927 and the
feedback node of the slave supply as short as possible.
In addition, do not route this trace next to signals with
fast transition times. In some circumstances it might be
advantageous to add a resistor near the feedback node of
the slave supply in series with the FB pin of the LTC2927.
This resistor must not exceed:
MASTER
RSERIES =
SLAVE
1V/DIV
ON
20ms/DIV
2927 F18
1.5V − VFB ⎛ 1.5V ⎞
=⎜
− 1⎟ RFA RFB
IMAX
⎝ VFB
⎠
(
)
This resistor is most effective if there is already a capacitor at the feedback node of the slave supply (often a
compensation component). Increasing the capacitance on
a slave supply’s feedback node will further improve the
noise immunity, but could affect the stability and transient
response of the supply.
Figure 18. Power Supply Start-Up Delayed
VCC
FB
FB
MASTER
DC/DC
RSERIES
LTC2927
MINIMIZE
TRACE
LENGTH
GND
RFA
OUT
RFB
2927 F20
SLAVE
0.1μF
1V/DIV
Figure 20. Layout Considerations
ON
5ms/DIV
2927 F19
Figure 19. ON Pin Delayed
2927fb
14
LTC2927
U
PACKAGE DESCRIPTIO
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1702)
0.61 ±0.05
(2 SIDES)
R = 0.115
TYP
5
0.56 ± 0.05
(2 SIDES)
3.00 ±0.10
(2 SIDES)
0.675 ±0.05
2.50 ±0.05
1.15 ±0.05
PACKAGE
OUTLINE
2.00 ±0.10
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.25 ± 0.05
4
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.50 BSC
2.20 ±0.05
(2 SIDES)
0.38 ± 0.10
8
(DDB8) DFN 1103
0.50 BSC
0 – 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1
PIN 1
CHAMFER OF
EXPOSED PAD
2.15 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
0.52
MAX
2.90 BSC
(NOTE 4)
0.65
REF
1.22 REF
1.4 MIN
3.85 MAX 2.62 REF
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
1.95 BSC
TS8 TSOT-23 0802
2927fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC2927
U
TYPICAL APPLICATIO
Single Supply Application
EARLY
VIN
3.3V
High Voltage Supply Application
EARLY
VIN
3.3V
0.1μF
RONB
138k
RONB
138k
VCC
ON
RAMP
RONA
100k
SDO
RONA
100k
3.3V
RUN/SS
FB
FB = 1.235V
MASTER
CRAMP
0.4μF
LTC2927
SDO
1.8V
RTB
78.7k
3.3V
RUN/SS
IN
DC/DC
RAMPBUF
OUT
FB
FB = 1.235V
OUT
SLAVE
12V
TRACK
TRACK
RTA
13k
RAMP
IN
DC/DC
RAMPBUF
VCC
ON
MASTER
CRAMP
0.1μF
LTC2927
RTB
16.5k
0.1μF
GND
2927 TA02a
RFB
16.5k
RFA
35.7k
RTA
28k
GND
2927 TA02b
RFA
35.7k
RFB
311k
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2920
Power Supply Margining Controller
Single or Dual Versions, Symmetric as Symmetric High and Low Margining
LTC2921/LTC2922
Power Supply Tracker with Input Monitors
Includes 3 (LTC2921) or 5 (LTC2922) Remote Sense Switches
LTC2923
Power Supply Tracking Controller
Controls 3 Supplies for Tracking or Sequencing
LTC2924
Quad Power Supply Sequencer
Controls 4 Supplies for Sequencing
LTC2925
Multiple Power Supply Tracking Controller with
Power Good Timeout
Controls 4 Supplies for Tracking or Sequencing
LTC2926
MOSFET-Controlled Power Supply Tracker
Active Tracking Control with Series MOSFETs
LTC2928
Multichannel Power Supply Sequencer
and Supervisor
Programmable with External Components; No Software Required
LT4220
Dual Supply Hot Swap™ Controller
±2.7V to ±16.5V, Supply Tracking Mode
LTC4221
Dual Hot Swap Controller
Operates from 1V to 13.5V, Allows Supply Sequencing, Active Current Limiting
LTC4230
Triple Hot Swap Controller with Multifunction
Current Control
1.7V to 16.5V, Active Inrush Limiting, Fast Comparator
LTC4253
–48V Hot Swap Controller and Supply
Sequencer
Floating Supply from –15V, Active Current Limiting, Enables Three DC/DC
Converters
Hot Swap is a trademark of Linear Technology Corporation.
2927fb
16
Linear Technology Corporation
LT 0308 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
工商网监
湘ICP备2023018690号
