LTC3711
5-Bit Adjustable,
Wide Operating Range,
No RSENSETM Step-Down Controller
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DESCRIPTIO
FEATURES
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The LTC®3711 is a synchronous step-down switching
regulator controller for CPU power. An output voltage
between 0.925V and 2.000V is selected by a 5-bit code
(Intel mobile VID specification). The controller uses a
valley current control architecture to deliver very low duty
cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT.
5-Bit Programmable Output Voltage: 0.925V to 2V
No Sense Resistor Required
True Current Mode Control
2% to 90% Duty Cycle at 200kHz
tON(MIN) < 100ns
Supports Active Voltage Positioning
Extremely Fast Transient Response
Stable with Ceramic COUT
Dual N-Channel MOSFET Synchronous Drive
Power Good Output Voltage Monitor
Wide VIN Range: 4V to 36V
±1% 0.8V Reference
Adjustable Current Limit
Adjustable Switching Frequency
Programmable Soft-Start
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Micropower Shutdown: IQ < 30µA
Available in 24-Lead Narrow SSOP Package
Discontinuous mode operation provides high efficiency
operation at light loads. A forced continuous control pin
reduces noise and RF interference and can assist secondary winding regulation by disabling discontinuous mode
operation when the main output is lightly loaded.
Fault protection is provided by internal foldback current
limiting, an output overvoltage comparator and optional
short-circuit shutdown timer. Soft-start capability for supply sequencing is accomplished using an external timing
capacitor. The regulator current limit level is user programmable. Wide supply range allows operation from 4V
to 36V at the input.
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APPLICATIO S
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, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
Power Supplies for Mobile Pentium® Processors
Notebook and Palmtop Computers, PDAs
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TYPICAL APPLICATIO
RON
330k
CSS
0.1µF
VIN
RUN/SS
CC 500pF
RC 20k
M1
IRF7811A
TG
ITH
SW
SGND
BOOST
VID4
BG
VID3
VID2
PGND
VID1
VID0
VOSENSE
+
DB
CMDSH-3
INTVCC
+
CVCC
4.7µF
CIN
22µF
50V
×3
L1
1µH
CB 0.33µF
LTC3711
5-BIT VID
Efficiency vs Load Current
ION
M2
IRF7811A
×2
D1
UPS840
COUT
270µF
2V
×4
VIN
5V TO 24V
Figure 1. High Efficiency Step-Down Converter
VOUT = 1.5V
EXTVCC = 5V
VIN = 5V
90
VOUT
1.5V
15A
CIN: UNITED CHEMICON
THCR70EIH226ZT
COUT: CORNELL DUBILIER
ESRE271M02B
L1: SUMIDA CEP125-IROMC
3711 F01a
100
EFFICIENCY (%)
PGOOD
VIN = 15V
80
70
60
0.01
1
0.1
LOAD CURRENT (A)
10
3711 F01b
3711f
1
LTC3711
W W
W
AXI U
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage
VIN, ION ..................................................36V to – 0.3V
Boosted Topside Driver Supply Voltage
BOOST .................................................. 42V to – 0.3V
SW, SENSE + Voltages ................................. 36V to – 5V
EXTVCC, (BOOST – SW), RUN/SS,
VID0-VID4, PGOOD Voltages ..................... 7V to – 0.3V
FCB, VON, VRNG Voltages .......... INTVCC + 0.3V to – 0.3V
ITH, VFB, VOSENSE Voltages ....................... 2.7V to – 0.3V
TG, BG, INTVCC, EXTVCC Peak Currents .................... 2A
TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA
Operating Ambient Temperature Range
LTC3711EGN (Note 2) ........................ – 40°C to 85°C
Junction Temperature (Note 3) ............................ 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
VID2
1
24 VID1
RUN/SS
2
23 VID0
VON
3
22 BOOST
PGOOD
4
21 TG
VRNG
5
20 SW
FCB
6
19 SENSE+
ITH
7
18 PGND
SGND
8
17 BG
ION
9
16 INTVCC
VFB 10
VOSENSE 11
VID3 12
LTC3711EGN
15 VIN
14 EXTVCC
13 VID4
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
900
15
2000
30
µA
µA
0.800
0.808
V
Main Control Loop
IQ
Input DC Supply Current
Normal
Shutdown Supply Current
VFB
Feedback Reference Voltage
ITH = 1.2V (Note 4)
∆VFB(LINEREG)
Feedback Voltage Line Regulation
VIN = 4V to 30V, ITH = 1.2V (Note 4)
∆VFB(LOADREG)
Feedback Voltage Load Regulation
ITH = 0.5V to 1.9V (Note 4)
IFB
Feedback Input Current
VFB = 0.8V
gm(EA)
Error Amplifier Transconductance
ITH = 1.2V (Note 4)
VFCB
Forced Continuous Threshold
IFCB
Forced Continuous Pin Current
VFCB = 0.8V
tON
On-Time
ION = 60µA, VON = 1.5V
ION = 30µA, VON = 1.5V
tON(MIN)
Minimum On-Time
ION = 180µA, VON = 0V
50
100
ns
tOFF(MIN)
Minimum Off-Time
ION = 60µA, VON = 1.5V
250
400
ns
VSENSE(MAX)
Maximum Current Sense Threshold
VPGND – VSENSE+
VRNG = 1V, VFB = 0.76V
VRNG = 0V, VFB = 0.76V
VRNG = INTVCC, VFB = 0.76V
133
93
186
153
107
214
mV
mV
mV
VSENSE(MIN)
Minimum Current Sense Threshold
VPGND – VSENSE+
VRNG = 1V, VFB = 0.84V
VRNG = 0V, VFB = 0.84V
VRNG = INTVCC, VFB = 0.84V
∆VFB(OV)
Output Overvoltage Fault Threshold
5.5
7.5
9.5
VFB(UV)
Output Undervoltage Fault Threshold
520
600
680
●
0.792
0.002
●
%/V
– 0.05
– 0.3
%
–5
±50
nA
mS
●
1.4
1.7
2
●
0.76
0.8
0.84
V
–1
–2
µA
250
500
288
575
ns
ns
212
425
●
113
79
158
– 67
– 47
– 93
mV
mV
mV
%
mV
3711f
2
LTC3711
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted.
SYMBOL
PARAMETER
VRUN/SS(ON)
RUN Pin Start Threshold
CONDITIONS
●
MIN
TYP
MAX
0.8
1.5
2
V
4
4.5
V
RUN/SS Pin Rising
UNITS
VRUN/SS(LE)
RUN Pin Latchoff Enable Threshold
VRUN/SS(LT)
RUN Pin Latchoff Threshold
RUN/SS Pin Falling
3.5
4.2
V
IRUN/SS(C)
Soft-Start Charge Current
VRUN/SS = 0V
– 0.5
– 1.2
–3
µA
IRUN/SS(D)
Soft-Start Discharge Current
VRUN/SS = 4.5V, VFB = 0V
0.8
1.8
3
µA
VIN(UVLO)
Undervoltage Lockout
VIN Falling
●
3.4
3.9
V
VIN(UVLOR)
Undervoltage Lockout Release
VIN Rising
●
3.5
4
V
TG RUP
TG Driver Pull-Up On Resistance
TG High
2
3
Ω
TG RDOWN
TG Driver Pull-Down On Resistance
TG Low
2
3
Ω
BG RUP
BG Driver Pull-Up On Resistance
BG High
3
4
Ω
BG RDOWN
BG Driver Pull-Down On Resistance
BG Low
1
2
Ω
TG tr
TG Rise Time
CLOAD = 3300pF
20
ns
TG tf
TG Fall Time
CLOAD = 3300pF
20
ns
BG tr
BG Rise Time
CLOAD = 3300pF
20
ns
BG tf
BG Fall Time
CLOAD = 3300pF
20
ns
Internal VCC Regulator
VINTVCC
Internal VCC Voltage
6V < VIN < 30V, VEXTVCC = 4V
∆VLDO(LOADREG)
Internal VCC Load Regulation
ICC = 0mA to 20mA, VEXTVCC = 4V
VEXTVCC
EXTVCC Switchover Voltage
ICC = 20mA, VEXTVCC Rising
∆VEXTVCC
EXTVCC Switch Drop Voltage
ICC = 20mA, VEXTVCC = 5V
∆VEXTVCC(HYS)
EXTVCC Switchover Hysteresis
●
4.7
●
4.5
5
5.3
V
– 0.1
±2
%
4.7
150
V
300
200
mV
mV
PGOOD Output
∆VFBH
PGOOD Upper Threshold
∆VFBL
∆VFB(HYS)
VPGL
VFB Rising
5.5
7.5
9.5
%
PGOOD Lower Threshold
VFB Falling
– 5.5
– 7.5
– 9.5
%
PGOOD Hysteresis
VFB Returning
1
2
%
PGOOD Low Voltage
IPGOOD = 5mA
0.15
0.4
V
1.2
2
V
VID DAC
VVID(T)
VID0-VID4 Logic Threshold Voltage
0.4
IVID(PULLUP)
VID0-VID4 Pull-Up Current
VVID(PULLUP)
VID0-VID4 Pull-Up Voltage
VVID0 to VVID4 Open
4.5
IVID(LEAK)
VID0-VID4 Leakage Current
VVID0 to VVID4 = 5V, VRUN/SS = 0V
0.01
1
µA
RVID
Resistance from VOSENSE to VFB
6
10
14
KΩ
∆VOSENSE
DAC Output Accuracy
– 0.25
0
0.25
%
VVID0 to VVID4 = 0V
VOSENSE Programmed from
0.925V to 2V (Note 5)
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: The LTC3711E is guaranteed to meet performance specifications from
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD as follows:
LTC3711EGN: TJ = TA + (PD • 130°C/W)
µA
– 2.5
V
Note 4: The LTC3711 is tested in a feedback loop that adjusts VFB to achieve
a specified error amplifier output voltage (ITH).
Note 5: The LTC3711 VID DAC is tested in a feedback loop that adjusts
VOSENSE to achieve a specified feedback voltage (VFB = 0.8V) for each DAC VID
code.
3711f
3
LTC3711
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TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
(Discontinuous Mode)
Transient Response
VOUT
50mV/DIV
Start-Up
VOUT
50mV/DIV
RUN/SS
2V/DIV
VOUT
1V/DIV
IL
10A/DIV
IL
10A/DIV
20µs/DIV
LOAD STEP = 1A TO 15A
VIN = 15V
VOUT = 1.5V
FCB = INTVCC
FIGURE 9 CIRCUIT
3711 G01
Efficiency vs Load Current
DISCONTINUOUS
MODE
EFFICIENCY (%)
EFFICIENCY (%)
80
70
CONTINUOUS
MODE
VIN = 15V
VOUT = 1.5V
EXTVCC = 5V
FIGURE 9 CIRCUIT
60
50
0.001
0.1
1
0.01
LOAD CURRENT (A)
Frequency vs Load Current
350
FIGURE 9 CIRCUIT
FCB = 5V
EXTVCC = 5V
95
90
ILOAD = 1.5A
85
ILOAD = 15A
80
50
70
0
10
0
5
10
15
20
INPUT VOLTAGE (V)
25
300
CURRENT SENSE THRESHOLD (mV)
2.0
IOUT = 0A
250
1.5
1.0
0.5
225
15
20
INPUT VOLTAGE (V)
25
3711 G07
4
6
LOAD CURRENT (A)
8
0
0
5
10
15
LOAD CURRENT (A)
20
10
Current Sense Threshold
vs ITH Voltage
FIGURE 9 CIRCUIT
FCB = 0V
275
2
3711 G06
ITH Voltage vs Load Current
IOUT = 15A
0
3711 G05
ITH VOLTAGE (V)
FREQUENCY (kHz)
30
2.5
10
DISCONTINUOUS MODE
150
100
FIGURE 9 CIRCUIT
FCB = 0V
5
200
FIGURE 9 CIRCUIT
350
200
250
75
Frequency vs Input Voltage
300
CONTINUOUS MODE
300
3711 G04
325
3711 G03
VIN = 15V
VOUT = 1.5V
RLOAD = 0.1Ω
FIGURE 9 CIRCUIT
Efficiency vs Input Voltage
100
100
90
50ms/DIV
3711 G02
FREQUENCY (kHz)
20µs/DIV
LOAD STEP = 0A TO 15A
VIN = 15V
VOUT = 1.5V
FCB = 0V
FIGURE 9 CIRCUIT
IL
10A/DIV
25
3711 G09
VRNG =
200
2V
1.4V
1V
0.7V
0.5V
100
0
–100
–200
0
0.5
1.0
1.5
2.0
ITH VOLTAGE (V)
2.5
3.0
3711 G10
3711f
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LTC3711
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TYPICAL PERFOR A CE CHARACTERISTICS
On-Time vs VON Voltage
On-Time vs ION Current
10k
VVON = 0V
1000
On-Time vs Temperature
300
IION = 30µA
250
ON-TIME (ns)
1k
ON-TIME (ns)
ON-TIME (ns)
800
100
600
400
10
10
ION CURRENT (µA)
1
150
0
100
50
2
1
VON VOLTAGE (V)
0
3711 G11
100
75
50
25
0
0.2
0.4
VFB (V)
0.6
300
250
200
150
100
50
0
0.8
0.5
3711 G14
0.75
1.0
1.25
1.5
VRNG VOLTAGE (V)
1.75
100
75
50
25
0
2
2.5
3
RUN/SS VOLTAGE (V)
3.5
3711 G16
0.82
FEEDBACK REFERENCE VOLTAGE (V)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
125
Feedback Reference Voltage
vs Temperature
140
130
120
110
–25
125
VRNG = 1V
3711 G15
VRNG = 1V
100
–50
150
1.5
2.0
Maximum Current Sense
Threshold vs Temperature
150
100
Maximum Current Sense
Threshold vs RUN/SS Voltage
MAXIMUM CURRENT SENSE THRESHOLD (mV)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
125
50
25
75
0
TEMPERATURE (°C)
3711 G13
Maximum Current Sense
Threshold vs VRNG Voltage
VRNG = 1V
0
0
–50 –25
3
3711 G12
Current Limit Foldback
MAXIMUM CURRENT SENSE THRESHOLD (mV)
200
100
200
150
IION = 30µA
VVON = 0V
50
25
0
75
TEMPERATURE (°C)
100
125
3711 G17
0.81
0.80
0.79
0.78
–50 –25
75
0
25
50
TEMPERATURE (°C)
100
125
3711 G18
3711f
5
LTC3711
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TYPICAL PERFOR A CE CHARACTERISTICS
Input and Shutdown Currents
vs Input Voltage
2.0
EXTVCC OPEN
INPUT CURRENT (µA)
1.4
1.2
50
800
40
SHUTDOWN
600
30
400
20
200
SHUTDOWN CURRENT (µA)
1.6
0
60
1000
1.8
gm (mS)
INTVCC Load Regulation
1200
–0.1
∆INTVCC (%)
Error Amplifier gm vs Temperature
–0.2
–0.3
–0.4
10
EXTVCC = 5V
1.0
–50
0
50
25
0
75
TEMPERATURE (°C)
–25
100
5
20
15
25
10
INPUT VOLTAGE (V)
30
35
EXTVCC Switch Resistance
vs Temperature
RUN/SS Pin Current
vs Temperature
FCB Pin Current vs Temperature
8
–0.25
2
6
4
2
FCB PIN CURRENT (µA)
3
FCB PIN CURRENT (µA)
0
–0.50
–0.75
–1.00
50
25
0
75
TEMPERATURE (°C)
100
–1.50
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
100
3711 G22
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
RUN/SS THRESHOLD (V)
4.5
LATCHOFF ENABLE
4.0
3.5
LATCHOFF THRESHOLD
75
0
25
50
TEMPERATURE (°C)
PULL-UP CURRENT
125
–2
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3711 G24
Undervoltage Lockout Threshold
vs Temperature
5.0
–25
0
3711 G23
RUN/SS Latchoff Thresholds
vs Temperature
3.0
–50
PULL-DOWN CURRENT
1
–1
–1.25
–25
50
3711 G21
10
0
–50
10
30
40
20
INTVCC LOAD CURRENT (mA)
0
3711 G20
3711 G19
EXTVCC SWITCH RESISTANCE (Ω)
–0.5
0
0
125
100
125
3711 G25
4.0
3.5
3.0
2.5
2.0
–50 –25
75
0
25
50
TEMPERATURE (C)
100
125
3711 G26
3711f
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LTC3711
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PI FU CTIO S
VID0-VID4 (Pins 23, 24, 1, 12, 13): VID Digital Inputs.
The voltage identification (VID) code sets the internal
feedback resistor divider ratio for different output voltages
as shown in Table 1. If unconnected, the pins are pulled
high by internal 2.5µA current sources.
RUN/SS (Pin 2): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
VON (Pin 3): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to VOUT. The
comparator input defaults to 0.7V when the pin is grounded,
2.4V when the pin is tied to INTVCC.
PGOOD (Pin 4): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±7.5% of the regulation point.
VRNG (Pin 5): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
FCB (Pin 6): Forced Continuous Input. Tie this pin to
ground to force continuous synchronous operation at low
load, to INTVCC to enable discontinuous mode operation
at low load or to a resistive divider from a secondary output
when using a secondary winding.
ITH (Pin 7): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
SGND (Pin 8): Signal Ground. All small-signal components and compensation components should connect to
this ground, which in turn connects to PGND at one point.
ION (Pin 9): On-Time Current Input. Tie a resistor from VIN
to this pin to set the one-shot timer current and thereby set
the switching frequency.
VFB (Pin 10): Error Amplifier Feedback Input. This pin
connects to both the error amplifier input and to the output
of the internal resistive divider. It can be used to attach
additional compensation components if desired.
VOSENSE (Pin 11): Output Voltage Sense. The output
voltage connects here to the input of the internal resistive
feedback divider.
EXTVCC (Pin 14): External VCC Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to INTVCC
and shuts down the internal regulator so that controller
and gate drive power is drawn from EXTVCC. Do not exceed
7V at this pin and ensure that EXTVCC < VIN.
VIN (Pin 15): Main Input Supply. Decouple this pin to
PGND with an RC filter (1Ω, 0.1µF).
INTVCC (Pin 16): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. Decouple this pin to power ground with a minimum of 4.7µF
low ESR tantalum capacitor.
BG (Pin 17): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
PGND (Pin 18): Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of CVCC and the (–) terminal of CIN.
SENSE + (Pin 19): Current Sense Comparator Input. The
(+) input to the current comparator is normally connected
to the SW node unless using a sense resistor (see Applications Information).
SW (Pin 20): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to VIN.
TG (Pin 21): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW.
BOOST (Pin 22): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
3711f
7
LTC3711
W
FU CTIO AL DIAGRA
U
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RON
VIN
3 VON
9 ION
6 FCB
15 VIN
14 EXTVCC
+
4.7V
CIN
0.7V
+
1µA
2.4V
–
0.8V
REF
0.8V
1
5V
REG
+
–
OST
BOOST
F
22
V
tON = VON (10pF)
IION
R
S
Q
FCNT
20
SENSE +
SWITCH
LOGIC
IREV
L1
DB
19
–
–
M1
SW
+
ICMP
CB
21
ON
20k
+
TG
INTVCC
16
SHDN
1.4V
BG
OV
+
COUT
CVCC
M2
17
VRNG
5
PGND
×
18
PGOOD
0.7V
4
3.3µA
VOSENSE
11
1
240k
+
1V
Q2 Q4
0.74V
UV
–
Q6
R2
10k
×5 (ALL VID PINS)
INTVCC
ITHB
2.5µA
23 VID0
Q3 Q1
+
Q5
24 VID1
OV
+
–
–
0.8V
–
×4
SS
+
0.86V
RUN
SHDN
VID
DAC
12 VID3
1.2µA 6V
EA
1 VID2
13 VID4
+
–
–
+
0.6V
0.8V
7 ITH
RC
CC1
0.6V
2 RUN/SS CSS
VFB 10
R1
8 SGND
3711 FD
3711f
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LTC3711
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OPERATIO
Main Control Loop
The LTC3711 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and
initiating the next cycle. Inductor current is determined
by sensing the voltage between the PGND and SENSE +
pins using either the bottom MOSFET on-resistance or an
optional sense resistor. The voltage on the ITH pin sets the
comparator threshold corresponding to inductor valley
current. The error amplifier EA adjusts this voltage by
comparing the feedback signal VFB from the output
voltage with an internal 0.8V reference. The feedback
voltage is derived from the output voltage by a resistive
divider DAC that is set by the VID code pins VID0-VID4.
If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The ITH voltage
then rises until the average inductor current again matches
the load current.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator IREV which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the ITH voltage rises above the zero current level (0.8V) to
initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.8V, forcing continuous synchronous operation.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN and VOUT. The nominal frequency can be adjusted
with an external resistor RON.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±7.5% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned
off and M2 is turned on and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is
shorted to ground. As VFB drops, the buffered current
threshold voltage ITHB is pulled down by clamp Q3 to a 1V
level set by Q4 and Q6. This reduces the inductor valley
current level to one sixth of its maximum value as VFB
approaches 0V.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately
0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode
DB when the top MOSFET is turned off. When the EXTVCC
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VIN. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
a high efficiency source connected to EXTVCC, such as an
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the input voltage is low and INTVCC drops below 3.5V,
undervoltage lockout circuitry prevents the power
switches from turning on.
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The basic LTC3711 application circuit is shown in
Figure 1. External component selection is primarily determined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3711 can use either a sense resistor or
the on-resistance of the synchronous power MOSFET for
determining the inductor current. The desired amount of
ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its
ability to handle the large RMS current into the converter
and COUT is chosen with low enough ESR to meet the
output voltage ripple and transient specification.
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the PGND
and SENSE + pins. The maximum sense voltage is set by
the voltage applied to the VRNG pin and is equal to
approximately (0.133)VRNG. The current mode control
loop will not allow the inductor current valleys to exceed
(0.133)VRNG/RSENSE. In practice, one should allow some
margin for variations in the LTC3711 and external component values and a good guide for selecting the sense
resistance is:
RSENSE =
VRNG
10 • IOUT(MAX)
An external resistive divider from INTVCC can be used to
set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.
Connecting the SENSE + Pin
The LTC3711 can be used with or without a sense resistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect
the SENSE + pin to the source of the bottom MOSFET so
that the resistor appears between the SENSE + and PGND
pins. Using a sense resistor provides a well defined
current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the
bottom MOSFET as the current sense element by simply
connecting the SENSE + pin to the switch node SW at the
drain of the bottom MOSFET. This improves efficiency, but
one must carefully choose the MOSFET on-resistance as
discussed below.
Power MOSFET Selection
The LTC3711 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS,
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current IDS(MAX).
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3711 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
RDS(ON)(MAX) =
RSENSE
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum temperature of 100°C, using a
value ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. When the LTC3711 is operating in
continuous mode, the duty cycles for the MOSFETs are:
VOUT
VIN
V –V
= IN OUT
VIN
DTOP =
DBOT
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ρT NORMALIZED ON-RESISTANCE
2.0
Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency
operation as the input supply varies:
1.5
1.0
f=
VOUT
VVON RON(10pF )
0.5
0
– 50
50
100
0
JUNCTION TEMPERATURE (°C)
150
3711 F02
Figure 2. RDS(ON) vs. Temperature
To hold frequency constant during output voltage changes,
tie the VON pin to VOUT. Figure 3 shows how frequency
varies with RON in this case. The VON pin has internal
clamps that limit its input to the one-shot timer. If the pin
is tied below 0.7V, the input to the one-shot is clamped at
0.7V. Similarly, if the pin is tied above 2.4V, the input is
clamped at 2.4V.
The resulting power dissipation in the MOSFETs at maximum output current are:
PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX)
Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3711 applications is determined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the VON
pin according to:
VVON
(10pF )
IION
1000
SWITCHING FREQUENCY (kHz)
PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX)
+ k VIN2 IOUT(MAX) CRSS f
tON =
[Hz]
10
100
1000
RON (kΩ)
3711 F03
Figure 3. Switching Frequency vs RON with VON Tied to VOUT
Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
RON2 =
5V
RON
0.7 V
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By lengthening the on-time slightly
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RVON1
30k
RVON1
3k
VON
VOUT
CVON
0.01µF
RVON2
100k
VOUT
10k
LTC3711
INTVCC
RC
CVON
0.01µF
LTC3711
ITH
CC
3711 F04a
(4a)
VON
RC
Q1
2N5087
ITH
CC
RVON2
10k
3711 F04b
(4b)
Figure 4. Correcting Frequency Shift with Load Current Changes
2.0
SWITCHING FREQUENCY (MHz)
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 4a. Place capacitance on the VON pin to
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 4b.
1.5
DROPOUT
REGION
1.0
0.5
0
0
0.25
0.50
0.75
DUTY CYCLE (VOUT/VIN)
1.0
3711 F05
Minimum Off-time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3711 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
VIN(MIN) = VOUT
tON + tOFF(MIN)
tON
A plot of maximum duty cycle vs frequency is shown in
Figure 5.
Figure 5. Maximum Switching Frequency vs Duty Cycle
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
V V
∆IL = OUT 1 − OUT
VIN
fL
Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
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VOUT
VOUT
L=
1−
f ∆IL(MAX) VIN(MAX)
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. A variety of inductors designed for high
current, low voltage applications are available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft
and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to be
effective, the inductance between it and the bottom MOSFET
must be as small as possible, mandating that these
components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
IRMS ≅ IOUT(MAX)
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX) / 2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.
Kool Mµ is a registered trademark of Magnetics, Inc.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple ∆VOUT is approximately
bounded by:
1
∆VOUT ≤ ∆IL ESR +
8 fCOUT
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
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to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.8V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which
current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current and
will vary with changes in VIN. Tying the FCB pin below the
0.8V threshold forces continuous synchronous operation,
allowing current to reverse at light loads and maintaining
high frequency operation.
In addition to providing a logic input to force continuous
operation, the FCB pin provides a means to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output VSEC is normally set as shown in Figure 6 by the turns ratio N of the
transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary
load current, then VOUT2 will droop. An external resistor
divider from VOUT2 to the FCB pin sets a minimum voltage
VOUT2(MIN) below which continuous operation is forced
until VOUT2 has risen above its minimum.
R4
VOUT 2(MIN) = 0.8V 1 +
R3
CIN
VIN
OPTIONAL
EXTVCC
CONNECTION
5V < VOUT2 < 7V
TG
FCB
R3
SENSE +
ILIMIT =
VSNS(MAX)
1
+ ∆IL
RDS(ON) ρT 2
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
1N4148
•
+
LTC3711
SW
EXTVCC
R4
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3711, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
To further limit current in the event of a short circuit to
ground, the LTC3711 includes foldback current limiting. If
the output falls by more than 25%, then the maximum
sense voltage is progressively lowered to about one sixth
of its full value.
VIN
+
Fault Conditions: Current Limit and Foldback
T1
1:N
• +
VOUT2
COUT2
1µF
VOUT
COUT
BG
SGND
PGND
3711 F06
Figure 6. Secondary Output Loop and EXTVCC Connection
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Output Voltage Programming
Table 1. VID Output Voltage Programming
VID4
VID3
VID2
VID1
VID0
VOUT (V)
0
0
0
0
0
2.000V
0
0
0
0
1
1.950V
0
0
0
1
0
1.900V
0
0
0
1
1
1.850V
0
0
1
0
0
1.800V
0
0
1
0
1
1.750V
0
0
1
1
0
1.700V
0
0
1
1
1
1.650V
0
1
0
0
0
1.600V
INTVCC Regulator
0
1
0
0
1
1.550V
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3711. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF low ESR tantalum capacitor. Good
bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. Applications
using large MOSFETs with a high input voltage and high
frequency of operation may cause the LTC3711 to exceed
its maximum junction temperature rating or RMS current
rating. Most of the supply current drives the MOSFET
gates unless an external EXTVCC source is used. In continuous mode operation, this current is IGATECHG = f(Qg(TOP)
+ Qg(BOT)). The junction temperature can be estimated
from the equations given in Note 2 of the Electrical
Characteristics. For example, the LTC3711CGN is limited
to less than 14mA from a 30V supply:
0
1
0
1
0
1.500V
0
1
0
1
1
1.450V
0
1
1
0
0
1.400V
0
1
1
0
1
1.350V
0
1
1
1
0
1.300V
0
1
1
1
1
*
1
0
0
0
0
1.275V
1
0
0
0
1
1.250V
1
0
0
1
0
1.225V
1
0
0
1
1
1.200V
1
0
1
0
0
1.175V
1
0
1
0
1
1.150V
1
0
1
1
0
1.125V
1
0
1
1
1
1.100V
1
1
0
0
0
1.075V
1
1
0
0
1
1.050V
1
1
0
1
0
1.025V
1
1
0
1
1
1.000V
1
1
1
0
0
0.975V
1
1
1
0
1
0.950V
1
1
1
1
0
0.925V
1
1
1
1
1
**
The output voltage is digitally set to levels between 0.900V
and 2.000V using the voltage identification (VID) inputs
VID0-VID4. An internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in
increments according to Table 1. The VID codes are
compatible with Intel Mobile Pentium III processor specifications. Each VID input is pulled up by an internal 2.5µA
current source from the INTVCC supply and includes a
series diode to prevent damage from VID inputs that
exceed the supply.
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
For larger currents, consider using an external supply with
the EXTVCC pin.
Note: *, ** represent codes without a defined output voltage as specified by
Intel. The LTC3711 interprets these codes as valid inputs and produces output
voltages as follows: [01111] = 1.250V, [11111] = 0.900V.
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EXTVCC Connection
The EXTVCC pin can be used to provide MOSFET gate drive
and control power from the output or another external
source during normal operation. Whenever the EXTVCC
pin is above 4.7V the internal 5V regulator is shut off and
an internal 50mA P-channel switch connects the EXTVCC
pin to INTVCC. INTVCC power is supplied from EXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
the EXTVCC pin and ensure that EXTVCC ≤ VIN. The following list summarizes the possible connections for EXTVCC:
1. EXTVCC grounded. INTVCC is always powered from the
internal 5V regulator.
2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
External Gate Drive Buffers
The LTC3711 drivers are adequate for driving up to about
30nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 7
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate and benefit from an
increased EXTVCC voltage of about 6V.
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3711 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3711 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:
tDELAY =
(
)
1.5V
CSS = 1.3s/µF CSS
1.2µA
When the voltage on RUN/SS reaches 1.5V, the LTC3711
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
back until the output reaches 75% of its final value. The pin
can be driven from logic as shown in Figure 8. Diode D1
reduces the start delay while allowing CSS to charge up
slowly for the soft-start function.
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA current then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:
CSS > COUT VOUT RSENSE (10 – 4 [F/V s])
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff
operation can prove annoying during troubleshooting.
The feature can be overridden by adding a pull-up current
greater than 5µA to the RUN/SS pin. The additional
current prevents the discharge of CSS during a fault and
also shortens the soft-start period. Using a resistor to V IN
as shown in Figure 8a is simple, but slightly increases
shutdown current. Connecting a resistor to INTV CC as
shown in Figure 8b eliminates the additional shutdown
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current, but requires a diode to isolate CSS. Any pull-up
network must be able to pull RUN/SS above the 4.2V
maximum threshold of the latchoff circuit and overcome
the 4µA maximum discharge current.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3711 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high
efficiency source, such as an output derived boost network or alternate supply if available.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
INTVCC
RSS*
VIN
INTVCC
BOOST
10Ω
GATE
OF M1
Q2
FMMT720
SW
D1
Q3
FMMT619
Q1
FMMT619
TG
3.3V OR 5V
10Ω
Q4
FMMT720
PGND
Figure 7. Optional External Gate Driver
D2*
RUN/SS
CSS
CSS
GATE
OF M2
BG
RUN/SS
RSS*
3711 F08
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
3711 F07
(8a)
(8b)
Figure 8. RUN/SS Pin Interfacing with Latchoff Defeated
3711f
17
LTC3711
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APPLICATIO S I FOR ATIO
2
Figure 9 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
PBOT
Design Example
TJ = 50°C + (2.12W)(50°C/W) = 156°C
As a design example, take a supply with the following
specifications: VIN = 7V to 24V (15V nominal), VOUT = 1.5V
±100mV, IOUT(MAX) = 15A, f = 300kHz. First, calculate the
timing resistor with VON = VOUT:
RON =
1
(300kHz)(10pF)
= 330k
and choose the inductor for about 40% ripple current at
the maximum VIN:
1.5V
1.5V
L=
1−
= 0.8µH
(300kHz)(0.4)(15A) 24V
Selecting a standard value of 1µH results in a maximum
ripple current of:
∆IL =
(
1.5V
1–
= 4.7 A
300kHz 1µH 24V
1.5V
)( )
Next, choose the synchronous MOSFET switch. Because
of the narrow duty cycle and large current, a single SO-8
MOSFET will have difficulty dissipating the power lost in
the switch. Choosing two IRF7811A (RDS(ON) = 0.013Ω,
CRSS = 60pF, θJA = 50°C/W) yields a nominal sense voltage
of:
VSNS(NOM) = (15A)(0.5)(1.3)(0.012Ω) = 117mV
Tying VRNG to INTVCC will set the current sense voltage
range for a nominal value of 140mV with current limit
occurring at 186mV. To check if the current limit is
acceptable, assume a junction temperature of about 100°C
above a 50°C ambient with ρ150°C = 1.6:
ILIMIT ≥
(0.5)(1.6)(0.012Ω) ( )
186mV
+
1
4.7 A = 18 A
2
and double check the assumed TJ in the MOSFET:
24V – 1.5V 21.7 A
=
1.6 0.012 Ω = 2.12 W
24V
2
( )(
)
Because the top MOSFET is on for such a short time, a
single IRF7811A will be sufficient. Checking its power
dissipation at current limit with ρ90°C = 1.3:
) (1.3)(0.012Ω) +
2
(1.7)(24V) (21.7A)(60pF)(300kHz)
PBOT =
(
1.5V
21.7 A
24V
2
= 0.46W + 0.38W = 0.84W
TJ = 50°C + (0.84W)(50°C/W) = 92°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (4.7A) (0.005Ω) = 24mV
However, a 0A to 15A load step will cause an output
change of up to:
∆VOUT(STEP) = ∆ILOAD (ESR) = (15A) (0.005Ω) = 75mV
The complete circuit is shown in Figure 9.
Active Voltage Positioning
Active voltage positioning (also termed load “deregulation” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage above the regulation point at zero load, and below
the regulation point at full load, one can use more of the
error budget for the load step. This allows one to reduce
the number of output capacitors by relaxing the ESR
requirement.
3711f
18
LTC3711
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APPLICATIO S I FOR ATIO
In the design example, Figure 9, five 0.025Ω capacitors
are required in parallel to keep the output voltage within
tolerance. Using active voltage positioning, the same
specification can be met with only three capacitors. In this
case, the load step will cause an output voltage change of:
VSNS(NOM) = (0.003Ω)(15A) = 45mV
To maintain a reasonable current limit, the voltage on the
VRNG pin is reduced to its minimum value of 0.5V, corresponding to a 50mV nominal sense voltage.
1
∆VOUT(STEP) = 15A 0.025Ω = 125mV
3
( ) (
voltage positioning. In order to minimize power lost in this
resistor, a low value is chosen of 0.003Ω. The nominal
sense voltage will now be:
)
By positioning the output voltage 60mV above the regulation point at no load, it will only drop 65mV below the
regulation point after the load step, well within the ±100mV
tolerance.
Next, the gain of the LTC3711 error amplifier must be
determined. The change in ITH voltage for a corresponding
change in the output current is:
12V
∆ITH =
RSENSE ∆IOUT
VRNG
Implementing active voltage positioning requires setting a
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resistance, it is prudent to use a sense resistor with active
1
CSS
0.1µF
2
3
RPG
100k
4
5
CC1
470pF
6
RC
20k
7
CC2
100pF
8
9
CFB 100pF
10
C2
6.8nF 11
RON
330k
12
VID2
VID1
RUN/SS
VID0
VON
BOOST
PGOOD
TG
VRNG
SW
SENSE+
FCB
LTC3711
ITH
SGND
ION
VFB
VOSENSE
VID3
PGND
BG
INTVCC
VIN
EXTVCC
VID4
( )(
)( )
= 24 0.003Ω 15A = 1.08 V
24
23
DB
CMDSH-3
22
21
CB
0.33µF
M1
IRF7811A
CIN
22µF
50V
×3
L1
1µH
20
M2
IRF7811A
×2
19
18
+
D1
UPS840
VIN
7V TO 24V
VOUT
1.5V
15A
COUT
270µF
2V
×5
17
16
CVCC
4.7µF
RF
1Ω
15
14
CF
0.1µF
13
3711 F09
CIN: UNITED CHEMICON THCR70EIH226ZT
COUT: CORNELL DUBILIER ESRE271M02B
L1: SUMIDA CEP125-IR0MC-H
Figure 9. CPU Core Voltage Regulator 1.5V/15A at 300kHz
3711f
19
LTC3711
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APPLICATIO S I FOR ATIO
The corresponding change in the output voltage is determined by the gain of the error amplifier and feedback
divider. The LTC3711 error amplifier has a transconductance gm that is constant over both temperature and a wide
± 40mV input range. Thus, by connecting a load resistance RVP to the ITH pin, the error amplifier gain can be
precisely set for accurate active voltage positioning.
0.8 V
∆ITH = gm RVP
∆VOUT
VOUT
Solving for this resistance value:
RVP =
VOUT ∆ITH
(0.8 V) gm ∆VOUT
(1.5V)(1.08 V)
=
= 9.53k
(0.8 V)(1.7mS)(125mV)
The gain setting resistance RVP is implemented with two
resistors, RVP1 connected from ITH to ground and RVP2
connected from ITH to INTVCC. The parallel combination of
these resistors must equal RVP and their ratio determines
nominal value of the ITH pin voltage when the error
amplifier input is zero. To center the load line around the
regulation point, the ITH pin voltage must be set to correspond to half the output current. The relation between ITH
voltage and the output current is:
12V
1
ITH(NOM) =
RSENSE IOUT – ∆IL + 0.8 V
2
VRNG
12V
1
=
.
Ω
.
–
.
0
003
7
5
4
7
A
A
+ 0.8 V
2
0.5V
= 1.17 V
(
)
The modified circuit is shown in Figure 10. Figures 11
and␣ 12 show the transient response without and with
active voltage positioning. Both circuits easily stay within
±100mV of the 1.5V output. However, the circuit with
active voltage positioning accomplishes this with only
three output capacitors rather than five. Refer to Design
Solutions 10 for additional information about active voltage positioning.
PC Board Layout Checklist
When laying out the printed circuit board, use the following checklist to ensure proper operation of the controller.
These items are also illustrated in Figure 11.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SENSE + traces short.
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Connect the VIN pin decoupling capacitor CF closely to
the VIN and PGND pins.
• VID0-VID4 interface circuitry must return to SGND.
Solving for the required values of the resistors:
RVP1 =
5V
5V
9.53k
RVP =
5V – ITH(NOM)
5V – 1.17 V
= 12.44k
5V
5V
9.53k = 40.73k
RVP2 =
RVP =
1.17 V
ITH(NOM)
3711f
20
LTC3711
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APPLICATIO S I FOR ATIO
1
CSS
0.1µF
2
3
RRNG1 RRNG2
4.99k 45.3k
RPG
100k
4
5
VID2
VID1
RUN/SS
VID0
VON
BOOST
PGOOD
TG
VRNG
SW
24
23
DB
CMDSH-3
22
21
CB
0.33µF
M1
IRF7811A
6
7
RVP1
12.4k
CC1
180pF 8
9
CFB 100pF
10
11
12
RON
330k
CIN: UNITED CHEMICON THCR70EIH226ZT
COUT: CORNELL DUBILIER ESRE271M02B
L1: SUMIDA CEP125-IR0MC-H
FCB
M2
IRF7811A
×2
ITH
SGND
SENSE +
PGND
BG
ION
INTVCC
VFB
VIN
VOSENSE
VID3
EXTVCC
VID4
L1
1µH
20
LTC3711
RVP2
40.2k
CIN
22µF
50V
×3
D1
UPS840
19
VIN
7V TO 24V
VOUT
1.5V
15A
COUT
270µF
2V
×3
RSENSE
0.003Ω
18
17
16
CVCC
4.7µF
RF
1Ω
15
14
CF
0.1µF
13
3711 F010
Figure 10. CPU Core Voltage Regulator with Active Voltage Positioning 1.5V/15A at 300kHz
3711f
21
LTC3711
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APPLICATIO S I FOR ATIO
VOUT
100mV/DIV
VOUT
100mV/DIV
1.5V
1.5V
IL
10A/DIV
IL
10A/DIV
COUT = 5 × 270µF
VIN = 15V
FIGURE 7 CIRCUIT
20µs/DIV
COUT = 3 × 270µF
VIN = 15V
FIGURE 8 CIRCUIT
3711 F09
Figure 11. Normal Transient Response
1
20µs/DIV
3711 F10
Figure 12. Transient Response with Active Voltage Positioning
VID2
VID1
RUN/SS
VID0
24
CSS
2
23
CB
3
4
5
6
CC1
RC
7
CC2
8
VON
BOOST
PGOOD
TG
VRNG
SW
21
20
DB
PGND
BG
SGND
D1
CFB
10
11
RON
12
ION
INTVCC
VFB
VIN
VOSENSE
EXTVCC
VID3
CIN
VIN
M2
LTC3711
ITH
19
18
–
17
–
CVCC
9
+
M1
SENSE+
FCB
L
22
VID4
16
15
VOUT
COUT
+
CF RF
14
13
3711 F13
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 13. LTC3711 Layout Diagram
3711f
22
LTC3711
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
24 23 22 21 20 19 18 17 16 15 1413
.033
(0.838)
REF
.045 ±.005
.229 – .244
(5.817 – 6.198)
.254 MIN
.150 – .157**
(3.810 – 3.988)
.150 – .165
1
.0165 ± .0015
2 3
4
5 6
7
8
9 10 11 12
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
.0250
(0.635)
BSC
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN24 (SSOP) 0502
3711f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC3711
U
TYPICAL APPLICATIO
1.5V/15A All Ceramic COUT
1
CSS
0.1µF
2
3
RPG
100k
4
5
CC1
2.2nF
6
RC
4.7k
7
CC2
100pF
8
9
CFB 100pF
10
11
RON
330k
12
VID2
VID1
RUN/SS
VID0
VON
BOOST
PGOOD
TG
VRNG
SW
SENSE +
FCB
LTC3711
ITH
PGND
BG
SGND
ION
INTVCC
VFB
VIN
VOSENSE
VID3
EXTVCC
VID4
24
23
DB
CMDSH-3
22
21
CB
0.33µF
M1
IRF7811A
CIN
22µF
50V
×3
L1
1µH
20
M2
IRF7811A
×2
19
18
+
D1
UPS840
VIN
7V TO 24V
VOUT
1.5V
15A
COUT
47µF
10V
×8
17
16
CVCC
4.7µF
RF
1Ω
15
14
CF
0.1µF
13
3711 TA01
CIN: UNITED CHEMICON THCR70EIH226ZT
COUT: TAIYO YUDEN LMK550BJ476MM, 1.5V/15A ALL CERAMIC
L1: SUMIDA CEP125-IR0MC-H
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PART NUMBER DESCRIPTION
COMMENTS
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No RSENSE Current Mode Synchronous Step-Down Controller
97% Efficiency, No Sense Resistor, 16-Pin SSOP
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High Efficiency, Synchronous Step-Down Controller with 5-Bit VID
Mobile VID, 0.925V ≤ VOUT ≤ 2V, 3.5V ≤ VIN ≤ 36V
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SOT-23 Step-Down Controller
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LTC1773
Synchronous Step-Down Controller
Up to 95% Efficiency; 550kHz, 2.65V ≤ VIN ≤ 8.5V,
0.8V ≤ VOUT ≤ VIN, Synchronizable to 750kHz
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No Sense Resistor Required, 4V ≤ VIN ≤ 36V,
0.8V ≤ VOUT ≤ (0.9) VIN
LTC1874
Dual, Step-Down Controller
Current Mode; 550kHz; Small 16-Pin SSOP, VIN < 9.8V
LTC1876
2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator
3.5V ≤ VIN ≤ 36V, Power Good Output, 300kHz Operation
LTC3714
Intel and Transmeta Compatible DC/DC Controller with V20 and
Internal Op Amp
0.6V ≤ VOUT ≤ 1.75V, 4V ≤ VIN ≤ 36V, ±1% 0.6V Reference
LTC3732
3-Phase, VRM 9.0/9.1 Synchronous Step-Down Controller
600kHz per Phase, ±5% Output Current Matching,
Integrated Drivers, SSOP-36
Burst Mode is a registered trademark of Linear Technology Corporation.
3711f
24 Linear Technology Corporation
LT/TP 1202 2K • PRINTED IN USA
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