LTC4267-3
Power over Ethernet
IEEE 802.3af PD Interface with
Integrated Switching Regulator
Description
Features
Complete Power Interface Port for IEEE 802®.3af
Powered Device (PD)
nn Onboard 100V, UVLO Switch
nn Constant-Frequency 300kHz Operation
nn Precision Dual Level Inrush Current Limit
nn Integrated Current Mode Switching Regulator
nn Onboard 25k Signature Resistor with Disable
nn Programmable Classification Current (Class 0-4)
nn Thermal Overload Protection
nn Power Good Signal
nn Integrated Error Amplifier and Voltage Reference
nn Low Profile 16-Pin SSOP or DFN Packages
The LTC®4267-3 combines an IEEE 802.3af compliant
Powered Device (PD) interface with a 300kHz current mode
switching regulator, providing a complete power solution
for PD applications. The LTC4267-3 integrates the 25k
signature resistor, classification current source, thermal
overload protection, signature disable and power good
signal along with an undervoltage lockout optimized for
use with the IEEE-required diode bridge. The LTC4267-3
provides an increased operational current limit, maximizing
power available for class 3 applications.
nn
Applications
IP Phone Power Management
Wireless Access Points
nn Security Cameras
nn Power over Ethernet
nn
nn
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
LTPoE++ is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Typical Application
The 300kHz current mode switching regulator provides
higher output power or smaller external size compared
to its lower frequency counterparts. The LTC4267-3 is
designed for driving a 6V rated N-channel MOSFET and
features programmable slope compensation, soft-start,
and constant-frequency operation, minimizing noise even
with light loads. The LTC4267-3 includes an onboard error amplifier and voltage reference allowing use in both
isolated and nonisolated configurations.
The LTC4267-3 is available in a space saving, low profile
16-pin SSOP or DFN packages.
Class 2 PD with 3.3V Isolated Power Supply
SBM1040
PA1133
–48V
FROM
DATA PAIR
10k
+
HD01
VPORTP
–
SMAJ58A
+
HD01
–
PVCC
PWRGD
LTC4267-3
NGATE
0.1µF
–48V
FROM
SPARE PAIR
3.3V
1.5A
SENSE
RCLASS
68.1Ω
1%
RCLASS
ITH/RUN
+
PVCC
4.7µF
PGND
VPORTN
POUT
•
5µF
MIN
•
320µF
MIN
CHASSIS
Si3440
10k
PVCC
0.1Ω
470Ω
6.8k
VFB
SIGDISA
+
22nF
100k
BAS516
PS2911
TLV431
60.4k
42671 TA01
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1
LTC4267-3
Absolute Maximum Ratings
(Note 1)
VPORTN with Respect to VPORTP Voltage... 0.3V to –100V
POUT, SIGDISA, PWRGD
Voltage......................VPORTN + 100V to VPORTN –0.3V
PVCC to PGND Voltage (Note 2)
Low Impedance Source............................ –0.3V to 8V
Current Fed...........................................5mA into PVCC
RCLASS Voltage.................VPORTN + 7V to VPORTN – 0.3V
PWRGD Current......................................................10mA
RCLASS Current.....................................................100mA
NGATE to PGND Voltage............................–0.3V to PVCC
VFB, ITH/RUN to PGND Voltages................ –0.3V to 3.5V
SENSE to PGND Voltage............................... –0.3V to 1V
NGATE Peak Output Current ( VITHSHDN
AND PVCC > VTURNON
(NOMINALLY 8.7V)
LTC4267-3
PWM
ENABLED
42673 F08
Figure 8. LTC4267-3 Switching Regulator
Start-Up/Shutdown State Diagram
The undervoltage lockout mechanism on PVCC prevents
the LTC4267-3 switching regulator from trying to drive
the external N-Channel MOSFET with insufficient gate-tosource voltage. The voltage at the PVCC pin must exceed
VTURNON (nominally 8.7V with respect to PGND) at least
momentarily to enable operation. The PVCC voltage must
fall to VTURNOFF (nominally 5.7V with respect to PGND)
before the undervoltage lockout disables the switching
regulator. This wide UVLO hysteresis range supports
applications where a bias winding on the flyback transformer is used to increase the efficiency of the LTC4267-3
switching regulator.
The ITH/RUN can be driven below VITHSHDN (nominally 0.28V
with respect to PGND) to force the LTC4267-3 switching
regulator into shutdown. An internal 0.3µA current source
always tries to pull the ITH/RUN pin towards PVCC. When
the ITH/RUN pin voltage is allowed to exceed VITHSHDN and
PVCC exceeds VTURNON, the LTC4267-3 switching regulator
begins to operate and an internal clamp immediately pulls
the ITH/RUN pin to about 0.7V. In operation, the ITH/RUN
pin voltage will vary from roughly 0.7V to 1.9V to represent
current comparator thresholds from zero to maximum.
Internal Soft-Start
An internal soft-start feature is enabled whenever the
LTC4267-3 switching regulator comes out of shutdown.
Specifically, the ITH/RUN voltage is clamped and is
prevented from reaching maximum until 1.4ms have
passed. This allows the input current of the PD to rise in a
smooth and controlled manner on start-up and stay within
the current limit requirement of the LTC4267-3 interface.
16
The LTC4267-3 switching regulator injects a 5µA peak
current ramp out through its SENSE pin which can be
used for slope compensation in designs that require it.
This current ramp is approximately linear and begins at
zero current at 6% duty cycle, reaching peak current at
80% duty cycle. Programming the slope compensation
via a series resistor is discussed in the External Interface
and Component Selection section.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Input Interface Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer (Figure 9). For
PoE devices, the isolation transformer must include a
center tap on the media (cable) side. Proper termination
is required around the transformer to provide correct
impedance matching and to avoid radiated and conducted
emissions. Transformer vendors such as Bel Fuse, Coilcraft, Pulse and Tyco (Table 3) can provide assistance with
selection of an appropriate isolation transformer and proper
termination methods. These vendors have transformers
specifically designed for use in PD applications.
Table 3. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
FAX: 201-432-9542
http://www.belfuse.com
Coilcraft, Inc.
1102 Silver Lake Road
Cary, IL 60013
Tel: 847-639-6400
FAX: 847-639-1469
http://www.coilcraft.com
Pulse Engineering
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
FAX: 858-674-8262
http://www.pulseeng.com
Tyco Electronics
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
FAX: 650-361-2508
http://www.circuitprotection.com
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LTC4267-3
Applications Information
Diode Bridge
IEEE 802.3af allows power wiring in either of two configurations: on the TX/RX wires or via the spare wire pairs in
the RJ45 connector. The PD is required to accept power in
either polarity on either the main or spare inputs; therefore
it is common to install diode bridges on both inputs in
order to accommodate the different wiring configurations.
Figure 9 demonstrates an implementation of these diode
bridges. The IEEE 802.3af specification also mandates
that the leakage back through the unused bridge be less
than 28µA when the PD is powered with 57V.
The LTC4267-3 has several different modes of operation
based on the voltage present between VPORTN and VPORTP
pins. The forward voltage drop of the input diodes in a
PD design subtracts from the input voltage and will affect the transition point between modes. When using the
LTC4267‑3, it is necessary to pay close attention to this
forward voltage drop. Selection of oversized diodes will help
keep the PD thresholds from exceeding IEEE specifications.
The input diode bridge of a PD can consume over 4% of
the available power in some applications. It may be desirable to use Schottky diodes in order to reduce power
loss. However, if the standard diode bridge is replaced
with a Schottky bridge, the transition points between the
modes will be affected. Figure 10 shows a technique for
using Schottky diodes while maintaining proper threshold
RJ45
1
2
3
6
4
TX+
16 T1 1
15
2
TX–
14
3
RX+
11
6
10
7
9
8
RX–
8
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 9) is used to
meet the AC impedance requirement.
Input Series Resistance
Linear Technology has seen the customer community cable
discharge requirements increase by nearly 500,000 times
the original test levels. The PD must survive and operate
reliably not only when an initially charged cable connects
and dissipates the energy through the PD front end, but
also when the electrical power system grounds are subject
to very high energy events (e.g. lightning strikes).
In these high energy events, adding 10Ω series resistance
into the VPORTP pin greatly improves the robustness of the
LTC4267-3 based PD. (see Figure 9.) The TVS limits the
voltage across the port while the 10Ω and 0.1µF capacitance reduces the edge rate the LTC4267-3 encounters
across its pin. The added 10Ω series resistance does not
operationally affect the LTC4267-3 PD Interface nor does
it affect its compliance with the IEEE 802.3 standard.
BR1
HD01
TO PHY
PULSE H2019
SPARE+
5
7
points to meet IEEE 802.3af compliance. D13 is added
to compensate for the change in UVLO turn-on voltage
caused by the Schottky diodes and consumes little power.
SPARE–
BR2
HD01
10Ω
D3
SMAJ58A
TVS
C14
0.1µF
100V
VPORTP
LTC4267-3
VPORTN
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Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor
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17
LTC4267-3
Applications Information
D11
B1100
D9
B1100
R2
75Ω
C3
0.01µF
200V
R1
75Ω
C7
0.01µF
200V
D10
B1100
10Ω
D12
B1100
C2
1000pF
2kV
J2
1
2
IN
FROM
PSE
3
6
TX+
16
T1
1
15
2
TX–
14
3
RX+
11
6
10
7
9
8
RX–
4
5
7
8
C11
0.1µF
100V
D6
SMAJ58A
OUT
TO PHY
TXOUT+
TXOUT–
D13
MMSD4148
RXOUT+
C25
0.01µF
200V
C24
0.01µF
200V
RXOUT–
R31
75Ω
R30
75Ω
D14
B1100
SPARE+
D15
B1100
SPARE–
RJ45
RCLASS
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE 5%
2. SELECT RCLASS FOR CLASS 1-4 OPERATION. REFER
TO DATA SHEET APPLICATIONS INFORMATION SECTION
C2: AVX 1808GC102MAT
D9 TO D12, D14 TO D17: DIODES INC., B1100
T1: PULSE H2019
D17
B1100
D16
B1100
RCLASS
1%
VPORTP
LTC4267-3
VPORTN
42673 F10
Figure 10. PD Front End with Isolation Transformer, Two Schottky Diode Bridges
Transient Voltage Suppressor
Classification Resistor Selection (RCLASS)
The LTC4267-3 specifies and absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4267-3, install a transient voltage suppressor (D3)
between the input diode bridge and the LTC4267-3 as
shown in Figure 9. A SMAJ58A is recommended for typical
PD applications. However, a SMBJ58A may be preferred in
applications where the PD front-end must absorb higher
energy discharge events.
The IEEE specification allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from RCLASS to
VPORTN (Figure 4) sets the value of the load current. The
designer should determine which power category the PD
falls into and then select the appropriate value of RCLASS
from Table 2. If a unique load current is required, the value
of RCLASS can be calculated as:
18
RCLASS = 1.237V/(IDESIRED – IIN_CLASS)
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LTC4267-3
Applications Information
where IIN_CLASS is the LTC4267-3 IC supply current during classification and is given in the electrical specifications. The RCLASS resistor must be 1% or better to avoid
degrading the overall accuracy of the classification circuit.
Resistor power dissipation will be 50mW maximum and
is transient so heating is typically not a concern. In order
to maintain loop stability, the layout should minimize
capacitance at the RCLASS node. The classification circuit
can be disabled by floating the RCLASS pin. The RCLASS
pin should not be shorted to VPORTN as this would force
the LTC4267-3 classification circuit to attempt to source
very large currents and quickly go into thermal shutdown.
Power Good Interface
The PWRGD signal is controlled by a high voltage, opendrain transistor. The designer has the option of using this
signal to enable the onboard switching regulator through
the ITH/RUN or the PVCC pins. Examples of active-high
interface circuits for controlling the switching regulator
are shown in Figure 7.
In some applications, it is desirable to ignore intermittent
power bad conditions. This can be accomplished by including capacitor C15 in Figure 7 to form a lowpass filter.
With the components shown, power bad conditions less
than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the switching regulator using CPVCC or C17
as shown in Figure 7.
It is recommended that the designer use the power
good signal to enable the switching regulator. Using
PWRGD ensures the capacitor C1 has reached within
1.5V of the final value and is ready to accept a load. The
LTC4267-3 is designed with wide power good hysteresis
to handle sudden fluctuations in the load voltage and
current without prematurely shutting off the switching
regulator. Please refer to the Power-Up Sequencing of the
Application Information section.
Signature Disable Interface
To disable the 25k signature resistor, connect SIGDISA pin
to the VPORTP pin. Alternately, SIGDISA pin can be driven
high with respect to VPORTN. An example of a signature
disable interface is shown in Figure 16, option 2. Note that
the SIGDISA input resistance is relatively large and the
threshold voltage is fairly low. Because of high voltages
present on the printed circuit board, leakage currents from
the VPORTP pin could inadvertently pull SIGDISA high. To
ensure trouble-free operation, use high voltage layout
techniques in the vicinity of SIGDISA. If unused, connect
SIGDISA to VPORTN.
Load Capacitor
The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5µF (provided by C1
in Figure 11). It is permissible to have a much larger load
capacitor and the LTC4267-3 can charge very large load
capacitors before thermal issues become a problem. The
load capacitor must be large enough to provide sufficient
energy for proper operation of the switching regulator.
However, the capacitor must not be too large or the PD
design may violate IEEE 802.3af requirements.
If the load capacitor is too large, there can be a problem
with inadvertent power shutdown by the PSE. Consider
the following scenario. If the PSE is running at –57V
(maximum allowed) and the PD has detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V (minimum allowed), the input bridge will reverse bias
and the PD power will be supplied by the load capacitor.
Depending on the size of the load capacitor and the DC load
of the PD, the PD will not draw any power for a period of
time. If this period of time exceeds the IEEE 802.3af 300ms
disconnect delay, the PSE will remove power from the PD.
For this reason, it is necessary to ensure that inadvertent
shutdown cannot occur.
Very small output capacitors (≤10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily, causing the capacitor to charge at a somewhat reduced rate.
Conversely, charging a very large capacitor may cause the
current limit to increase slightly. In either case, once the
output voltage reaches its final value, the input current
limit will be restored to its nominal value.
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LTC4267-3
Applications Information
The load capacitor can store significant energy when fully
charged. The design of a PD must ensure that this energy
is not inadvertently dissipated in the LTC4267-3. The
polarity-protection diode(s) prevent an accidental short on
the cable from causing damage. However, if the VPORTN
pin is shorted to VPORTP inside the PD while the capacitor
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4267-3.
Maintain Power Signature
In an IEEE 802.3af system, the PSE uses the Maintain
Power Signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25k in parallel with 0.05µF. If either the DC current
is less than 10mA or the AC impedance is above 26.25k,
the PSE may disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2M
to guarantee power will be removed.
Selecting Feedback Resistor Values
The regulated output voltage of the switching regulator is
determined by the resistor divider across VOUT (R1 and
R2 in Figure 11) and the error amplifier reference voltage
VREF. The ratio of R2 to R1 needed to produce the desired
voltage can be calculated as:
R2 = R1 • (VOUT – VREF)/VREF
In an isolated power supply application, VREF is determined
by the designer’s choice of an external error amplifier.
Commercially available error amplifiers or programmable
shunt regulators may include an internal reference of
1.25V or 2.5V. Since the LTC4267-3 internal reference
and error amplifier are not used in an isolated design, tie
the VFB pin to PGND.
In a nonisolated power supply application, the LTC4267‑3
onboard internal reference and error amplifier can be
used. The resistor divider output can be tied directly to
the VFB pin. The internal reference of the LTC4267-3 is
0.8V nominal.
20
Choose resistance values for R1 and R2 to be as large as
possible to minimize any efficiency loss due to the static
current drawn from VOUT, but just small enough so that
when VOUT is in regulation, the error caused by the nonzero
input current from the output of the resistor divider to the
error amplifier pin is less than 1%.
Error Amplifier and Opto-Isolator Considerations
In an isolated topology, the selection of the external error
amplifier depends on the output voltage of the switching
regulator. Typical error amplifiers include a voltage reference of either 1.25V or 2.5V. The output of the amplifier
and the amplifier upper supply rail are often tied together
internally. The supply rail is usually specified with a wide
upper voltage range, but it is not allowed to fall below the
reference voltage. This can be a problem in an isolated
switcher design if the amplifier supply voltage is not properly managed. When the switcher load current decreases
and the output voltage rises, the error amplifier responds
by pulling more current through the LED. The LED voltage
can be as large as 1.5V, and along with RLIM, reduces the
supply voltage to the error amplifier. If the error amp does
not have enough headroom, the voltage drop across the
LED and RLIM may shut the amplifier off momentarily,
causing a lock-up condition in the main loop. The switcher
will undershoot and not recover until the error amplifier
releases its sink current. Care must be taken to select the
reference voltage and RLIM value so that the error amplifier
always has enough headroom. An alternate solution that
avoids these problems is to utilize the LT1431 or LT4430
where the output of the error amplifier and amplifier supply
rail are brought out to separate pins.
The PD designer must also select an opto-isolator such
that its bandwidth is sufficiently wider than the bandwidth
of the main control loop. If this step is overlooked, the
main control loop may be difficult to stabilize. The output
collector resistor of the opto-isolator can be selected for
an increase in bandwidth at the cost of a reduction in gain
of this stage.
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LTC4267-3
Applications Information
Output Transformer Design Considerations
Since the external feedback resistor divider sets the
output voltage, the PD designer has relative freedom in
selecting the transformer turns ratio. The PD designer
can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)
which yields more freedom in setting the total turns and
mutual inductance and may allow the use of an off the
shelf transformer.
Transformer leakage inductance on either the primary or
secondary causes a voltage spike to occur after the output
switch (Q1 in Figure 11) turns off. The input supply voltage plus the secondary-to-primary referred voltage of the
flyback pulse (including leakage spike) must not exceed
the allowed external MOSFET breakdown rating. This spike
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In some cases,
a “snubber” circuit will be required to avoid overvoltage
breakdown at the MOSFET’s drain node. Application
Note 19 is a good reference for snubber design.
Current Sense Resistor Consideration
The external current sense resistor (RSENSE in Figure 11)
allows the designer to optimize the current limit behavior
for a particular application. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak swing current goes from a fraction of an ampere to
several amperes. Care must be taken to ensure proper
circuit operation, especially for small current sense resistor values.
Choose RSENSE such that the switching current exercises
the entire range of the ITH/RUN voltage. The nominal voltage
range is 0.7V to 1.9V and RSENSE can be determined by
experiment. The main loop can be temporarily stabilized by
connecting a large capacitor on the power supply. Apply
the maximum load current allowable at the power supply output based on the class of the PD. Choose RSENSE
such that ITH/RUN approaches 1.9V. Finally, exercise the
output load current over the entire operating range and
ensure that ITH/RUN voltage remains within the 0.7V to
1.9V range. Layout is critical around the RSENSE resistor.
For example, a 0.020Ω sense resistor, with one milliohm
(0.001Ω) of parasitic resistance will cause a 5% reduction
in peak switch current. The resistance of printed circuit
copper traces cannot necessarily be ignored and good
layout techniques are mandatory.
Programmable Slope Compensation
The LTC4267-3 switching regulator injects a ramping
current through its SENSE pin into an external slope
compensation resistor (RSL in Figure 11). This current
ramp starts at zero after the NGATE pin has been high for
the LTC4267-3’s minimum duty cycle of 6%. The current
rises linearly towards a peak of 5µA at the maximum duty
cycle of 80%, shutting off once the NGATE pin goes low.
A series resistor (RSL) connecting the SENSE pin to the
current sense resistor (RSENSE) develops a ramping voltage drop. From the perspective of the LTC4267-3 SENSE
pin, this ramping voltage adds to the voltage across the
sense resistor, effectively reducing the current comparator
threshold in proportion to duty cycle. This stabilizes the
control loop against subharmonic oscillation. The amount
of reduction in the current comparator threshold (∆VSENSE)
can be calculated using the following equation:
ΔVSENSE = 5µA • RSL • [(Duty Cycle – 6%)/74%]
Note: The LTC4267-3 enforces 6% < Duty Cycle < 80%.
Designs not needing slope compensation may replace RSL
with a short-circuit.
Applications Employing a Third Transformer Winding
A standard operating topology may employ a third winding on the transformer’s primary side that provides power
to the LTC4267-3 switching regulator via its PVCC pin
(Figure 11). However, this arrangement is not inherently
self-starting. Start-up is usually implemented by the use of
an external “trickle-charge” resistor (RSTART) in conjunction with the internal wide hysteresis undervoltage lockout
circuit that monitors the PVCC pin voltage.
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LTC4267-3
Applications Information
ISOLATED DESIGN EXAMPLE
–48V
FROM
DATA PAIR
+
C1
RSTART
–
LPRI
PGND
PVCC
VPORTP
–48V
FROM
SPARE PAIR
+
–
VPORTN
NGATE
VPORTN
RSL
RLIM
RSENSE
PGND
VPORTP
VFB
ITH/RUN
COUT
LSEC
Q1
SENSE
LTC4267-3
SIGDISA
POUT
•
PGND
RCLASS
RCLASS
VOUT
•
CPVCC
PVCC
0.1µF
100V
D1
T1
VPORTP
OPTOISOLATOR
PGND
PVCC
PGND
ERROR
AMPLIFIER
RC
CC
R2
R1
PGND
CISO
NONISOLATED DESIGN EXAMPLE
T1
LBIAS
D2
–48V
FROM
DATA PAIR
+
R3
RSTART
–
0.1µF
100V
+
D1
VPORTP
C1
LPRI
PGND
NGATE
–
ITH/RUN
CC
POUT
LSEC
PGND
RSENSE
R2
VFB
PGND
COUT
Q1
SENSE
LTC4267-3
SIGDISA
VPORTN
•
RSL
RCLASS
RCLASS
VOUT
•
CPVCC
PGND
PVCC
–48V
FROM
SPARE PAIR
•
PGND
PGND
R1
42673 F11
PGND
Figure 11. Typical LTC4267-3 Application Circuits
22
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LTC4267-3
Applications Information
RSTART is connected to VPORTP and supplies a current,
typically 100µA, to charge CPVCC. After some time, the
voltage on CPVCC reaches the PVCC turn-on threshold. The
LTC4267-3 switching regulator then turns on abruptly and
draws its normal supply current. The NGATE pin begins
switching and the external MOSFET (Q1) begins to deliver
power. The voltage on CPVCC begins to decline as the
switching regulator draws its normal supply current, which
exceeds the delivery from RSTART. After some time, typically
tens of milliseconds, the output voltage approaches the
desired value. By this time, the third transformer winding
is providing virtually all the supply current required by the
LTC4267-3 switching regulator.
One potential design pitfall is under-sizing the value of
capacitor CPVCC. In this case, the normal supply current
drawn through PVCC will discharge CPVCC rapidly before the
third winding drive becomes effective. Depending on the
particular situation, this may result in either several off-on
cycles before proper operation is reached or permanent
relaxation oscillation at the PVCC node.
Resistor RSTART should be selected to yield a worst-case
minimum charging current greater that the maximum rated
LTC4267-3 start-up current to ensure there is enough current to charge CPVCC to the PVCC turn-on threshold. RSTART
should also be selected large enough to yield a worst-case
maximum charging current less than the minimum-rated
PVCC supply current, so that in operation, most of the
PVCC current is delivered through the third winding. This
results in the highest possible efficiency.
Capacitor CPVCC should then be made large enough to avoid
the relaxation oscillation behavior described previously.
This is difficult to determine theoretically as it depends on
the particulars of the secondary circuit and load behavior.
Empirical testing is recommended.
The third transformer winding should be designed so
that its output voltage, after accounting for the forward
diode voltage drop, exceeds the maximum PVCC turn-off
threshold. Also, the third winding’s nominal output voltage
should be at least 0.5V below the minimum rated PVCC
clamp voltage to avoid running up against the LTC4267-3
shunt regulator, needlessly wasting power.
PVCC Shunt Regulator
In applications including a third transformer winding,
the internal PVCC shunt regulator serves to protect the
LTC4267-3 switching regulator from overvoltage transients
as the third winding is powering up.
If a third transformer winding is undesirable or unavailable, the shunt regulator allows the LTC4267-3 switching
regulator to be powered through a single dropping resistor
from VPORTP as shown in Figure 12. This simplicity comes
at the expense of reduced efficiency due to static power
dissipation in the RSTART dropping resistor.
The shunt regulator can sink up to 5mA through the PVCC
pin to PGND. The values of RSTART and CPVCC must be
selected for the application to withstand the worst-case
load conditions and drop on PVCC, ensuring that the PVCC
turn-off threshold is not reached. CPVCC should be sized
sufficiently to handle the switching current needed to drive
NGATE while maintaining minimum switching voltage.
+
VPORTP
RSTART
–48
FROM
PSE
PVCC
LTC4267-3
CPVCC
PGND
–
VPORTN POUT
PGND
42673 F14
Figure 12. Powering the LTC4267-3 Switching
Regulator via the Shunt Regulator
42673fb
For more information www.linear.com/LTC4267-3
23
LTC4267-3
Applications Information
External Preregulator
Compensating the Main Loop
The circuit in Figure 13 shows a third way to power the
LTC4267-3 switching regulator circuit. An external series
preregulator consists of a series pass transistor Q1, zener
diode D1, and a bias resistor RB. The preregulator holds
PVCC at 7.6V nominal, well above the maximum rated PVCC
turn-off threshold of 6.8V. Resistor RSTART momentarily
charges the PVCC node up to the PVCC turn-on threshold,
enabling the switching regulator. The voltage on CPVCC
begins to decline as the switching regulator draws its
normal supply current, which exceeds the delivery of
RSTART. After some time, the output voltage approaches
the desired value. By this time, the pass transistor Q1
catches the declining voltage on the PVCC pin, and provides
virtually all the supply current required by the LTC4267-3
switching regulator. CPVCC should be sized sufficiently to
handle the switching current needed to drive NGATE while
maintaining minimum switching voltage.
In an isolated topology, the compensation point is typically
chosen by the components configured around the external
error amplifier. Shown in Figure 14, a series RC network
is connected from the compare voltage of the error amplifier to the error amplifier output. In PD designs where
transient load response is not critical, replace RZ with a
short. The product of R2 and CC should be sufficiently large
to ensure stability. When fast settling transient response
is critical, introduce a zero set by RZCC. The PD designer
must ensure that the faster settling response of the output
voltage does not compromise loop stability.
+
CC
RZ
TO OPTOISOLATOR
VOUT
R2
R1
42673 F14
Figure 14. Main Loop Compensation for an Isolated Design
RB
VPORTP
– 48
FROM
PSE
PVCC
RSTART
Q1
D1
8.2V
PGND
LTC4267-3
PGND
CPVCC
PGND
–
VPORTN POUT
PGND
In a nonisolated design, the LTC4267-3 incorporates an
internal error amplifier where the ITH/RUN pin serves as
a compensation point. In a similar manner, a series RC
network can be connected from ITH/RUN to PGND as
shown in Figure 15. CC and RZ are chosen for optimum
load and line transient response.
42673 F15
Figure 13. Powering the LTC4267-3 Switching
Regulator with an External Preregulator
LTC4267-3
ITH/RUN
The external preregulator has improved efficiency over
the simple resistor-shunt regulator method mentioned
previously. RB can be selected so that it provides a small
current necessary to maintain the zener diode voltage and
the maximum possible base current Q1 will encounter. The
actual current needed to power the LTC4267-3 switching
regulator goes through Q1 and PVCC sources current on
an “as-needed” basis. The static current is then limited
only to the current through RB and D1.
24
CC
PGND
RZ
42673 F15
Figure 15. Main Loop Compensation for a Nonisolated Design
42673fb
For more information www.linear.com/LTC4267-3
LTC4267-3
Applications Information
Selecting the Switching Transistor
With the N-channel power MOSFET driving the primary of
the transformer, the inductance will cause the drain of the
MOSFET to traverse twice the voltage across VPORTP and
PGND. The LTC4267-3 operates with a maximum supply
of – 57V; thus the MOSFET must be rated to handle 114V
or more with sufficient design margin. Typical transistors have 150V ratings while some manufacturers have
developed 120V rated MOSFETs specifically for Powerover-Ethernet applications.
The NGATE pin of the LTC4267-3 drives the gate of the
N-channel MOSFET. NGATE will traverse a rail-to-rail voltage from PGND to PVCC. The designer must ensure the
MOSFET provides a low “ON” resistance when switched
to PVCC as well as ensure the gate of the MOSFET can
handle the PVCC supply voltage.
For high efficiency applications, select an N-channel
MOSFET with low total gate charge. The lower total gate
charge improves the efficiency of the NGATE drive circuit
and minimizes the switching current needed to charge
and discharge the gate.
Auxiliary Power Source
In some applications, it may be desirable to power the
PD from an auxiliary power source such as a wall transformer. The auxiliary power can be injected into the PD
at several locations and various trade-offs exist. Power
can be injected at the 3.3V or 5V output of the isolated
power supply with the use of a diode ORing circuit. This
method accesses the internal circuits of the PD after the
isolation barrier and therefore meets the 802.3af isolation safety requirements for the wall transformer jack on
the PD. Power can also be injected into the PD interface
portion of the LTC4267-3. In this case, it is necessary to
ensure the user cannot access the terminals of the wall
transformer jack on the PD since this would compromise
the 802.3af isolation safety requirements.
Figure 16 demonstrates three methods of diode ORing
external power into a PD. Option 1 inserts power before
the LTC4267-3 interface controller while options 2 and
3 bypass the LTC4267-3 interface controller section and
power the switching regulator directly.
If power is inserted before the LTC4267-3 interface controller, it is necessary for the wall transformer to exceed
the LTC4267-3 UVLO turn-on requirement and include a
transient voltage suppressor (TVS) to limit the maximum
voltage to 57V. This option provides input current limit
for the transformer, provides a valid power good signal,
and simplifies power priority issues. As long as the wall
transformer applies power to the PD before the PSE, it
will take priority and the PSE will not power up the PD
because the wall power will corrupt the 25k signature. If
the PSE is already powering the PD, the wall transformer
power will be in parallel with the PSE. In this case, priority will be given to the higher supply voltage. If the wall
transformer voltage is higher, the PSE should remove the
line voltage since no current will be drawn from the PSE.
On the other hand, if the wall transformer voltage is lower,
the PSE will continue to supply power to the PD and the
wall transformer will not be used. Proper operation should
occur in either scenario.
If auxiliary power is applied directly to the LTC4267-3
switching regulator (bypassing the LTC4267-3 PD interface), a different set of trade-offs arise. In the configuration
shown in option 2, the wall transformer does not need
to exceed the LTC4267-3 turn-on UVLO requirement;
however, it is necessary to include diode D9 to prevent
the transformer from applying power to the LTC4267-3
interface controller. The transformer voltage requirement
will be governed by the needs of the onboard switching
regulator. However, power priority issues require more
intervention. If the wall transformer voltage is below
the PSE voltage, then priority will be given to the PSE
power. The LTC4267-3 interface controller will draw power
42673fb
For more information www.linear.com/LTC4267-3
25
LTC4267-3
Applications Information
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4267-3 PD
RJ45
1
2
3
6
TX+
TX
T1
~
–
RX+
BR1
HD01
TO PHY
~
RX–
D3
SMAJ58A
TVS
+
C14
0.1µF
100V
RSTART
–
C1
VPORTP
SPARE+
4
~
5
7
LTC4267-3
BR2
HD01
–
SPARE
8
PVCC
+
~
+
CPVCC
PGND
–
VPORTN POUT
PGND
D8
S1B
ISOLATED
WALL
38V TO 57V
TRANSFORMER
–
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4267-3 PD WITH SIGNATURE DISABLED
RJ45
1
2
3
6
TX+
T1
~
TX–
RX+
+
~
100k
C14
0.1µF
100V
BR1
HD01
TO PHY
RX–
D3
SMAJ58A
TVS
–
C1
BSS63
VPORTP
SPARE+
4
~
5
7
SPARE
ISOLATED
WALL
TRANSFORMER
~
+
100k
SIGDISA
PVCC
LTC4267-3
PGND
BR2
HD01
–
8
+
RSTART
–
CPVCC
VPORTN POUT
PGND
D9
S1B
–
D10
S1B
OPTION 3: AUXILIARY POWER APPLIED TO LTC4267-3 PD AND SWITCHING REGULATOR
RJ45
1
2
3
6
4
TX+
TX
T1
~
–
RX+
BR1
HD01
TO PHY
~
RX–
8
D3
SMAJ58A
TVS
C14
0.1µF
100V
RSTART
–
C1
VPORTP
SPARE+
~
5
7
+
+
BR2
HD01
–
SPARE
ISOLATED
WALL
TRANSFORMER
+
~
38V TO 57V
–
PVCC
LTC4267-3
CPVCC
PGND
–
VPORTN POUT
PGND
D10
S1B
42673 F16
Figure 16. Auxiliary Power Source for PD
26
42673fb
For more information www.linear.com/LTC4267-3
LTC4267-3
Applications Information
from the PSE while the transformer will sit unused. This
configuration is not a problem in a PoE system. On the
other hand, if the wall transformer voltage is higher than
the PSE voltage, the LTC4267-3 switching regulator will
draw power from the transformer. In this situation, it is
necessary to address the issue of power cycling that may
occur if a PSE is present. The PSE will detect the PD and
apply power. If the switcher is being powered by the wall
transformer, then the PD will not meet the minimum load
requirement and the PSE will subsequently remove power.
The PSE will again detect the PD and power cycling will
start. With a transformer voltage above the PSE voltage,
it is necessary to either disable the signature, as shown
in option 2, or install a minimum load on the output of the
LTC4267-3 interface to prevent power cycling.
The third option also applies power directly to the
LTC4267‑3 switching regulator, bypassing the LTC4267‑3
interface controller and omitting diode D9. With the
diode omitted, the transformer voltage is applied to the
LTC4267-3 interface controller in addition to the switching
regulator. For this reason, it is necessary to ensure that
the transformer maintain the voltage between 38V and 57V
to keep the LTC4267-3 interface controller in its normal
operating range. The third option has the advantage of
automatically disabling the 25k signature resistor when
the external voltage exceeds the PSE voltage.
Power-Up Sequencing the LTC4267-3
The LTC4267-3 consists of two functional cells, the PD
interface and the switching regulator, and the power up
sequencing of these two cells must be carefully considered.
The PD designer should ensure that the switching regulator
does not begin operation until the interface has completed
charging up the load capacitor. This will ensure that the
switcher load current does not compete with the load
capacitor charging current provided by the PD interface
current limit circuit. Overlooking this consideration may
result in slow power supply ramp up, power-up oscillation,
and possibly thermal shutdown.
The LTC4267-3 includes a power good signal in the PD
interface that can be used to indicate to the switching regulator that the load capacitor is fully charged and ready to
handle the switcher load. Figure 7 shows two examples of
ways the PWRGD signal can be used to control the switching regulator. The first example employs an N-channel
MOSFET to drive the ITH/RUN port below the shutdown
threshold (typically 0.28V). The second example drives
PVCC below the PVCC turn-off threshold. Employing the
second example has the added advantage of adding delay
to the switching regulator start-up beyond the time the
power good signal becomes active. The second example
ensures additional timing margin at start-up without the
need for added delay components. In applications where it
is not desirable to utilize the power good signal, sufficient
timing margin can be achieved with RSTART and CPVCC.
RSTART and CPVCC should be set to a delay of two to three
times longer than the duration needed to charge up C1.
Layout Considerations for the LTC4267-3
The most critical layout considerations for the LTC4267-3
are the placement of the supporting external components
associated with the switching regulator. Efficiency, stability, and load transient response can deteriorate without
good layout practices around critical components.
For the LTC4267-3 switching regulator, the current loop
through C1, T1 primary, Q1, and RSENSE must be given
careful layout attention. (Refer to Figure 11.) Because of
the high switching current circulating in this loop, these
components should be placed in close proximity to each
other. In addition, wide copper traces or copper planes
should be used between these components. If vias are
necessary to complete the connectivity of this loop, placing
multiple vias lined perpendicular to the flow of current is
essential for minimizing parasitic resistance and reducing
current density. Since the switching frequency and the
power levels are substantial, shielding and high frequency
layout techniques should be employed. A low current,
42673fb
For more information www.linear.com/LTC4267-3
27
LTC4267-3
Applications Information
low impedance alternate connection should be employed
between the PGND pins of the LTC4267-3 and the PGND
side of RSENSE, away from the high current loop. This
Kelvin sensing will ensure an accurate representation of
the sense voltage is measured by the LTC4267-3.
The placement of the feedback resistors R1 and R2 as
well as the compensation capacitor CC is very important
in the accuracy of the output voltage, the stability of the
main control loop, and the load transient response. In
an isolated design application, R1, R2, and CC should be
placed as close as possible to the error amplifier’s input
with minimum trace lengths and minimum capacitance. In
a nonisolated application, R1, and R2 should be placed as
close as possible to the VFB pin of the LTC4267-3 and CC
should be placed close to the ITH/RUN pin of the LTC4267-3.
28
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure successful operation of the LTC4267-3 in a PD.
Place C14 (Figure 9) as close as physically possible to the
LTC4267-3. Place the series 10Ω resistor close to C14.
Excessive parasitic capacitance on the RCLASS pin should
be avoided. The SIGDISA pin is adjacent to the VPORTP
pin and any coupling, whether resistive or capacitive may
inadvertently disable the signature resistance. To ensure
consistent behavior, the SIGDISA pin should be electrically connected and not left floating. Voltages in a PD can
be as large as –57V, so high voltage layout techniques
should be employed.
42673fb
For more information www.linear.com/LTC4267-3
LTC4267-3
Typical Applications
Class 3 PD with 5V Nonisolated Power Supply
COILTRONICS
CTX-02-15242
4.7µH
12µF
100V
–48V
FROM
DATA PAIR
+
2.2µF
100V
100k
220k
VPORTP
HD01
300µF*
•
1µF
0.1µF
NGATE
+
HD01
–
RCLASS
45.3Ω
1%
10k
150pF
200V
VFB
SIGDISA
POUT
220Ω
SENSE
ITH/RUN
22nF
VPORTN
* THREE 100µF CERAMICS
FDC2512
PWRGD
SMAJ58A
–48V
FROM
SPARE PAIR
9.1V
PVCC
LTC4267-3
–
UPS840
•
MMBTA42
BAS516
10Ω
5V
1.8A
PGND
27k
0.04Ω
1%
42.2k
1%
42673 TA02
8.06k
1%
42673fb
For more information www.linear.com/LTC4267-3
29
J1
T1
T2
*
**
For more information www.linear.com/LTC4267-3
1
2
3
4
5
6
7
8
TO
PHY
TO
PHY
SMAJ58A
10Ω
45.3Ω
0.1µF
HALO HFJ11 RP28E-L12 INTEGRATED JACK
COILCRAFT D1766-AL
PULSE PA0184
TWO 100µF CAPACITORS IN PARALLEL
47µF AND 220µF IN PARALLEL
J1
9
10
11
12
13
14
12µF
100V
PVCC
2.2µF
100V
PGND
VFB
VPORTN
POUT
ITH/RUN
SENSE
SIGDISA
RCLASS
PWRGD
NGATE
LTC4267-3
VPORTP
4.7µH
220k
4.7µF
PVCC
BCX5616
8.2k
10p
51Ω
BAS516
6.8k
PVCC
10Ω
BAS516
8.2V
220k
0.1µF
2.2k
0.068
1%
MMBT3904
Si3440DV
•
T1
•
T2
1k
2.2nF
2kV
0.033µF
ZRL431
PH7030DL
Si3442DV
6.8nF
10k
4.7µF
PH7030DL
0.47µF
20Ω
BAT54SLT1
PS2911
•
•
•
30
•
Synchronous Class 3 PD with Triple Output Isolated Power Supplies
42673 TA03
49.9k
1%
49.9k
1%
PH7030DL
100µF
200µF*
267µF**
CHASSIS
1.8V
AT 2.5A
2.5V
AT 1.5A
3.3V
AT 0.5A
LTC4267-3
Typical Applications
42673fb
LTC4267-3
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706 Rev Ø)
0.65 ±0.05
3.50 ±0.05
1.65 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
5.00 ±0.10
(2 SIDES)
R = 0.20
TYP
3.00 ±0.10
(2 SIDES)
9
R = 0.115
TYP
0.40 ±0.10
16
1.65 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
0.200 REF
0.75 ±0.05
0.00 – 0.05
8
1
0.25 ±0.05
0.50 BSC
(DHC16) DFN 1103
4.40 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
42673fb
For more information www.linear.com/LTC4267-3
31
LTC4267-3
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.0250
(0.635)
BSC
GN16 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
32
42673fb
For more information www.linear.com/LTC4267-3
LTC4267-3
Revision History
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/12
Changed 12.95W IEEE 802.3af reference to 13.0W
9
Updated maximum power levels for class 0 and class 3 to 13.0W
12
Added 10Ω resistor to VPORTP pin in Figure 9 and Figure 10. Added Input Capacitor section, Input Series Resistance
section and Transient Voltage Suppressor section
Added C14 and 10Ω resistor layout recommendation
Added 10Ω resistor to VPORTP pin
B
7/15
Revised Exposed Pad pin description.
17, 18
28
29, 30, 34
8
42673fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC4267-3
33
LTC4267-3
Typical Application
High-Efficiency Class 3 PD with 3.3V Isolated Power Supply
10Ω
PULSE
PA1136
4.7µH
12µF
100V
2.2µF
100V
220k
220k
330Ω
510Ω
MMTBA42
9.1V
–48V
FROM
DATA PAIR
10Ω
MMSD4148
VPORTP
PVCC
B1100
(8 PLACES)
–48V
FROM
SPARE PAIR
•
ITH/RUN
0.068Ω
1%
PVCC
100k
VPORTN
*100µF CERAMIC + 470µF TANTALUM
POUT
CHASSIS
Si3440
45.3Ω
1%
SIGDISA
570µF*
•
10k
SENSE
RCLASS
3.3V
2.6A
BAS516
150pF
BAS516
PVCC
NGATE
SMAJ58A
SBM1040
•
4.7µF
LTC4267-3
0.1µF
470pF
PWRGD
500Ω
6.8k
33nF
BAS516
2N7002
10k
VFB
PVCC
100k
1%
PS2911
MMSD4148
PGND
TLV431
60.4k
1%
2200pF
2kV
42673 TA04
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC4265
IEEE 802.3at High Power PD Interface Controller 2-Event Classification Recognition, 100mA Inrush Current, Single-Class Programming
with 2-Event Classification
Resistor, Full Compliance to 802.3at
LTC4267-1
IEEE 802.3af PD Interface with Integrated
Switching Regulator
Internal 100V, 400mA Switch, Programmable Class, 200kHz Constant Frequency PWM
LTC4269-1
IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator
2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback
Controller, 50kHz to 250kHz, Auxiliary Support
LTC4269-2
IEEE 802.3at PD Interface with Integrated
Forward Switching Regulator
2-Event Classification, Programmable Classification, Synchronous Forward Controller,
100kHz to 500kHz, Auxiliary Support
LTC4278
2-Event Classification, Programmable Classification, Synchronous No-Opto Flyback
Controller, 50kHz to 250kHz, 12V Auxiliary Support
LT4275A
IEEE 802.3at PD Interface with Integrated
Flyback Switching Regulator
LTPoE++™ PD Controller
LT4275B
IEEE 802.3at PD Controller
External MOSFET for Lowest Power Dissipation and Highest System Efficiency,
2-Event Classification, Programmable Classification
LT4275C
IEEE 802.3at PD Controller
External MOSFET for Lowest Power Dissipation and Highest System Efficiency,
Programmable Classification
LTC4274
Single PoE PSE Controller
Provides Up to 90W, 2-Event Classification, and Port Current and Voltage Monitoring
LTC4266
Quad PoE PSE Controller
Provides Up to 90W, 2-Event Classification, and Port Current and Voltage Monitoring
34 Linear Technology Corporation
Provides Up to 90W, External MOSFET for Lowest Power Dissipation and Highest
System Efficiency, 2-Event Classification, Programmable Classification
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC4267-3
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC4267-3
42673fb
LT 0715 REV B • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2007
工商网监
湘ICP备2023018690号
