LTC4278
IEEE 802.3at PD with
Synchronous No-Opto Flyback
Controller and 12V Aux Support
DESCRIPTION
FEATURES
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25.5W IEEE 802.3at Compliant (Type 2) PD
10V to 57V Auxiliary Power Input
Shutdown Pin for Flexible Auxiliary Power Support
Integrated State-of-the-Art No-Opto Synchronous
Flyback Controller
– Isolated Power Supply Efficiency >92%
– 88% Efficiency Including Diode Bridge and
Hot Swap™ FET
Superior EMI Performance
Robust 100V 0.7Ω (Typ) Integrated Hot Swap MOSFET
IEEE 802.3at High Power Available Indicator
Integrated Signature Resistor and Programmable
Class Current
Undervoltage, Overvoltage and Thermal Protection
Short-Circuit Protection with Auto-Restart
Programmable Soft-Start and Switching Frequency
Complementary Power Good Indicators
Thermally Enhanced 7mm × 4mm DFN Package
The LTC®4278 is an integrated Powered Device (PD) controller and switching regulator intended for high power
IEEE 802.3at and 802.3af applications. With a wide input
voltage range, the LTC4278 is specifically designed to support PD applications that include a low-voltage auxiliary
power input such as a 12V wall adaptor. The inclusion of
a shutdown pin provides simple implementation of both
PoE and auxiliary dominate applications. In addition, the
LTC4278 supports both 1-event and 2-event classifications
as defined by the IEEE, thereby allowing the use in a wide
range of product configurations.
The LTC4278 synchronous, current mode, flyback controller generates multiple supply rails in a single conversion
step providing for the highest system efficiency while maintaining tight regulation across all outputs. The LTC4278
includes Linear Technology’s patented No-Opto feedback
topology to provide full IEEE 802.3 isolation without the
need of an opto-isolator circuit. A true soft-start function
allows graceful ramp-up of all output voltages.
APPLICATIONS
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The LTC4278 is available in a space saving 32-lead DFN
package.
VoIP Phones with Advanced Display Options
Dual-Radio Wireless Access Points
PTZ Security Cameras
RFID Readers
Industrial Controls
TYPICAL APPLICATION
L, LT, LTC, LTM, Linear Technology, SwitcherCAD and the Linear logo are registered
trademarks and Hot Swap and ThinSOT are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5841643.
EPC3472G-LF
25W PD Solution with 12V Auxiliary
•
0.18µH
8.2µH
+
AUXILIARY
SUPPLY
(10V TO 57V)
10µF
46.4k
54V FROM
DATA PAIR
54V FROM
SPARE PAIR
~ +
~ –
~ +
~ –
•
10µF
294k
BSS63
–
+
TO MICRO
CONTROLLER
UVLO PWRGD
VPORTP
HAT2169
FDMS2572
FB
VCC
PG
SENSE+
12mΩ
SENSE–
LTC4278
30.9Ω
SG
VCMP
VPORTN
VNEG
B1100
100µF
1µF
3.01k
T2P
SHDN
RCLASS
24k
•
5V
4.5A
21.5k
PDS5100H
0.1µF
+
47µF
SYNC GND OSC
PGDLY
12k
33pF
tON
ENDLY RCMP CCMP
100k
38.3k
•
1.8k
2.2nF
1µF
•
0.1µF
4278 TA01a
4278fc
1
LTC4278
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Pins with Respect to VPORTN
VPORTP Voltage.......................................... –0.3V to 100V
VNEG Voltage.......................................... –0.3V to VPORTP
VNEG Pull-Up Current...................................................1A
SHDN........................................................ –0.3V to 100V
RCLASS, Voltage............................................. –0.3V to 7V
RCLASS Source Current............................................50mA
PWRGD Voltage (Note 3)
Low Impedance Source.......VNEG –0.3V to VNEG +11V
Sink Current..........................................................5mA
PWRGD, T2P Voltage................................ –0.3V to 100V
PWRGD, T2P Sink Current......................................10mA
Pins with Respect to GND
VCC Voltage................................................. –0.3V to 22V
SENSE–, SENSE+ Voltage......................... –0.5V to +0.5V
UVLO, SYNC Voltage....................................–0.3V to VCC
FB Current...............................................................±2mA
VCMP Current..........................................................±1mA
Operating Ambient Temperature Range
LTC4278C................................................. 0°C to 70°C
LTC4278I..............................................–40°C to 85°C
SHDN
1
32 VPORTP
T2P
2
31 NC
RCLASS
3
30 PWRGD
NC
4
29 PWRGD
VPORTN
5
28 NC
VPORTN
6
27 VNEG
NC
7
NC
8
SG
9
26 VNEG
33
25 NC
24 PG
VCC 10
23 PGDLY
tON 11
22 RCMP
ENDLY 12
21 CCMP
SYNC 13
20 SENSE+
SFST 14
19 SENSE –
OSC 15
18 UVLO
FB 16
17 VCMP
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 2°C/W
GND, EXPOSED PAD (PIN 33) MUST BE SOLDERED TO A
HEAT SINKING PLANE THAT IS CONNECTED TO VNEG
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4278CDKD#PBF
LTC4278CDKD#TRPBF
4278
32-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
LTC4278IDKD#PBF
LTC4278IDKD#TRPBF
4278
32-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4278fc
2
LTC4278
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
60
9.8
21
37.2
V
V
V
V
V
V
Interface Controller (Note 4)
Operating Input Voltage
Signature Range
Classification Range
ON Voltage
OFF Voltage
Overvoltage Lockout
At VPORTP (Note 5)
l
l
l
l
1.5
12.5
30.0
71
ON/OFF Hysteresis Window
l
4.1
V
Signature/Class Hysteresis Window
l
1.4
V
State Machine Reset for 2-Event Classification
l
2.57
Supply Current at 57V
Measured at VPORTP Pin
Class 0 Current
Reset Threshold
5.40
V
l
1.35
mA
VPORTP = 17.5V, No RCLASS Resistor
l
0.40
mA
1.5V ≤ VPORTP ≤ 9.8V (Note 6)
l
26
kΩ
Supply Current
Signature
Signature Resistance
23.25
Invalid Signature Resistance, SHDN Invoked 1.5V ≤ VPORTP ≤ 9.8V, VSHDN = 3V (Note 6)
l
11
kΩ
Invalid Signature Resistance During Mark
Event
(Notes 6, 7)
l
11
kΩ
Class Accuracy
10mA < ICLASS < 40mA, 12.5V < VPORTP < 21V
(Notes 8, 9)
l
±3.5
%
Classification Stability Time
VPORTP Pin Step to 17.5V, RCLASS = 30.9, ICLASS Within 3.5%
of Ideal Value (Notes 8, 9)
l
1
ms
Inrush Current
VPORTP = 54V, VNEG = 3V
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100
180
mA
Power FET On-Resistance
Tested at 600mA into VNEG, VPORTP = 54V
l
0.7
1.0
Ω
Power FET Leakage Current at VNEG
VPORTP = SHDN = VNEG = 57V
l
1
µA
Classification
Normal Operation
60
Digital Interface
SHDN Input High Level Voltage
l
SHDN Input Low Level Voltage
l
3
V
0.45
100
V
SHDN Input Resistance
VPORTP = 9.8V, SHDN = 9.65V
l
PWRGD, T2P Output Low Voltage
Tested at 1mA, VPORTP = 54V. For T2P, Must Complete
2-Event Classification to See Active Low
l
0.15
V
PWRGD, T2P Leakage Current
Pin Voltage Pulled 57V, VPORTP = VPORTN = 0V
l
1
µA
PWRGD Output Low Voltage
Tested at 0.5mA, VPORTP = 52V, VNEG = 48V, Output Voltage
Is With Respect to VNEG
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0.4
V
PWRGD Clamp Voltage
Tested at 2mA, VNEG = 0V, Voltage With Respect to VNEG
l
16.5
V
PWRGD Leakage Current
VPWRGD = 11V, VNEG = 0V, Voltage With Respect to VNEG
l
1
µA
12
kΩ
4278fc
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LTC4278
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PWM Controller (Note 10)
Power Supply
VCC Operating Range
l
4.5
4
VCC Supply Current (ICC)
VCMP = Open (Note 11)
l
VCC Shutdown Current
VCMP = Open, VUVLO = 0V
l
20
V
6.4
10
mA
50
150
µA
1.237
1.251
V
Feedback Amplifier
Feedback Regulation Voltage (VFB)
l
Feedback Pin Input Bias Current
RCMP Open
Feedback Amplifier Transconductance
∆IC = ±10µA
Feedback Amplifier Source or Sink Current
1.220
200
l
700
l
25
nA
1000
1400
55
90
Feedback Amplifier Clamp Voltage
VFB = 0.9V
VFB = 1.4V
Reference Voltage Line Regulation
12V ≤ VCC ≤ 18V
Feedback Amplifier Voltage Gain
VCMP = 1.2V to 1.7V
Soft-Start Charging Current
VSFST = 1.5V
16
20
Soft-Start Discharge Current
VSFST = 1.5V, VUVLO = 0V
0.7
1.3
Control Pin Threshold (VCMP)
Duty Cycle = Min
2.56
0.84
0.005
l
µmho
µA
V
V
0.05
1400
%/ V
V/ V
25
µA
mA
1
V
Gate Outputs
7.4
8
V
l
0.01
0.05
V
l
1.6
2.3
V
PG, SG Output High Level
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PG, SG Output Low Level
6.6
PG, SG Output Shutdown Strength
VUVLO = 0V; IPG, ISG = 20mA
PG Rise Time
CPG = 1nF
SG Rise Time
CSG = 1nF
15
ns
PG, SG Fall Time
CPG, CSG = 1nF
10
ns
11
ns
Current Amplifier
Switch Current Limit at Maximum VCMP
VSENSE+
l
88
∆VSENSE /∆VCMP
Sense Voltage Overcurrent Fault Voltage
98
110
0.07
+, V
VSENSE
SFST < 1V
l
mV
V/ V
206
230
mV
100
110
kHz
200
pF
Timing
Switching Frequency (fOSC)
COSC = 100pF
Oscillator Capacitor Value (COSC)
(Note 12)
l
84
33
Minimum Switch On Time (tON(MIN))
200
ns
Flyback Enable Delay Time (tENDLY)
265
ns
PG Turn-On Delay Time (tPGDLY)
200
ns
88
%
Maximum Switch Duty Cycle
l
SYNC Pin Threshold
l
SYNC Pin Input Resistance
85
1.53
40
2.1
V
kΩ
4278fc
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LTC4278
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Load Compensation
Load Compensation to VSENSE Offset
Voltage
VRCMP with VSENSE+ = 0V
0.8
mV
Feedback Pin Load Compensation Current
VSENSE+ = 20mV, VFB = 1.230V
20
µA
UVLO Function
UVLO Pin Threshold (VUVLO)
UVLO Pin Bias Current
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VUVLO = 1.2V
VUVLO = 1.3V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: Active high PWRGD internal clamp self-regulates to 14V with
respect to VNEG.
Note 4: All voltages are with respect to VPORTN pin unless otherwise noted.
Note 5: Input voltage specifications are defined with respect to LTC4278
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 6: Signature resistance is measured via the ∆V/∆I method with the
minimum ∆V of 1V. The LTC4278 signature resistance accounts for the
additional series resistance in the input diode bridge.
1.215
1.240
1.265
V
–0.25
–4.50
0.1
–3.4
0.25
–2.50
µA
µA
Note 7: An invalid signature after the 1st classification event is mandated
by the IEEE802.3at standard. See the Applications Information section.
Note 8: Class accuracy is with respect to the ideal current defined as
1.237/RCLASS and does not include variations in RCLASS resistance.
Note 9: This parameter is assured by design and wafer level testing.
Note 10: VCC = 14V; PG, SG Open; VCMP = 1.4V, VSENSE– = 0V, RCMP = 1k,
RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. All
voltages are with respect to GND.
Note 11: Supply current does not include gate charge current to the
MOSFETs. See the Applications Information section.
Note 12: Component value range guaranteed by design.
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5
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
50
TA = 25°C
VPORTP CURRENT (mA)
VPORTP CURRENT (mA)
TA = 25°C
0.3
0.2
30
CLASS 3
20
CLASS 2
0.1
10
0
0
0
2
4
6
VPORTP VOLTAGE (V)
8
10
CLASS 1 OPERATION
CLASS 4
40
0.4
Input Current vs Input Voltage
11.0
VPORTP CURRENT (mA)
0.5
CLASS 1
CLASS 0
0
4278 G01
10
50
20
30
40
VPORTP VOLTAGE (V)
(RISING)
10.5
85°C
–40°C
10.0
9.5
60
12
14
20
18
16
VPORTP VOLTAGE (V)
4278 G03
4278 G02
Signature Resistance
vs Input Voltage
22
Class Operation vs Time
On-Resistance vs Temperature
28
26
1.0
LTC4278 + 2 DIODES
25
CLASS
CURRENT
10mA/DIV
24
LTC4278 ONLY
IEEE LOWER LIMIT
3
4
TIME (10µs/DIV)
9
10
7
5
8
6
VPORTP VOLTAGE (V)
0.2
–50
4278 G05
Active High PWRGD
Output Low Voltage vs Current
1.0
TA = 25°C
Inrush Current vs Input Voltage
TA = 25°C
VPORTP – VNEG = 4V
110
0.2
CURRENT (mA)
PWRGD (V)
0.4
0.6
0.4
0.2
2
6
4
CURRENT (mA)
8
10
4278 G07
100
115
0.8
0
0
25
50
75
–25
JUNCTION TEMPERATURE (°C)
4278 G06
0.6
0
0.6
4278 G04
PWRGD, T2P Output Low Voltage
vs Current
0.8
0.8
0.4
23
22
V1: 1
V2: 2
VPWRGD – VPORTN (V)
VT2P – VPORTN (V)
TA = 25°C
VPORTP
VOLTAGE
10V/DIV
RESISTANCE (Ω)
SIGNATURE RESISTANCE (kΩ)
RESISTANCE = ΔV = V2 – V1
ΔI I2 – I1
27 DIODES: HD01
TA = 25°C
IEEE UPPER LIMIT
0
105
100
95
90
0
0.5
1
1.5
CURRENT (mA)
2
4278 G08
85
40
45
50
55
VPORTP VOLTAGE (V)
60
4278 G09
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6
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Shutdown Current
vs Temperature
VCC Current vs Temperature
VUVLO = 0
80
70
108
DYNAMIC CURRENT CPG = 1nF,
CSG = 1nF, fOSC = 100kHz
106
8
VCC = 14V
7
IVCC (mA)
VCC CURRENT (µA)
110
9
60
SENSE Voltage vs Temperature
10
50
40
SENSE VOLTAGE (mV)
90
6
30
STATIC PART CURRENT
5
20
0
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
VCC = 14V
3
50
–50 –25
25
75
0
TEMPERATURE (°C)
125
SENSE Fault Voltage
vs Temperature
110
98
96
92
100
90
–50
125
108
210
205
200
195
190
1.240
COSC = 100pF
106
1.238
104
1.237
102
1.236
1.234
98
96
1.233
1.232
1.231
180
–50
90
–50
100
125
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1.230
–50
Feedback Pin Input Bias
vs Temperature
RCMP OPEN
250
1.04
70
1.03
50
1.02
100
1.00
0.99
0
–50 –25
100
125
4278 G17
0.96
–50
25°C
–40°C
10
–10
–50
0.97
50
25
75
0
TEMPERATURE (°C)
125°C
–30
0.98
50
125
100
Feedback Amplifier Output
Current vs VFB
30
1.01
IVCMP (µA)
VFB RESET (V)
150
50
25
0
75
TEMPERATURE (°C)
4278 G16
VFB Reset vs Temperature
200
–25
4278 G15
4278 G14
300
VFB vs Temperature
1.235
100
92
50
75
25
TEMPERATURE (°C)
125
100
1.239
94
0
50
25
0
75
TEMPERATURE (°C)
4278 G13
185
–25
–25
VFB (V)
+
fOSC (kHz)
SENSE VOLTAGE (mV)
100
Oscillator Frequency
vs Temperature
SENSE = VSENSE
–
215 WITH VSENSE = 0V
FEEDBACK PIN INPUT BIAS (nA)
102
4278 G12
4278 G02
220
104
94
4
10
FB = 1.1V
SENSE = VSENSE+
WITH VSENSE– = 0V
–25
0
50
75
25
TEMPERATURE (°C)
100
125
4278 G18
–70
0.9
1
1.1
1.2
VFB (V)
1.3
1.4
1.5
4278 G19
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7
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Amplifier Source and
Sink Current vs Temperature
1600
1550
1050
1500
1450
gm (µmho)
IVCMP (µA)
1650
SINK
CURRENT
VFB = 1.4V
60
1700
1100
SOURCE CURRENT
VFB = 1.1V
65
Feedback Amplifier Voltage Gain
vs Temperature
AV (V/V)
70
Feedback Amplifier gm
vs Temperature
1400
1000
55
1350
1300
50
950
1250
1200
45
1150
40
–50
–25
50
25
75
0
TEMPERATURE (°C)
100
125
900
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
–25
75
50
25
TEMPERATURE (°C)
0
UVLO vs Temperature
125
IUVLO Hysteresis vs Temperature
1.250
3.7
3.6
1.245
3.5
IUVLO (µA)
1.240
1.235
1.230
3.4
3.3
3.2
1.225
3.1
1.220
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
3.0
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
100
4278 G23
PG, SG Rise and Fall Times
vs Load Capacitance
80
22
70
21
60
20
50
TIME (ns)
23
19
18
16
10
75
50
25
TEMPERATURE (°C)
0
100
125
4278 G25
FALL TIME
30
20
–25
TA = 25°C
40
17
15
–50
125
4278 G24
Soft-Start Charge Current
vs Temperature
SFST CHARGE CURRENT (µA)
100
4278 G22
4278 G21
4278 G20
UVLO (V)
1100
–50
125
0
RISE TIME
0
1
2
3 4 5 6 7
CAPACITANCE (nF)
8
9
10
4278 G26
4278fc
8
LTC4278
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum PG On-Time
vs Temperature
325
300
RtON(MIN) = 158k
330
250
tPGDLY (ns)
tON(MIN) (ns)
200
310
300
290
RENDLY = 90k
305
RPGDLY = 27.4k
320
285
tENDLY (ns)
340
Enable Delay Time
vs Temperature
PG Delay Time vs Temperature
150
RPGDLY = 16.9k
100
265
245
280
260
–50
225
50
270
–25
0
50
75
25
TEMPERATURE (°C)
100
125
4278 G28
0
–50
–25
25
0
75
50
TEMPERATURE (°C)
100
125
4278 G29
205
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
125
4278 G30
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9
LTC4278
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4278
operation and corrupt the signature resistance. If unused,
tie SHDN to VPORTN.
T2P (Pin 2): Type 2 PSE Indicator, Open-Drain. Low impedance indicates the presence of a Type 2 PSE.
RCLASS (Pin 3): Class Select Input. Connect a resistor
between RCLASS and VPORTN to set the classification load
current (see Table 2).
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
VPORTN (Pins 5, 6): Input Voltage, Negative Rail. Pin 5
and Pin 6 must be electrically tied together at the package.
SG (Pin 9): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchronous rectifier. Large dynamic currents may flow during
voltage transitions. See the Applications Information
section for details.
VCC (Pin 10): Supply Voltage Pin. Bypass this pin to
GND with a low ESR ceramic capacitor. See the Applications Information section for details.
tON (Pin 11): Pin for external programming resistor to
set the minimum time that the primary switch is on for
each cycle. Minimum turn-on facilitates the isolated feedback method. See the Applications Information section
for details.
ENDLY (Pin 12): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifier for a fixed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for flyback voltage sensing.
See the Applications Information section for details.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to discharge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See the Applications Information section for details.
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (CSFST) to GND, controls the ramp-up of peak
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
the VCMP voltage and thus limits peak current until softstart is complete. The ramp time is approximately 70ms
per µF of capacitance. Leave SFST open if not using the
soft-start function.
OSC (Pin 15): Oscillator. This pin, in conjunction with an
external capacitor (COSC) to GND, defines the controller
oscillator frequency. The frequency is approximately
100kHz • 100/COSC (pF).
FB (Pin 16): Feedback Amplifier Input. Feedback is usually
sensed via a third winding and enabled during the flyback
period. This pin also sinks additional current to compensate
for load current variation as set by the RCMP pin. Keep the
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
VCMP (Pin 17): Frequency Compensation Control. VCMP
is used for frequency compensation of the switcher control loop. It is the output of the feedback amplifier and
the input to the current comparator. Switcher frequency
compensation components are placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifier output is enabled
during the synchronous switch on time.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
from VPORTP to this pin sets an undervoltage lockout based
upon VPORTP level (not VCC). When the UVLO pin is below
its threshold, the gate drives are disabled, but the part
draws its normal quiescent current from VCC.
The bias current on this pin has hysteresis such that the
bias current is sourced when UVLO threshold is exceeded.
This introduces a hysteresis at the pin equivalent to the bias
current change times the impedance of the upper divider
resistor. The user can control the amount of hysteresis
by adjusting the impedance of the divider. Tie the UVLO
pin to VCC if not using this function. See the Applications
4278fc
10
LTC4278
PIN FUNCTIONS
Information section for details. This pin is used for the
UVLO function of the switching regulator. The PD interface
section has an internal UVLO.
SENSE –, SENSE+ (Pins 19, 20): Current Sense Inputs.
These pins are used to measure primary-side switch current through an external sense resistor. Peak primary-side
current is used in the converter control loop. Make Kelvin
connections to the sense resistor RSENSE to reduce noise
problems. SENSE – connects to the GND side. At maximum
current (VCMP at its maximum voltage) SENSE pins have
100mV threshold. The signal is blanked (ignored) during
the minimum turn-on time.
CCMP (Pin 21): Load Compensation Capacitive Control.
Connect a capacitor from CCMP to GND in order to reduce
the effects of parasitic resistances in the feedback sensing
path. A 0.1µF ceramic capacitor suffices for most applications. Short this pin to GND when load compensation is
not needed.
RCMP (Pin 22): Load Compensation Resistive Control.
Connect a resistor from RCMP to GND in order to compensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See the Applications
Information section for details.
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (RPGDLY) to set delay from
synchronous gate turn-off to primary gate turn-on. See
the Applications Information section for details.
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary-side MOSFET switch. Large dynamic currents flow during voltage transitions. See the Applications
Information section for details.
VNEG (Pins 26, 27): System Negative Rail. Connects VNEG
to VPORTN through an internal power MOSFET. Pin 26 and
Pin 27 must be electrically tied together at the package.
PWRGD (Pin 29): Power Good Output, Open-Collector.
High impedance signals power-up completion. PWRGD
is referenced to VNEG and features a 14V clamp.
PWRGD (Pin 30): Complementary Power Good Output,
Open-Drain. Low impedance signals power-up completion.
PWRGD is referenced to VPORTN.
VPORTP (Pin 32): Positive Power Input. Tie to the input
port power through the input diode bridge.
Exposed Pad (Pin 33): Ground. This is the negative rail
connection for both signal ground and gate driver grounds
of the flyback controller. This pin should be connected to
VNEG.
4278fc
11
LTC4278
BLOCK DIAGRAM
CLASSIFICATION
CURRENT LOAD
1
2
3
SHDN
VPORTP
+
1.237V
16k
T2P
32
25k
–
RCLASS
NC
PWRGD
31
30
CONTROL
CIRCUITS
PWRGD
4 NC
5
6
VPORTN
29
14V
VNEG
VPORTN
VNEG
BOLD LINE INDICATES
HIGH CURRENT PATH
7 NC
27
26
8 NC
VCC
CLAMPS
0.7
–
1.237V
REFERENCE
(VFB)
INTERNAL
REGULATOR
+
VCMP
+
S
Q
R
Q
UVLO
+
TSD
SFST
1V
14
OVERCURRENT
FAULT
–
CURRENT
COMPARATOR
IUVLO
17
COLLAPSE DETECT
–
–
UVLO
16
ERROR AMP
+
–
18
–
3V
DISABLE
0.8V
FB
1.3
–
+
+
10
SENSE–
19
CURRENT
SENSE AMP
–
+
+
CURRENT TRIP
SENSE+
SLOPE COMPENSATION
15
13
11
23
12
OSC
OSCILLATOR
RCMPF
50k
ENABLE
SET
+
SYNC
CCMP
ENDLY
21
–
LOAD
COMPENSATION
tON
PGDLY
20
LOGIC
BLOCK
RCMP
TO FB
PGATE
GATE DRIVE
PG
22
24
SGATE
+
25 NC
28 NC
–
3V
GATE DRIVE
SG
GND
(EXPOSED PAD)
9
33
4278 BD
4278fc
12
LTC4278
APPLICATIONS INFORMATION
OVERVIEW
50
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
powered device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
VPORTP (V)
40
30
ON
10
CLASSIFICATION
DETECTION V2
DETECTION V1
VPORTP – VNEG (V)
50
The IEE802.3at standard establishes a higher power allocation for Power over Ethernet while maintaining backwards
compatibility with the existing IEEE 802.3af systems.
Power sourcing equipment (PSE) and powered devices are
distinguished as Type 1 complying with the IEEE 802.3af/
IEEE 802.3at power levels, or Type 2 complying with the
IEEE 802.3at power levels. The maximum available power
of a Type 2 PD is 25.5W.
TIME
dV = INRUSH
dt
C1
40
30
OFF
ON
20
OFF
τ = RLOAD C1
10
TIME
VPORTP – PWRGD (V)
TIME
The IEEE 802.3at standard also establishes a new method
of acquiring power classification from a PD and communicating the presence of a Type 2 PSE. A Type 2 PSE has the
option of acquiring PD power classification by performing
2-event classification (layer 1) or by communicating with
the PD over the data line (layer 2). In turn, a Type 2 PD
must be able to recognize both layers of communications
and identify a Type 2 PSE.
–10
POWER
BAD
–20
POWER
GOOD
PWRGD
TRACKS
VPORTP
–30
–40
PWRGD – VNEG (V)
–50
POWER
BAD
PWRGD
TRACKS
VPORTP
PWRGD TRACKS
VPORTN
20
POWER
BAD
10
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
The LTC4278 is specifically designed to support the front
end of a PD that must operate under the IEEE 802.3at
standard. In particular, the LTC4278 provides the T2P
indicator bit which recognizes 2-event classification. This
indicator bit may be used to alert the LTC4278 output load
that a Type 2 PSE is present. With an internal signature
resistor, classification circuitry, inrush control, and thermal shutdown, the LTC4278 is a complete PD Interface
solution capable of supporting in the next generation PD
applications.
LOAD, ILOAD
PD CURRENT
INRUSH
CLASSIFICATION
DETECTION I2
TIME
DETECTION I1
I1 =
V1 – 2 DIODE DROPS
V2 – 2 DIODE DROPS
I2 =
25kΩ
25kΩ
ICLASS DEPENDENT ON RCLASS SELECTION
INRUSH = 100mA
V
ILOAD = PORTP
RLOAD
MODES OF OPERATION
The LTC4278 has several modes of operation depending
on the input voltage applied between the VPORTP and
VPORTN pins. Figure 1 presents an illustration of voltage
and current waveforms the LTC4278 may encounter with
the various modes of operation summarized in Table 1.
OFF
20
LTC4278
IIN
PSE
RCLASS VPORTP
PWRGD
RCLASS
RLOAD
C1
PWRGD
VPORTN
VNEG
4278 F01
Figure 1. VNEG, PWRGD, PWRGD and PD
Current as a Function of Input Voltage
4278fc
13
LTC4278
APPLICATIONS INFORMATION
The input diode bridge introduces a voltage drop that
affects the range for each mode of operation. The
LTC4278 compensates for these voltage drops so that a
PD built with the LTC4278 meets the IEEE 802.3af/IEEE
802.3at-established voltage ranges. Note the Electrical
Characteristics are referenced with respect to the LTC4278
package pins.
Table 1. LTC4278 Modes of Operation as a Function
of Input Voltage
VPORTP–VPORTN (V)
LTC4278 MODES OF OPERATION
0V to 1.4V
Inactive (Reset After 1st Classification Event)
1.5V to 9.8V
(5.4V to 9.8V)
25k Signature Resistor Detection Before 1st
Classification Event (Mark, 11k Signature
Corrupt After 1st Classification Event)
12.5V to ON/OFF*
Classification Load Current Active
ON/OFF* to 60V
Inrush and Power Applied To PD Load
>71V
Overvoltage Lockout,
Classification and Hot Swap Are Disabled
DETECTION
During detection, the PSE looks for a 25k signature resistor which identifies the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltages V1 and V2 and the corresponding PD current.
The PSE calculates the signature resistance using the ΔV/
ΔI measurement technique.
*ON/OFF includes hysteresis. Rising input threshold, 37.2V Max.
Falling input threshold, 30V Min.
These modes satisfy the requirements defined in the
IEEE 802.3af/IEEE 802.3at specification.
INPUT DIODE BRIDGE
In the IEEE 802.3af/IEEE 802.3at standard, the modes of
operation reference the input voltage at the PD’s RJ45
connector. Since the PD must handle power received in
either polarity from either the data or the spare pair, input
diode bridges BR1 and BR2 are connected between the
RJ45 connector and the LTC4278 (Figure 2).
RJ45
1
2
3
TX+
–
POWERED 6 RX
DEVICE
(PD)
SPARE+
INPUT
4
5
BR1
TO PHY
VPORTP
BR2
0.1µF
100V D3
LTC4278
VPORTN
7
8
T1
TX–
RX+
The LTC4278 presents its precision, temperature-compensated 25k resistor between the VPORTP and VPORTN pins,
alerting the PSE that a PD is present and requests power
to be applied. The LTC4278 signature resistor also compensates for the additional series resistance introduced by
the input diode bridge. Thus a PD built with the LTC4278
conforms to the IEEE 802.3af/IEEE 802.3at specifications.
4278 F02
SPARE–
Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs
4278fc
14
LTC4278
APPLICATIONS INFORMATION
SIGNATURE CORRUPT OPTION
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE. The LTC4278 signature resistance can be corrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/IEEE 802.3at specification, and alerts the PSE not to apply power. Invoking
the SHDN pin also ceases operation for classification and
disconnects the LTC4278 load from the PD input. If this
feature is not used, connect SHDN to VPORTN.
Table 2. Summary of Power Classifications and LTC4278
RCLASS Resistor Selection
CLASS
USAGE
MAXIMUM
POWER LEVELS
AT INPUT OF PD
(W)
NOMINAL
CLASSIFICATION
LOAD CURRENT
(mA)
LTC4278
RCLASS
RESISTOR
(Ω, 1%)
0
Type 1
0.44 to 12.95
< 0.4
Open
1
Type 1
0.44 to 3.84
10.5
124
2
Type 1
3.84 to 6.49
18.5
69.8
3
Type 1
6.49 to 12.95
28
45.3
4
Type 2
12.95 to 25.5
40
30.9
2-EVENT CLASSIFICATION AND THE T2P PIN
LTC4278
TO
PSE
VPORTP
16k
25k SIGNATURE
RESISTOR
SHDN
VPORTN
4278 F03
SIGNATURE DISABLE
Figure 3. 25k Signature Resistor with Disable
CLASSIFICATION
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power classification. Class 0 is included in the IEEE specification for
PDs that do not support classification. Class 1-3 partitions
PDs into three distinct power ranges. Class 4 includes the
new power range under IEEE802.3at (see Table 2).
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 1).
The LTC4278 asserts a load current representing the PD
power classification. The classification load current is
programmed with a resistor RCLASS that is chosen from
Table 2.
A Type 2 PSE may declare the availability of high power by
performing a 2-event classification (layer 1) or by communicating over the high speed data line (layer 2). A Type
2 PD must recognize both layers of communication. Since
layer 2 communication takes place directly between the
PSE and the LTC4278 load, the LTC4278 concerns itself
only with recognizing 2-event classification.
In 2-event classification, a Type 2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4278 presents a class 4 load current. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
The PSE repeats this sequence, signaling the 2nd Classification and 2nd mark event occurrence. This alerts the
LTC4278 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4278 charges
up the reservoir capacitor C1 with a controlled inrush current. When C1 is fully charged, and the LTC4278 declares
power good, the T2P pin presents an active low signal, or
low impedance output with respect to VPORTN . The T2P
output becomes inactive when the LTC4278 input voltage
falls below undervoltage lockout threshold.
4278fc
15
LTC4278
APPLICATIONS INFORMATION
SIGNATURE CORRUPT DURING MARK
50
VPORTP (V)
40
30
1st CLASS
2nd CLASS
ON
OFF
20
10
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
PD CURRENT
INRUSH
LOAD, ILOAD
1st CLASS
2nd CLASS
40mA
PD STABILITY DURING CLASSIFICATION
TIME
DETECTION V1
DETECTION V2
VPORTP – VNEG (V)
50
40
1st MARK 2nd MARK
dV = INRUSH
dt
C1
30
OFF
ON
20
OFF
τ = RLOAD C1
10
VPORTP – T2P (V)
TIME
–20
–30
–40
TRACKS
VPORTN
–50
INRUSH = 100mA
RCLASS = 30.9Ω
V
ILOAD = PORTN
RLOAD
LTC4278
IIN
PSE
RLOAD
RCLASS VPORTP
RCLASS
T2P
VPORTN
C1
VNEG
Figure 4. VNEG, T2P and PD Current
as a Result of 2-Event Classification
Classification presents a challenging stability problem due
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
The LTC4278 prevents this oscillation by introducing a
voltage hysteresis window between the detection and classification ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
TIME
–10
As a member of the IEEE 802.3at working group, Linear
Technology noted that it is possible for a Type 2 PD to
receive a false indication of a 2-event classification if a
PSE port is pre-charged to a voltage above the detection
voltage range before the first detection cycle. The IEEE
working group modified the standard to prevent this possibility by requiring a Type 2 PD to corrupt the signature
resistance during the mark event, alerting the PSE not to
apply power. The LTC4278 conforms to this standard by
corrupting the signature resistance. This also discharges
the port before the PSE begins the next detection cycle.
4278 F04
The LTC4278 also maintains a positive I-V slope throughout
the classification range up to the on-voltage. In the event
a PSE overshoots beyond the classification voltage range,
the available load current aids in returning the PD back
into the classification voltage range. (The PD input may
otherwise be “trapped” by a reverse-biased diode bridge
and the voltage held by the 0.1μF capacitor).
INRUSH CURRENT
Once the PSE detects and optionally classifies the PD,
the PSE then applies powers on the PD. When the
LTC4278 input voltage rises above the on-voltage threshold,
LTC4278 connects VNEG to VPORTN through the internal
power MOSFET.
4278fc
16
LTC4278
APPLICATIONS INFORMATION
To control the power-on surge currents in the system, the
LTC4278 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
is disconnected, and classification mode resumes. C1
discharges through the LTC4278 circuitry.
The LTC4278 keeps the PD inrush current below the PSE
current limit to provide a well controlled power-up characteristic that is independent of the PSE behavior. This ensures
a PD using the LTC4278 interoperability with any PSE.
COMPLEMENTARY POWER GOOD
TURN-ON/ TURN-OFF THRESHOLD
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD
operation when the input voltage is too low. In addition,
this specification allows PD designs to incorporate an ON/
OFF hysteresis window to prevent start-up oscillations.
The LTC4278 features an ON/OFF hysteresis window (see
Figure 5) that conforms with the IEEE 802.3af/at specification and accommodates the voltage drop in the cable
and input diode bridge at the onset of the inrush current.
Once C1 is fully charged, the LTC4278 turns on is internal
MOSFET and passes power to the PD load. The LTC4278
continues to power the PD load as long as the input voltage
does not fall below the OFF threshold. When the LTC4278
input voltage falls below the OFF threshold, the PD load
When LTC4278 fully charges the load capacitor (C1), power
good is declared and the LTC4278 load can safely begin
operation. The LTC4278 provides complementary power
good signals that remain active during normal operation
and are de-asserted when the input voltage falls below
the OFF threshold, when the input voltage exceeds the
overvoltage lockout (OVLO) threshold, or in the event of
a thermal shutdown (see Figure 6).
The PWRGD pin features an open collector output referenced to VNEG which can interface directly with the UVLO
pin. When power good is declared and active, the PWRGD
pin is high impedance with respect to VNEG. An internal 14V
clamp protects the UVLO pin from an excessive voltage.
The active low PWRGD pin connects to an internal, opendrain MOSFET referenced to VPORTN and may be used as
an indicator bit when power good is declared and active.
The PWRGD pin is low impedance with respect to VPORTN.
LTC4278
30 PWRGD
OVLO
ON/OFF
TSD
CONTROL
CIRCUIT
29 PWRGD
LTC4278
TO
PSE
VPORTP
+
C1
5µF
MIN
PD
LOAD
ON/OFF AND
OVERVOLTAGE
LOCKOUT
CIRCUIT
VPORTN
VNEG
VPORTP – VPORTN
LTC4278
VOLTAGE
POWER MOSFET
0V TO ON*
OFF
>ON*
ON
OVLO
OFF
*INCLUDES ON/OFF HYSTERESIS
ON THRESHOLD ≅ 36.1V
OFF THRESHOLD ≅ 30.7V
OVLO THRESHOLD ≅ 71.0V
VPORTN 5
27 VNEG
VPORTN 6
26 VNEG
BOLD LINE INDICATES HIGH CURRENT PATH
4278 F05
CURRENT-LIMITED
TURN ON
Figure 5. LTC4278 ON/OFF and Overvoltage Lockout
INRUSH COMPLETE
ON < VPORTP < OVLO
AND NOT IN THERMAL SHUTDOWN
POWER
NOT
GOOD
POWER
GOOD
VPORTP < OFF
VPORTP > OVLO
OR THERMAL SHUTDOWN
4278 F06
Figure 6. LTC4278 Power Good Functional and State Diagram
4278fc
17
LTC4278
APPLICATIONS INFORMATION
PWRGD PIN WHEN SHDN IS INVOKED
In PD applications where an auxiliary power supply invokes
the SHDN feature, the PWRGD pin becomes high impedance. This prevents the PWRGD pin that is connected to
the UVLO pin from interfering with the DC/DC converter
operations when powered by an auxiliary power supply.
OVERVOLTAGE LOCKOUT
The LTC4278 includes an overvoltage lockout (OVLO)
feature (Figure 6) which protects the LTC4278 and its load
from an overvoltage event. If the input voltage exceeds the
OVLO threshold, the LTC4278 discontinues PD operation.
Normal operations resume when the input voltage falls
below the OVLO threshold and when C1 is charged up.
isolation transformer must also include a center tap on
the RJ45 connector side (see Figure 7).
The increased current levels in a Type 2 PD over a Type
1 increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
provide correct impedance matching and to avoid radiated
and conducted emissions. Transformer vendors such as
Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
Table 4. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
Halo Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
PCA Electronics
16799 Schoenborn Street
North Hills, CA 91343
Tel: 818-892-0761
www.pca.com
Pulse Engineering
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
Tyco Electronics
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
THERMAL PROTECTION
The IEEE 802.3af/at specification requires a PD to withstand
any applied voltage from 0V to 57V indefinitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
During classification, excessive heating may occur if the
PSE exceeds the 75ms probing time limit. At turn-on, when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
The LTC4278 includes a thermal protection feature which
protects the LTC4278 from excessive heating. If the
LTC4278 junction temperature exceeds the over-temperature threshold, the LTC4278 discontinues PD operations
and power good becomes inactive. Normal operation
resumes when the junction temperature falls below the
overtemperature threshold and when C1 is charged up.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Input Diode Bridge
Figure 2 shows how two diode bridges are typically connected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4278 supports the use of either silicon or
Schottky input diode bridges. However, there are tradeoffs
in the choice of diode bridges.
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
4278fc
18
LTC4278
APPLICATIONS INFORMATION
An input diode bridge must be rated above the maximum
current the PD application will encounter at the temperature the PD will operate. Diode bridge vendors typically
call out the operating current at room temperature, but
derate the maximum current with increasing temperature.
Consult the diode bridge vendors for the operating current
derating curve.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profile. Figure 7 shows how to reconnect the two diode
bridges. Consult the diode bridge vendors for the derating
curve when only one of four diodes is in operation.
A silicon diode bridge can consume over 4% of the available
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
Input Capacitor
A Schottky bridge may not be suitable for some high
temperature PD application. The leakage current has a
voltage dependency that can reduce the perceived signature
resistance. In addition, the IEEE 802.3af/at specification
mandates the leakage back-feeding through the unused
bridge cannot generate more than 2.8V across a 100k
resistor when a PD is powered with 57V.
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drastically derated. The larger package may not be acceptable in some space-limited environments.
RJ45
1
2
3
6
4
TX+
8
Transient Voltage Suppressor
The LTC4278 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4278, install a transient voltage suppressor (D3) between the input diode bridge and the LTC4278 as shown
in Figure 7.
14 T1 1
12
3
TX–
13
2
RX+
10
5
11
4
9
6
RX–
BR1
HD01
TO PHY
COILCRAFT
ETHI - 230LD
SPARE+
5
7
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement.
SPARE –
VPORTP
BR2
HD01
C14
0.1µF
100V
D3
SMAJ58A
TVS
LTC4278
C1
VPORTN VNEG
4278 F07
B1100
Figure 7. PD Front-End with Isolation Transformer, Diode Bridges,
Capacitors, and a Transient Voltage Suppressor (TVS)
4278fc
19
LTC4278
APPLICATIONS INFORMATION
Classification Resistor (RCLASS)
The RCLASS resistor sets the classification load current,
corresponding to the PD power classification. Select the
value of RCLASS from Table 2 and connect the resistor
between the RCLASS and VPORTN pins as shown in Figure
4, or float the RCLASS pin if the classification load current is not required. The resistor tolerance must be 1%
or better to avoid degrading the overall accuracy of the
classification circuit.
VPORTP
TO
PSE
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store significant energy when fully
charged. The PD design must ensure that this energy is
not inadvertently dissipated in the LTC4278. For example,
if the VPORTP pin shorts to VPORTN while the capacitor
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4278.
T2P Interface
When a 2-event classification sequence successfully
completes, the LTC4278 recognizes this sequence, and
provides an indicator bit, declaring the presence of a
Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4278 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P pin
and the opto-isolator. The T2P pin is active low and connects to an opto-isolator to communicate across the DC/
RP
LTC4278
–54V
TO PD LOAD
VPORTN
T2P
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
V+
Load Capacitor
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5μF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
V+
VPORTP
RP
LTC4278
TO
PSE
T2P
–54V
VPORTN
VNEG
TO PD LOAD
4278 F08
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
Figure 8. T2P Interface Examples
DC converter isolation barrier. The pull-up resistor RP is
sized according to the requirements of the opto-isolator
operating current, the pull-down capability of the T2P pin,
and the choice of V+. V+ for example can come from the
PoE supply rail (which the LTC4278 VPORTP is tied to), or
from the voltage source that supplies power to the DC/
DC converter. Option 1 has the advantage of not drawing
power unless T2P is declared active.
Shutdown Interface
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to VPORTN. If unused, connect
SHDN directly to VPORTN.
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
Auxiliary power can be injected into an LTC4278-based
PD at the input of the LTC4278 VPORTN , at VNEG, or even
the power supply output. In addition, some PD applications
may desire auxiliary supply dominance or may be configured
4278fc
20
LTC4278
APPLICATIONS INFORMATION
for PoE dominance. Furthermore, PD applications may
also opt for a seamless transition — that is, without power
disruption — between PoE and auxiliary power.
The most common auxiliary power option injects power at
VNEG. Figure 9 presents an example of this application. In
this example, the auxiliary port injects 48V onto the line via
diode D1. The components surrounding the SHDN pin are
selected so that the LTC4278 does not disconnect power
to the output until the auxiliary supply exceeds 36V.
This configuration is an auxiliary-dominant configuration.
That is, the auxiliary power source supplies the power even
if PoE power is already present. This configuration also
provides a seamless transition from PoE to auxiliary power
when auxiliary power is applied, however, the removal of
auxiliary power to PoE power is not seamless.
Contact Linear Technology applications support for detail
information on implementing a custom auxiliary power
supply.
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
Under the IEEE 802.3at standard, a PD must operate under
12.95W in accordance with IEEE 802.3at standard until it
recognizes a Type 2 PSE. Initializing PD operation in 12.95W
mode eliminates interoperability issue in case a Type 2
PD connects to a Type 1 PSE. Once the PD recognizes a
RJ45
1
2
3
6
TX+
Type 2 PSE, the IEEE 802.3at standard requires the PD to
wait 80ms in 12.95W operation before 25.5W operation
can commence.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25k in parallel with 0.05μF. If one of these conditions is not met, the PSE may disconnect power to the PD.
SWITCHING REGULATOR OVERVIEW
The LTC4278 includes a current mode converter designed
specifically for use in an isolated flyback topology employing
synchronous rectification. The LTC4278 operation is similar
to traditional current mode switchers. The major difference
is that output voltage feedback is derived via sensing the
output voltage through the transformer. This precludes
the need of an opto-isolator in isolated designs, thus
greatly improving dynamic response and reliability. The
LTC4278 has a unique feedback amplifier that samples a
transformer winding voltage during the flyback period and
uses that voltage to control output voltage. The internal
blocks are similar to many current mode controllers.
The differences lie in the feedback amplifier and load
T1
+
TX–
RX+
TO PHY
TVS
0.1µF
100V
BR1
–
RX–
100k
4
SPARE+
+
5
7
8
C1
BR2
SPARE–
VPORTP
LTC4278
10k
SHDN
GND
10k
–
ISOLATED
WALL
TRANSFORMER
36V
VPORTN VNEG
+
–
D1
4278 F09
Figure 9. Auxiliary Power Dominant PD Interface Example
4278fc
21
LTC4278
APPLICATIONS INFORMATION
compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
flyback control. For more information on the basics of
current mode switcher/controllers and isolated flyback
converters see Application Note 19.
Feedback Amplifier—Pseudo DC Theory
For the following discussion, refer to the simplified
Switching Regulator Feedback Amplifier diagram (Figure
10A). When the primary-side MOSFET switch MP turns off,
its drain voltage rises above the VPORTP rail. Flyback occurs
when the primary MOSFET is off and the synchronous
secondary MOSFET is on. During flyback the voltage on
nondriven transformer pins is determined by the secondary
voltage. The amplitude of this flyback pulse, as seen on
the third winding, is given as:
VFLBK =
(
VOUT + ISEC • ESR + R DS(ON)
N SF
)
RDS(ON) = on-resistance of the synchronous MOSFET MS
ISEC = transformer secondary current
ESR = impedance of secondary circuit capacitor, winding
and traces
NSF = transformer effective secondary-to-flyback winding
turns ratio (i.e., NS/NFLBK)
The flyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifier compares the voltage to the internal bandgap
reference. The feedback amp is actually a transconductance
amplifier whose output is connected to VCMP only during
a period in the flyback time. An external capacitor on
the VCMP pin integrates the net feedback amp current to
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference VFB because of the high gain in
the overall loop. The relationship between VFLBK and VFB
is expressed as:
VFLBK =
R1+ R2
• VFB
R2
Combining this with the previous VFLBK expression yields
an expression for VOUT in terms of the internal reference,
programming resistors and secondary resistances:
R1+R2
VOUT =
• VFB • NSF −ISEC • ESR+RDS(ON)
R2
(
)
The effect of nonzero secondary output impedance is
discussed in further detail (see Load Compensation
Theory). The practical aspects of applying this equation for
VOUT are found in subsequent sections of the Applications
Information.
Feedback Amplifier Dynamic Theory
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision is made to turn on the
flyback amplifier only when the flyback pulse is present,
using the enable signal as shown in the timing diagram
(Figure 10b).
Minimum Output Switch On Time (tON(MIN))
The LTC4278 affects output voltage regulation via flyback
pulse action. If the output switch is not turned on, there
is no flyback pulse and output voltage information is
not available. This causes irregular loop response and
start-up/latchup problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
feedback is blanked each cycle for tON(MIN). If the output load
is less than that developed under these conditions, forced
continuous operation normally occurs. See subsequent
discussions in the Applications Information section for
further details.
Enable Delay Time (ENDLY)
The flyback pulse appears when the primary-side switch
shuts off. However, it takes a finite time until the transformer
primary-side voltage waveform represents the output
voltage. This is partly due to rise time on the primaryside MOSFET drain node, but, more importantly, is due
4278fc
22
LTC4278
APPLICATIONS INFORMATION
T1
VFLBK
FLYBACK
LTC4278 FEEDBACK AMP
R1
FB
–
1V
R2
VFB
1.237V
+
16
•
VCMP
+
17
CVCMP
VIN
PRIMARY
•
SECONDARY
•
+
COUT
ISOLATED
OUTPUT
MP
–
COLLAPSE
DETECT
MS
R
ENABLE
S
Q
4278 F10a
Figure 10a. LTC4278 Switching Regulator Feedback Amplifier
PRIMARY-SIDE
MOSFET DRAIN
VOLTAGE
VFLBK
0.8 • VFLBK
VIN
PG VOLTAGE
SG VOLTAGE
tON(MIN)
ENABLE
DELAY
MIN ENABLE
PG DELAY
4278 F10b
FEEDBACK
AMPLIFIER
ENABLED
Figure 10b. LTC4278 Switching Regulator Timing Diagram
4278fc
23
LTC4278
APPLICATIONS INFORMATION
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See the subsequent sections
for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
voltage (FB) to a fixed reference, nominally 80% of VFB.
When the flyback waveform drops below this level, the
feedback amplifier is disabled.
Minimum Enable Time
The feedback amplifier, once enabled, stays on for a fixed
minimum time period, termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low, e.g., during start-up. The minimum
enable time period ensures that the VCMP node is able to
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback amplifier is enabled during only a portion of
the cycle time. This can vary from the fixed minimum enable
time described to a maximum of roughly the off switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and VCMP node slew rate.
Load Compensation Theory
The LTC4278 uses the flyback pulse to obtain information
about the isolated output voltage. An error source is
caused by transformer secondary current flow through
the synchronous MOSFET RDS(ON) and real life nonzero
impedances of the transformer secondary and output
capacitor. This was represented previously by the
expression, ISEC • (ESR + RDS(ON)). However, it is generally
more useful to convert this expression to effective output
impedance. Because the secondary current only flows
during the off portion of the duty cycle (DC), the effective
output impedance equals the lumped secondary impedance
divided by off time DC.
Since the off-time duty cycle is equal to 1 – DC, then:
RS(OUT) =
ESR + RDS(ON)
1– DC
where:
RS(OUT) = effective supply output impedance
DC = duty cycle
RDS(ON) and ESR are as defined previously
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases, the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 11 shows the block diagram of the load
compensation function. Switch current is converted to a
voltage by the external sense resistor, averaged and lowpass
filtered by the internal 50k resistor RCMPF and the external
capacitor on CCMP. This voltage is impressed across the
external RCMP resistor by op amp A1 and transistor Q3
producing a current at the collector of Q3 that is subtracted
from the FB node. This effectively increases the voltage
required at the top of the R1/R2 feedback divider to achieve
equilibrium.
The average primary-side switch current increases to
maintain output voltage regulation as output loading
increases. The increase in average current increases RCMP
resistor current which affects a corresponding increase
in sensed output voltage, compensating for the IR drops.
4278fc
24
LTC4278
APPLICATIONS INFORMATION
Assuming relatively fixed power supply efficiency, Eff,
power balance gives:
Nominal output impedance cancellation is obtained by
equating this expression with RS(OUT):
POUT = Eff • PIN
K1•
VOUT • IOUT = Eff • VIN • IIN
Average primary-side current is expressed in terms of
output current as follows:
Solving for RCMP gives:
IIN = K1•IOUT
RCMP = K1•
where:
K1=
VOUT
VIN • Eff
Transformer Design
R
ΔVOUT =K1• SENSE • R1• NSF • ΔIOUT
RCMP
Transformer design/specification is the most critical part
of a successful application of the LTC4278. The following
sections provide basic information about designing the
transformer and potential tradeoffs. If you need help, the
LTC Applications group is available to assist in the choice
and/or design of the transformer.
thus:
R
ΔVOUT
=K1• SENSE • R1• NSF
ΔIOUT
RCMP
where:
K1 = dimensionless variable related to VIN, VOUT and
efficiency, as previously explained
RSENSE = external sense resistor
VFLBK
R2
Turns Ratios
The design of the transformer starts with determining
duty cycle (DC). DC impacts the current and voltage stress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
•
FB
Q1 Q2
16
VFB
VIN
LOAD
COMP I
•
•
MP
+
Q3
A1
–
22 RCMP
RSENSE • (1– DC)
• R1• NSF
ESR + RDS(ON)
The practical aspects of applying this equation to determine
an appropriate value for the RCMP resistor are discussed
subsequently in the Applications Information section.
So, the effective change in VOUT target is:
R1
ESR + RDS(ON)
RSENSE
• R1• NSF =
RCMP
1– DC
RCMPF
+
50k SENSE
20
21 CCMP
VOUT 1– DC
•
VIN
DC
Avoid extreme duty cycles, as they generally increase current stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
RSENSE
4278 F11
Figure 11. Load Compensation Diagram
N IDEAL =
N IDEAL =
5 1– 0.5 1
•
=
48 0.5
9.6
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio.
4278fc
25
LTC4278
APPLICATIONS INFORMATION
Note the use of the external feedback resistive divider
ratio to set output voltage provides the user additional
freedom in selecting a suitable transformer turns ratio.
Turns ratios that are the simple ratios of small integers;
e.g., 1:1, 2:1, 3:2 help facilitate transformer construction
and improve performance.
When building a supply with multiple outputs derived
through a multiple winding transformer, lower duty cycle
can improve cross regulation by keeping the synchronous
rectifier on longer, and thus, keep secondary windings
coupled longer. For a multiple output transformer, the turns
ratio between output windings is critical and affects the
accuracy of the voltages. The ratio between two output
voltages is set with the formula VOUT2 = VOUT1 • N21 where
N21 is the turns ratio between the two windings. Also
keep the secondary MOSFET RDS(ON) small to improve
cross regulation.
The feedback winding usually provides both the feedback
voltage and power for the LTC4278. Set the turns ratio
between the output and feedback winding to provide a
rectified voltage that under worst-case conditions is greater
than the the preregulator maximum supply voltage. For
example if the preregulator maximum output were 7V:
NSF >
VOUT
7 + VF
where:
VF = Diode Forward Voltage
5
1
=
For our example: NSF >
7 + 0.7 1.56
1
We will choose
3
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary-side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
flyback voltage may break down the MOSFET switch if it
has too low a BVDSS rating.
One solution to reducing this spike is to use a clamp circuit
to suppress the voltage excursion. However, suppressing
the voltage extends the flyback pulse width. If the flyback
pulse extends beyond the enable delay time, output
voltage regulation is affected. The feedback system has a
deliberately limited input range, roughly ±50mV referred
to the FB node. This rejects higher voltage leakage spikes
because once a leakage spike is several volts in amplitude,
a further increase in amplitude has little effect on the
feedback system. Therefore, it is advisable to arrange the
clamp circuit to clamp at as high a voltage as possible,
observing MOSFET breakdown, such that leakage spike
duration is as short as possible. Application Note 19
provides a good reference on clamp design.
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a clamp, but
exhibit little to no regulation error due to leakage spike
behavior. Inductances from several percent up to, perhaps,
ten percent, cause increasing regulation error.
Avoid double digit percentage leakage inductances. There
is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the
leakage spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal!
It then reverts to a potentially stable state whereby the
top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This typically reduces the output voltage
abruptly to a fraction, roughly one-third to two-thirds of
its correct value.
Once load current is reduced sufficiently, the system snaps
back to normal operation. When using transformers with
considerable leakage inductance, exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This is usually evident
by simultaneously viewing the primary-side MOSFET drain
voltage to observe firsthand the leakage spike behavior.
4278fc
26
LTC4278
APPLICATIONS INFORMATION
A final note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I =
V/R behavior—is the most apt to be bistable. Capacitive
loads that exhibit I = V2/R behavior are less susceptible.
Ripple current and percentage ripple is largest at minimum
duty cycle; in other words, at the highest input voltage.
LP is calculated from the following equation.
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the flyback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior, this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
where:
2
Bifilar Winding
A bifilar, or similar winding, is a good way to minimize
troublesome leakage inductances. Bifilar windings also
improve coupling coefficients, and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so is not always practical.
Primary Inductance
The transformer primary inductance, LP, is selected
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value. As a general
rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to
0.4). Higher values of ripple will increase conduction losses,
while lower values will require larger cores.
LP
2
• Eff
fOSC • XMAX • POUT
fOSC • XMAX • PIN
fOSC is the oscillator frequency
DCMIN is the DC at maximum input voltage
XMAX is ripple current ratio at maximum input voltage
Using common high power PoE values, a 48V (41V < VIN
< 57V) to 5V/5.3A converter with 90% efficiency, POUT=
26.5W and PIN = 29.5W. Using X = 0.4 N = 1/8 and fOSC
= 200kHz:
Winding Resistance Effects
Primary or secondary winding resistance acts to reduce
overall efficiency (POUT/PIN). Secondary winding resistance
increases effective output impedance, degrading load
regulation. Load compensation can mitigate this to some
extent but a good design keeps parasitic resistances low.
( VIN(MAX) • DCMIN ) = ( VIN(MAX) • DCMIN )
=
DCMIN =
LP =
1+
1
=
N • VIN(MAX)
VOUT
(57V • 0.412)
1
= 41.2%
1 57
1+ •
8 5
2
200kHz • 0.4 • 26.5W
= 260µH
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at tradeoffs.
Transformer Core Selection
Once LP is known, the type of transformer is selected.
High efficiency converters use ferrite cores to minimize
core loss. Actual core loss is independent of core size for
a fixed inductance, but decreases as inductance increases.
Since increased inductance is accomplished through more
turns of wire, copper losses increase. Thus, transformer
design balances core and copper losses. Remember that
increased winding resistance will degrade cross regulation
and increase the amount of load compensation required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
4278fc
27
LTC4278
APPLICATIONS INFORMATION
when the peak design current is exceeded. This results
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
at minimum VIN:
PIN
VIN(MIN) • DCMAX
IPK =
X
• 1+ MIN
2
1+
XMIN
1
=
N • VIN(MIN)
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
1
= 49.4%
1 41
1+ •
8 5
VOUT
( VIN(MIN) • DCMAX )
=
2
fOSC • LP • PIN
=
(41• 49.4%)
Current Sense Resistor Considerations
2
200kHz • 260µH • 29.5W
= 0.267
Using the example numbers leads to:
IPK =
29.5W 0.267
• 1+
=1.65A
41• 0.494
2
One advantage that the flyback topology offers is that
additional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the flyback winding signal is a combination of
activity on all the secondary windings. Thus load regulation
is affected by each winding’s load. Take care to minimize
cross regulation effects.
Setting Feedback Resistive Divider
The expression for VOUT developed in the Operation section
is rearranged to yield the following expression for the
feedback resistors:
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane connected
with wide and short traces keeps stray resistance and
inductance low.
The dual sense pins allow for a full Kelvin connection. Make
sure that SENSE+ and SENSE– are isolated and connect
close to the sense resistor.
Multiple Outputs
V +I • ESR+R
DS(ON)
OUT SEC
R1=R2
−1
VFB • NSF
(
5+ 5.3 • 0.008
R1= 3.32k
−1 = 37.28k
1.237 • 1/ 3
choose 37.4k.
now :
DCMAX =
Continuing the example, if ESR + RDS(ON) = 8mW, R2 =
3.32k, then:
)
Peak current occurs at 100mV of sense voltage VSENSE. So
the nominal sense resistor is VSENSE/IPK. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010Ω Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
Size RSENSE using worst-case conditions, minimum LP ,
VSENSE and maximum VIN. Continuing the example, let us
assume that our worst-case conditions yield an IPK of 40%
above nominal, so IPK = 2.3A. If there is a 10% tolerance
on RSENSE and minimum VSENSE = 88mV, then RSENSE •
110% = 88mV/2.3A and nominal RSENSE = 35mΩ. Round
to the nearest available lower value, 33mΩ.
4278fc
28
LTC4278
APPLICATIONS INFORMATION
Selecting the Load Compensation Resistor
4. Compute:
The expression for RCMP was derived in the Operation
section as:
R
• (1– DC)
RCMP = K1• SENSE
• R1• NSF
ESR + RDS(ON)
6. Disconnect the ground short to CCMP and connect a 0.1µF
filter capacitor to ground. Measure the output impedance RS(OUT) = DVOUT/DIOUT with the new compensation
in place. RS(OUT) should have decreased significantly.
Fine tuning is accomplished experimentally by slightly
altering RCMP. A revised estimate for RCMP is:
V
5
K1= OUT =
= 0.116
VIN • Eff 48 • 90%
1
1
DC=
=
= 45.5%
N•VIN(NOM)
1 48
1+ •
1+
8 5
VOUT
If ESR+RDS(ON) = 8mΩ
= 3.25k
33mΩ • (1− 0.455)
8mΩ
• 37.4kΩ •
RSENSE
• R1• NSF
RS(OUT)
5. Verify this result by connecting a resistor of this value
from the RCMP pin to ground.
Continuing the example:
RCMP = 0.116 •
RCMP = K1•
1
3
This value for RCMP is a good starting point, but empirical
methods are required for producing the best results.
This is because several of the required input variables
are difficult to estimate precisely. For instance, the ESR
term above includes that of the transformer secondary,
but its effective ESR value depends on high frequency
behavior, not simply DC winding resistance. Similarly, K1
appears as a simple ratio of VIN to VOUT times efficiency,
but theoretically estimating efficiency is not a simple
calculation.
R
R′CMP =RCMP • 1+ S(OUT)CMP
RS(OUT)
where R′CMP is the new value for the load compensation
resistor. RS(OUT)CMP is the output impedance with RCMP
in place and RS(OUT) is the output impedance with no
load compensation (from step 2).
Setting Frequency
The switching frequency of the LTC4278 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 12 shows the nominal relationship between
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
300
1. Build a prototype of the desired supply including the
actual secondary components.
200
2. Temporarily ground the CCMP pin to disable the load
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line.
fOSC (kHz)
The suggested empirical method is as follows:
100
DVOUT/DIOUT = RS(OUT) .
3. Calculate a value for the K1 constant based on VIN, VOUT
and the measured efficiency.
50
30
100
COSC (pF)
200
4278 F12
Figure 12. fOSC vs OSC Capacitor Values
4278fc
29
LTC4278
APPLICATIONS INFORMATION
trace length and area to minimize stray capacitance and
potential noise pick-up.
You can synchronize the oscillator frequency to an external
frequency. This is done with a signal on the SYNC pin.
Set the LTC4278 frequency 10% slower than the desired
external frequency using the OSC pin capacitor, then use
a pulse on the SYNC pin of amplitude greater than 2V
and with the desired frequency. The rising edge of the
SYNC signal initiates an OSC capacitor discharge forcing
primary MOSFET off (PG voltage goes low). If the oscillator
frequency is much different from the sync frequency,
problems may occur with slope compensation and system
stability. Also, keep the sync pulse width greater than 500ns.
Selecting Timing Resistors
There are three internal “one-shot” times that are
programmed by external application resistors: minimum
on-time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated flyback control
technique, and their functions are previously outlined in
the Theory of Operation section. The following information
should help in selecting and/or optimizing these timing
values.
Minimum Output Switch On-Time (tON(MIN))
Minimum on-time is the programmable period during which
current limit is blanked (ignored) after the turn-on of the
primary-side switch. This improves regulator performance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
both the gate/source charging current and the discharge
of drain capacitance. The isolated flyback sensing requires
a pulse to sense the output. Minimum on-time ensures
that the output switch is always on a minimum time and
that there is always a signal to close the loop.
The LTC4278 does not employ cycle skipping at light loads.
Therefore, minimum on-time along with synchronous
rectification sets the switch over to forced continuous
mode operation.
The tON(MIN) resistor is set with the following equation
R tON(MIN) (kW) =
tON(MIN) (ns) −104
1.063
Keep RtON(MIN) greater than 70k. A good starting value
is 160k.
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifier. As discussed earlier, this
delay allows the feedback amplifier to ignore the leakage
inductance voltage spike on the primary side. The worstcase leakage spike pulse width is at maximum load conditions. So, set the enable delay time at these conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondaryside controller might cause discontinuous operation at
light loads. Under such conditions, the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the flyback waveform at light loads.
Even though the LTC4278 has a robust gate drive, the gate
transition time slows with very large MOSFETs. Increase
delay time as required when using such MOSFETs.
The enable delay resistor is set with the following equation:
RENDLY (kW) =
tENDLY (ns) − 30
2.616
Keep RENDLY greater than 40k. A good starting point is 56k.
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
4278fc
30
LTC4278
APPLICATIONS INFORMATION
between the primary-side switch and secondary-side synchronous switch(es) and the subsequent current spike in
the transformer. This spike will cause additional component
stress and a loss in regulator efficiency.
The primary gate delay resistor is set with the following
equation:
RPGDLY (kW) =
tPGDLY (ns) + 47
9.01
A good starting point is 15k.
Soft-Start Function
The LTC4278 contains an optional soft-start function that
is enabled by connecting an external capacitor between
the SFST pin and ground. Internal circuitry prevents the
control voltage at the VCMP pin from exceeding that on
the SFST pin. There is an initial pull-up circuit to quickly
bring the SFST voltage to approximately 0.8V. From there it
charges to approximately 2.8V with a 20µA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when the current sense voltage is greater
than 200mV or the IC’s thermal (overtemperature) shutdown is tripped. When SFST discharges, the VCMP node
voltage is also pulled low to below the minimum current
voltage. Once discharged and the fault removed, the
SFST charges up again. In this manner, switch currents
are reduced and the stresses in the converter are reduced
during fault conditions.
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin voltage and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 13, the voltage hysteresis at VIN is
equal to the change in bias current times RA. The design
procedure is to select the desired VIN referred voltage
hysteresis, VUVHYS. Then:
RA =
VUVHYS
IUVLO
where:
IUVLO = IUVLOL – IUVLOH is approximately 3.4µA
RB is then selected with the desired turn-on voltage:
RB =
RA
VIN(ON)
– 1
VUVLO
VIN
IUVLO
The time it takes to fully charge soft-start is:
C
• 1.4V
t ss = SFST
= 70kW • CSFST (µF )
20µA
VIN
IUVLO
VIN
RA
RB
UVLO
LTC4278
RA
RB
RA2
UVLO
LTC4278
Switcher’s UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on VIN. The gate drivers are disabled when
RA1
CUVLO
UVLO
RB
4278 F13
(13a) UV Turning On
(13b) UV Turning Off
(13c) UV Filtering
Figure 13. UVLO Pin Function and Recommended Filtering
4278fc
31
LTC4278
APPLICATIONS INFORMATION
If we wanted a VIN-referred trip point of 36V, with 1.8V
(5%) of hysteresis (on at 36V, off at 34.2V):
R A = 1.8V = 529k, use 523k
3.4µA
RB =
523k
= 18.5k, use 18.7 k
36V
– 1
1.23V
Even with good board layout, board noise may cause
problems with UVLO. You can filter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 13c shows an alternate method of filtering by splitting the RA resistor with the capacitor. The split should put
more of the resistance on the UVLO side.
to turn off QPR. If the two voltage ranges overlap, the only
disadvantage is that a small degradation in efficiency may
occur. It is also necessary to verify that the worst-case
maximum winding voltage is not high enough to damage
the B-E junction of QPR.
VIN
•
•
QPR
CVCC
VCC
LTC4278
GND
Converter Start-Up
The standard topology for the LTC4278 uses a third transformer winding on the primary side that provides both the
feedback information and local VCC power for the LTC4278
(Figure 14). This power bootstrapping improves converter
efficiency but is not inherently self-starting. Start-Up is
affected with an external preregulator circuit that conditions the input line voltage for the LTC4278 during start-up.
Upon application of power, CVCC is charged via the preregulator, thereby providing an appropriate supply voltage
at the VCC pin for the LTC4278. This supply voltage is
typically in the range 7V and is used during start-up. After
converter startup, the third transformer winding becomes
energized and is designed to generate a higher voltage than
the preregulator. The higher voltage of the third winding
turns off QPR and provides an efficient method to power
the LTC4278.
Design of the VCC power circuitry involves selecting appropriate voltage ranges for both the preregulator and
the third transformer winding. The preregulator voltage
is set as low as possible while ensuring it’s worst-case
minimum voltage is high enough to drive the switching
FETs gates during the startup period. The third winding
output voltage is selected to ensure that it’s worst-case
minimum voltage exceeds the preregulator voltage in order
PG
•
FB
4278 F14
Figure 14. Typical Power Bootstrapping
Control Loop Compensation
Loop frequency compensation is performed by connecting a capacitor network from the output of the feedback
amplifier (VCMP pin) to ground as shown in Figure 15.
Because of the sampling behavior of the feedback amplifier,
compensation is different from traditional current mode
controllers. Normally only CVCMP is required. RVCMP can
be used to add a zero, but the phase margin improvement
traditionally offered by this extra resistor is usually already
accomplished by the nonzero secondary circuit impedance.
CVCMP2 can be used to add an additional high frequency
pole and is usually sized at 0.1 times CVCMP.
VCMP
17
CVCMP2
RVCMP
CVCMP
4278 F15
Figure 15. VCMP Compensation Network
4278fc
32
LTC4278
APPLICATIONS INFORMATION
In further contrast to traditional current mode switchers, VCMP pin ripple is generally not an issue with the
LTC4269‑1. The dynamic nature of the clamped feedback
amplifier forms an effective track/hold type response,
whereby the VCMP voltage changes during the flyback
pulse, but is then held during the subsequent switch-on
portion of the next cycle. This action naturally holds the
VCMP voltage stable during the current comparator sense
action (current mode switching).
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
VCMP reaches its 2.56V clamp. At clamp, the primary-side
MOSFET will turn off at the rated 100mV VSENSE level. This
repeats on the next cycle.
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
It is possible for the peak primary switch currents as
referred across RSENSE to exceed the max 100mV rating
because of the minimum switch on time blanking. If the
voltage on VSENSE exceeds 205mV after the minimum
turn-on time, the SFST capacitor is discharged, causing
the discharge of the VCMP capacitor. This then reduces
the peak current on the next cycle and will reduce overall
stress in the primary switch.
Slope Compensation
Short-Circuit Conditions
The LTC4278 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the DC is greater than 50%. In some switching
regulators, slope compensation reduces the maximum peak
current at higher duty cycles. The LTC4278 eliminates this
problem by having circuitry that compensates for the slope
compensation so that maximum current sense voltage is
constant across all duty cycles.
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhibited
by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is:
Minimum Load Considerations
At light loads, the LTC4278 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
tON(MIN) resistor. If this produces more power than the
load requires, power will flow back into the primary during the off period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efficiency is reduced.
Maximum Load Considerations
The current mode control uses the VCMP node voltage and
amplified sense resistor voltage as inputs to the current
comparator. When the amplified sense voltage exceeds the
VCMP node voltage, the primary-side switch is turned off.
DCMIN = t ON(MIN) • fOSC <
(
I SC • R SEC + R DS(ON)
VIN • N SP
)
where:
tON(MIN) is the primary-side switch minimum on-time
ISC is the short-circuit output current
NSP is the secondary-to-primary turns ratio (NSEC/NPRI)
(other variables as previously defined)
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
4278fc
33
LTC4278
APPLICATIONS INFORMATION
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
Output Voltage Error Sources
The LTC4278’s feedback sensing introduces additional
minor sources of errors. The following is a summary list:
• The internal bandgap voltage reference sets the reference
voltage for the feedback amplifier. The specifications
detail its variation.
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
• The transformer secondary current flows through the
impedances of the winding resistance, synchronous
MOSFET RDS(ON) and output capacitor ESR. The DC
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s off-time. So, divide the load current by
(1 – DC).
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LTC4278 load compensation circuitry
(see Load Compensation). If multiple output windings are
used, the flyback winding will have a signal that represents
an amalgamation of all these windings impedances. Take
care that you examine worst-case loading conditions when
tweaking the voltages.
where XMIN is peak-to-peak current ratio as defined earlier.
For each secondary-side power MOSFET, the peak current is:
For the primary-side power MOSFET, the peak current is:
IPK(PRI) =
PIN
VIN(MIN) • DCMAX
X
• 1+ MIN
2
X
IOUT
• 1+ MIN
1−DCMAX
2
Select a primary-side power MOSFET with a BVDSS
greater than:
BVDSS ≥IPK
VOUT(MAX)
LLKG
+ VIN(MAX) +
CP
NSP
where NSP reflects the turns ratio of that secondary-to
primary winding. LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from
the drain capacitance (COSS) of the primary-side power
MOSFET). A clamp may be added to reduce the leakage
inductance as discussed.
For each secondary-side power MOSFET, the BVDSS should
be greater than:
BVDSS ≥ VOUT + VIN(MAX) • NSP
Choose the primary-side MOSFET RDS(ON) at the nominal
gate drive voltage (7.5V). The secondary-side MOSFET gate
drive voltage depends on the gate drive method.
Primary-side power MOSFET RMS current is given by:
IRMS(PRI) =
PIN
VIN(MIN) DCMAX
For each secondary-side power MOSFET RMS current is
given by:
Power MOSFET Selection
The power MOSFETs are selected primarily on the criteria of
on-resistance RDS(ON), input capacitance, drain-to‑source
breakdown voltage (BVDSS), maximum gate voltage (VGS)
and maximum drain current (ID(MAX)).
IPK(SEC) =
IRMS(SEC) =
IOUT
1– DCMAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high VDS, a
transition power loss term is included for accuracy. CMILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
4278fc
34
LTC4278
APPLICATIONS INFORMATION
CMILLER is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 16).
PDIS(SEC) = IRMS(SEC)2 • RDS(ON)(1 + d)
MILLER EFFECT
VGS
a
b
QA
QB
GATE CHARGE (QG)
4278 F16
Figure 16. Gate Charge Curve
The flat portion of the curve is the result of the Miller (gate
to-drain) capacitance as the drain voltage drops. The Miller
capacitance is computed as:
CMILLER =
QB – Q A
VDS
With CMILLER determined, calculate the primary-side power
MOSFET power dissipation:
PD(PRI) =I RMS(PRI)2 • R DS(ON) (1+ δ ) +
PIN(MAX)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
TJ = TA + PDIS • qJA
where TA is the ambient temperature and qJA is the MOSFET
junction to ambient thermal resistance.
Once you have TJ iterate your calculations recomputing
d and power dissipations until convergence.
Gate Drive Node Consideration
The curve is done for a given VDS. The Miller capacitance
for different VDS voltages are estimated by multiplying the
computed CMILLER by the ratio of the application VDS to
the curve specified VDS.
VIN(MAX) •
The secondary-side power MOSFETs typically operate
at substantially lower VDS, so you can neglect transition
losses. The dissipation is calculated using:
• RDR •
CMILLER
•f
VGATE(MAX) – VTH OSC
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer efficiency.
where:
The LTC4278 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
maximum VGS of 10V and larger.
RDR is the gate driver resistance (≈10Ω)
Synchronous Gate Drive
VTH is the MOSFET gate threshold voltage
There are several different ways to drive the synchronous
gate MOSFET. Full converter isolation requires the synchronous gate drive to be isolated. This is usually accomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary, as shown in the
application on the front page of this data sheet.
DCMIN
fOSC is the operating frequency
VGATE(MAX) = 7.5V for this part
(1 + d) is generally given for a MOSFET in the form of a
normalized RDS(ON) vs temperature curve. If you don’t have
a curve, use d = 0.005/°C • DT for low voltage MOSFETs.
However, other schemes are possible. There are gate drivers
and secondary-side synchronous controllers available that
provide the buffer function as well as additional features.
4278fc
35
LTC4278
APPLICATIONS INFORMATION
Capacitor Selection
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors are
selected based on RMS current ratings and ripple voltage.
PIN
OUTPUT VOLTAGE
RIPPLE WAVEFORM
29.5W
41V
1– 49.4%
= 0.728A
49.4%
Keep input capacitor series resistance (ESR) and
inductance (ESL) small, as they affect electromagnetic
interference suppression. In some instances, high ESR can
also produce stability problems because flyback converters
exhibit a negative input resistance characteristic. Refer to
Application Note 19 for more information.
The output capacitor is sized to handle the ripple current
and to ensure acceptable output voltage ripple. The output
capacitor should have an RMS current rating greater than:
IRMS(SEC) =IOUT
DCMAX
1– DCMAX
Continuing the example:
IRMS(SEC) = 5.3A
49.4%
= 5.24A
1– 49.4%
This is calculated for each output in a multiple winding
application.
ESR and ESL along with bulk capacitance directly affect the
output voltage ripple. The waveforms for a typical flyback
converter are illustrated in Figure 17.
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose of
simplicity, we will choose 2% for the maximum output
∆VESR
4278 F17
Figure 17. Typical Flyback Converter Waveforms
Continuing the example:
IRMS(PRI) =
RINGING
DUE TO ESL
∆VCOUT
1– DCMAX
DCMAX
VIN(MIN)
IPRI
N
SECONDARY
CURRENT
Select an input capacitor with a ripple current rating
greater than:
IRMS(PRI) =
IPRI
PRIMARY
CURRENT
ripple, divided equally between the ESR step and the
charging/discharging DV. This percentage ripple changes,
depending on the requirements of the application. You can
modify the following equations.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
ESRCOUT ≤ 1% •
VOUT • (1– DCMAX )
IOUT
The other 1% is due to the bulk C component, so use:
COUT ≥
IOUT
1% • VOUT • fOSC
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing our example, the output capacitor needs:
5V • (1– 49.4%)
= 4mΩ
5.3A
5.3A
= 600µF
COUT ≥
1% • 5 • 200kHz
ESRCOUT ≤ 1% •
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
4278fc
36
LTC4278
APPLICATIONS INFORMATION
One way to reduce cost and improve output ripple is to use
a simple LC filter. Figure 18 shows an example of the filter.
L1, 0.1µH
FROM
SECONDARY
WINDING
+
C1
47µF
×3
+
ISOLATION
VOUT
COUT
470µF
unidirectional 58V transient voltage suppressor be installed
between the diode bridge and the LTC4278 (D3 in Figure 2).
COUT2
1µF
RLOAD
4278 F18
Figure 18.
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a COUT 1/4 the size of the nonfilter
solution. Make C1 1/4 of COUT to make the second filter
pole independent of COUT. C1 may be best implemented
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1µH filter inductor is sufficient. Add a small ceramic
capacitor (COUT2) for high frequency noise on VOUT. For
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitic. LTC SwitcherCAD® is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4278 is specified to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily VPORTN and VPORTP) can
routinely see peak voltages in excess of 10kV. To protect
the LTC4278, it is highly recommended that the SMAJ58A
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4278 or support circuitry
other than the RJ-45 port.
LAYOUT CONSIDERATIONS FOR THE LTC4278
The LTC4278’s PD front end is relatively immune to layout
problems. Excessive parasitic capacitance on the RCLASS
pin should be avoided. Include a PCB heat sink to which
the exposed pad on the bottom of the package can be
soldered. This heat sink should be electrically connected
to GND. For optimum thermal performance, make the
heat sink as large as possible. Voltages in a PD can be as
large as 57V for PoE applications, so high voltage layout
techniques should be employed. The SHDN pin should
be separated from other high voltage pins, like VPORTP,
VNEG, to avoid the possibility of leakage currents shutting
down the LTC4278. If not used, tie SHDN to VPORTN. The
load capacitor connected between VPORTP and VNEG of the
LTC4278 can store significant energy when fully charged.
The design of a PD must ensure that this energy is not
inadvertently dissipated in the LTC4278. The polarityprotection diodes prevent an accidental short on the cable
from causing damage. However if, VPORTN is shorted
to VPORTP inside the PD while capacitor C1 is charged,
4278fc
37
LTC4278
APPLICATIONS INFORMATION
current will flow through the parasitic body diode of the
internal MOSFET and may cause permanent damage to
the LTC4278.
Check that the maximum BVDSS ratings of the MOSFETs
are not exceeded due to inductive ringing. This is done by
viewing the MOSFET node voltages with an oscilloscope. If
it is breaking down, either choose a higher voltage device,
add a snubber or specify an avalanche-rated MOSFET.
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LTC4278 directly
to the ground terminal of the VCC decoupling capacitor,
the bottom terminal of the current sense resistor and the
ground terminal of the input capacitor, using a ground plane
with multiple vias. Place the VCC capacitor immediately
adjacent to the VCC and GND pins on the IC package. This
capacitor carries high di/dt MOSFET gate drive currents.
Use a low ESR ceramic capacitor.
Place the small-signal components away from high frequency
switching nodes. This allows the use of a pseudo-Kelvin
connection for the signal ground, where high di/dt gate
driver currents flow out of the IC ground pin in one direction
(to the bottom plate of the VCC decoupling capacitor) and
small-signal currents flow in the other direction.
Keep the trace from the feedback divider tap to the FB pin
short to preclude inadvertent pick-up.
Take care in PCB layout to keep the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. This reduces the parasitic inductance and
also minimizes magnetic field radiation. Figure 19 outlines
the critical paths.
For applications with multiple switching power converters
connected to the same input supply, make sure that the
input filter capacitor for the LTC4278 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple which could
interfere with the LTC4278 operation. A few inches of PC
trace or wire (L @ 100nH) between the CIN of the LTC4278
and the actual source VIN, is sufficient to prevent current
sharing problems.
Keep electric field radiation low by minimizing the length
and area of traces (keep stray capacitances low). The drain
of the primary-side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes.
T1
VCC
VIN
CVCC
•
•
GATE
TURN-ON
VCC
PG
MP
+
•
CVIN
OUT
GATE
TURN-OFF
RSENSE
VCC
VCC
SG
•
T2
+
+
CR
Q4
GATE
TURN-ON
COUT
MS
•
Q3
GATE
TURN-OFF
4278 F19
Figure 19. Layout Critical High Current Paths
4278fc
38
AUX–
SPARE2
VPORT_N
SPARE1
RXCT
TXCT
VPORT_P
AUX+
AUXILIARY SUPPLY
8V TO 57V
B1100 (8 PLCS)
S1B
L1: COILCRAFT, DO1813P-181HC
L2: WÜRTH, 7443330820
C2, C6: TDK, C3225X7S2A335M
C1, C3: MURATA, GRM31CR60J226KE19
C9: TDK, C3225X5R0J107M
20k
2.49k
54.9k
294k
0.1µF
100V
10Ω
PDS5100H
24k
BSS63LT1
SMAJ58A
+
3.01k
21.5k
VPORTP
T2P
B1100
30.9Ω
RCLASS VPORTN VPORTN
UVLO
SHDN
NC
FB
C6
C2
3.3µF
×2
PWRGD /PWRGD
10µF
100V
L2
8.2µH
LTC4278IDKD
1µF
VCC
FMMT624
VCC
7.5V
CMHZ4693
20k
12k
VNEG VNEG PGDLY
PG
SG
1.82k
38.3k
SYNC RCMP ENDLY OSC
100k
tON
EXPOSED PAD SOLDER SIDE
20Ω
BAS21
33pF
CCMP
0.1µF
GND
VCMP
SENSE–
SENSE+
220pF
47Ω
10k
3
4
1
2
4278 TA02
3.3k
33nF
12m
6
5
•
3.3nF
3
1
1µF
•
•
11
12
7
8
•
2.2nF
4
EPA4271GE
6
5.1Ω
1nF
EPC3472G-LF
•
4.7nF, 2kV
PS2801-1-L
100Ω
FDMS86101
VCC
BAT54
CMLT7820G
+VOUT
5V AT 4.5A
10k
15Ω
CMLT3820G
+VOUT
–VOUT
C9
100µF
HAT2169H
C3, C1
22µF
×2
L1
180nH
10k
T2P
1µF
LTC4278
TYPICAL APPLICATION
4278fc
39
LTC4278
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DKD Package
DKD Package
32-Lead Plastic
DFN (7mm × 4mm)
32-Lead Plastic
DFN
(7mm × 4mm)
(Reference
LTC DWG
# 05-08-1734
Rev A)
(Reference LTC DWG # 05-08-1734 Rev A)
0.70 ±0.05
0.70 ±0.05
4.50 ±0.05
6.43 ±0.05
4.50 ±0.05
6.43 ±0.05
2.65
±0.05
2.65
±0.05
3.103.10
±0.05
±0.05
PACKAGE
PACKAGE
OUTLINE
OUTLINE
0.20 ±0.05
0.20
0.40
BSC
0.40
BSC
6.00REF
REF
6.00
RECOMMENDEDSOLDER
SOLDERPAD
PADLAYOUT
LAYOUT
RECOMMENDED
APPLY
SOLDER
MASKTO
TOAREAS
AREASTHAT
THATARE
ARE NOT
NOT SOLDERED
SOLDERED
APPLY
SOLDER
MASK
7.00 ±0.10
7.00 ±0.10
R = 0.115
R = 0.115
TYP
17
R = 0.05
R =TYP
0.05
32
TYP
17
32
0.40 ±0.10
0.40 ±0.10
TYP
6.43 ±0.10
6.43 ±0.10
4.00 ±0.10
2.65 ±0.10
2.65 ±0.10
4.00 ±0.10
PIN 1 NOTCH
R = 0.30PIN
TYP1 OR
NOTCH
0.35 × 45°
R =CHAMFER
0.30 TYP OR
PIN 1
0.35 × 45° CHAMFER
TOP
PIN
1 MARK
(SEE
NOTE 6)
TOP
MARK
(SEE NOTE 6)
16
0.75 ±0.05
0.75 ±0.05
16
0.40 BSC
0.20 ±0.05
0.20 ±0.05
0.40 BSC
6.00 REF
6.00 REF PAD
BOTTOM VIEW—EXPOSED
0.200 REF
0.00 – 0.05
0.00 – 0.05
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
NOTE:IN JEDEC PACKAGE OUTLINE M0-229
1. DRAWING
PROPOSED
TO BE MADE VARIATION OF VERSION (WXXX)
2. DRAWING
NOT TO SCALE
3. ALL
DIMENSIONS
ARE IN MILLIMETERS
IN
JEDEC
PACKAGE OUTLINE
M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
1
(DKD32) QFN 0707 REV A
BOTTOM VIEW—EXPOSED PAD
0.200 REF NOTE:
1
(DKD32) QFN 0707 REV A
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
DIMENSIONS
OF EXPOSED
PAD PLATED
ON BOTTOM OF PACKAGE DO NOT INCLUDE
5.4.EXPOSED
PAD SHALL
BE SOLDER
6. SHADED
AREA ISMOLD
ONLY FLASH,
A REFERENCE
FOR PIN
1 LOCATION
MOLD FLASH.
IF PRESENT,
SHALL
NOT EXCEED 0.20mm ON ANY SIDE
THE TOPPAD
ANDSHALL
BOTTOM
PACKAGE
5.ON
EXPOSED
BEOF
SOLDER
PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4278fc
40
LTC4278
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
3/12
Added B1100 to schematic
C
4/12
PAGE NUMBER
1, 19
Revised Max Junction Temperature
2
Added Typical Application
39
Updated component values on Typical Application
1
Updated Maximum Junction Temperature to 125°C
2
Updated Typical Application
39
4278fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
41
LTC4278
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®
COMMENTS
Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current
TM
4278fc
42 Linear Technology Corporation
LT 0412 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 l FAX: (408) 434-0507
l
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