1642AI

LTC1642A Hot Swap Controller FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Adjustable Undervoltage and Overvoltage Protection Foldback Current Limit Adjustable Current Limit Time-Out VCC: 2.97V to 16.5V Normal Operation, Protected Against Surges to 33V Single Channel NFET Driver Latch Off or Automatic Retry on Current Fault Driver for SCR Crowbar on Overvoltage Adjustable Reset Timer Reference Output with Uncommitted Comparator 16-Pin SSOP Package The LTC®1642A is a 16-pin Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using an external N-Channel pass transistor, the board supply voltage can be ramped up at an adjustable rate. A high side switch driver controls the N-Channel gate for supply voltages ranging from 2.97V to 16.5V. The SENSE pin allows foldback limiting of the load current, with circuit breaker action after an adjustable delay time. The delay allows the part to power-up in current limit. The CRWBR output can be used to trigger an SCR for crowbar protection of the load if the input supply exceeds an adjustable threshold. The RESET output can generate a system reset with adjustable delay when the supply voltage falls below an adjustable threshold. The ON pin cycles the board power. The LTC1642A is available in the 16-pin SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Hot Swap is a trademark of Linear Technology Corporation. APPLICATIO S ■ ■ ■ Hot Board Insertion Electronic Circuit Breaker InfiniBandTM Systems TYPICAL APPLICATIO BACKPLANE 12V PLUG-IN CARD 0.010Ω 5% FDS6630A (SHORT PIN) 110k 1% 1N4705 18V 100Ω 5% 330Ω 5% 0.047µF 107k 1% VCC SENSE GATE RESET FB CRWBR COMP– COMP+ 2N2222 MCR 12DC UV = 10.8V 2.87k 1% OV = 13.2V 11.3k 1% ON FAULT OV GND BRK TMR LTC1642A COMPOUT RST TMR REF 0.33µF GND 0.33µF 0.1µF 0.01µF 1642a TA01 U + 12V AT 2.5A CLOAD POWER-GOOD = 11.4V 13k 1% 1642af U U 1 LTC1642A ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW CRWBR 1 BRK TMR 2 RST TMR 3 ON 4 RESET 5 FAULT 6 FB 7 GND 8 16 VCC 15 SENSE 14 GATE 13 REF 12 COMP – 11 COMP + 10 COMPOUT 9 OV Supply Voltage (VCC) .................................– 0.3V to 33V SENSE Pin ................................... – 0.3V to (VCC + 0.3V) ON, FB, OV, COMP +, COMP – RESET, FAULT, COMPOUT .....................– 0.3V to 18.5V Operating Temperature Range LTC1642AC ............................................. 0°C to 70°C LTC1642AI ......................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER LTC1642ACGN LTC1642AIGN GN PART MARKING 1642A 1642AI GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 130°C/W Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise specified. SYMBOL VCC ICC VLKHI VLKLO VLKHYST VFB ∆VFB VFBHST IFB(IN) VOV ∆VOV VOVHYST IOV(IN) VRST ∆VRST IRST VBRK ∆VBRK IBRK VCR ∆VCR ICR PARAMETER Operating Voltage Range VCC Supply Current VCC Undervoltage Lockout VCC Undervoltage Lockout VCC Undervoltage Lockout Hysteresis FB Pin Voltage Threshold FB Pin Threshold Supply Variation FB Pin Voltage Threshold Hysteresis FB Pin Input Current OV Pin Voltage Threshold OV Pin Threshold Supply Variation OV Pin Voltage Theshold Hysteresis OV Pin Input Current RST TMR Pin Voltage Threshold RST TMR Pin Threshold Supply Variation RST TMR Pin Current BRK TMR Pin Voltage Threshold BRK TMR Pin Threshold Supply Variation BRK TMR Pin Current CRWBR Pin Voltage Theshold CRWBR Pin Threshold Supply Variation CRWBR Pin Current CONDITIONS ● MIN 2.97 2.55 2.35 1.208 TYP 1.25 2.73 2.50 230 1.220 5 3 0 1.220 5 3 0 1.220 5 – 2.0 10 1.220 5 – 20 10 410 4 – 45 –1500 2.3 ON = VCC VCC Rising VCC Falling FB Falling FB Falling, 2.97V ≤ VCC ≤ 16.5V VOV = 5V OV Rising OV Rising, 2.97V ≤ VCC ≤ 16.5V VFB = 5V RST TMR Rising RST TMR Rising, 2.97V ≤ VCC ≤ 16.5V Timer On Timer Off, VRSTTMR = 1.5V BRK TMR Rising BRK TMR Rising, 2.97V ≤ VCC ≤ 16.5V Timer On Timer Off, VBRKTMR = 1.5V CRWBR Rising 2.97V ≤ VCC ≤ 16.5V CRWBR On, VCRWBR = 0V CRWBR On, VCRWBR = 2.1V CRWBR Off, VCRWBR = 1.5V ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● MAX 16.5 3.0 2.95 2.95 1.232 15 ±1 1.232 15 ±1 1.250 15 – 2.5 1.250 15 – 30 425 15 – 60 1.208 1.200 – 1.5 1.200 – 15 375 – 30 –1000 UNITS V mA V V mV V mV mV µA V mV mV µA V mV µA mA V mV µA mA mV mV µA µA mA 1642af 2 U W U U WW W LTC1642A DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise specified. SYMBOL VCB PARAMETER Circuit Breaker Trip Voltage CONDITIONS VCB = (VCC – VSENSE), VFB = GND VCB = (VCC – VSENSE), VFB = 1V 2.97V ≤ VCC ≤ 16.5V, VCB = (VCC – VSENSE), VFB = GND VCB = (VCC – VSENSE), VFB = 1V ISENSE IGATE ∆VGATE SENSE Pin Input Bias Current GATE Pin Output Current External N-Channel Gate Drive VCC = VSENSE = 16.5V Charge Pump On, VGATE = GND Charge Pump Off, VGATE = 5V VGATE – VCC, VCC = 2.97V VGATE – VCC, VCC = 5V VGATE – VCC, VCC = 15V (0°C to 70°C) VGATE – VCC, VCC = 15V (–40°C to 85°C) ON Rising ON Falling VON = 5V ● ● ● ● ● ● ● ● ● ● ● ● MIN 15 45 12 42 – 20 4.5 10 6.5 6 1.30 1.20 TYP 25 52.5 25 52.5 – 25 10 5.9 11.5 8.5 8.5 1.34 1.22 110 0 MAX 36 60 39 63 0.5 – 30 8.0 14 18 18 1.38 1.26 ±1 0.4 2 UNITS mV mV mV mV µA µA mA V V V V V V mV µA V V µA V mV mV mA mV mV VONHI VONLO VONHYST ION(IN) VOL IPU VREF ∆VLNR ∆VLDR IRSC VCOS VCHYST ON Pin Threshold ON Pin Threshold ON Pin Hysteresis ON Pin Input Current Output Low Voltage Logic Output Pull-Up Current Reference Output Voltage Reference Supply Variation Reference Load Regulation Reference Short-Circuit Current Comparator Offset Voltage Comparator Hysteresis RESET, FAULT, COMPOUT IOL = 1.54mA ● RESET, FAULT IO = 5mA RESET, FAULT = GND No Load 2.97V ≤ VCC ≤ 16.5V, No Load IO = 0mA to –1mA, Sourcing Only VREF = 0V VCM = VREF VCM = VREF ● ● ● ● – 15 1.208 1.220 5 2.5 4.5 ±10 3 1.232 15 7.5 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. TYPICAL PERFOR A CE CHARACTERISTICS ∆VGATE vs Temperature 16 14 12 ∆VGATE (V) 10 VCC = 15V 8 6 VCC = 3V 4 3 2 0 –50 0 VCC = 5V ∆VGATE (V) VCC = 12V 12 15 TA = 25°C 9 IGATE (µA) –25 0 25 50 75 TEMPERATURE (°C) UW 100 125 1642a G03 ∆VGATE vs VCC 30 29 28 27 26 25 24 23 22 21 3 6 9 VCC (V) 12 15 1642a G26 IGATE vs Temperature VCC = 3V VCC = 5V VCC = 12V VCC = 15V 6 VGATE = 0V –25 0 25 50 75 TEMPERATURE (°C) 100 125 20 –50 1642a G04 1642af 3 LTC1642A TYPICAL PERFOR A CE CHARACTERISTICS IGATE Pull-Up Current vs VCC 25 CRWBR–TMR THRESHOLD VOLTAGE (mV) 20 IGATE (µA) IGATE (A) 15 10 5 VGATE = 0V TA = 25°C 3 6 9 VCC (V) 12 15 1642a G23 0 CRWBR Driver Current vs VCC 2.0 TA = 25°C CRWBR DRIVER CURRENT (mA) CRWBR DRIVER CURRENT (mA) 1.6 FB THRESHOLD VOLTAGE (V) 1.2 0.8 0.4 0 3 6 9 VCC (V) 12 FB Threshold Voltage vs VCC 1.232 TA = 25°C FB THRESHOLD VOLTAGE (V) 1.226 FB RISING OV THRESHOLD VOLTAGE (V) 1.224 1.222 1.220 OV RISING 1.224 1.220 1.216 1.212 1.208 3 6 OV THRESHOLD VOLTAGE (V) 1.228 FB FALLING 9 VCC (V) 12 4 UW 15 1642a G35 GATE Pull-Down Current (Current Limit Active) 128 112 96 80 64 48 32 16 0 0 4 8 12 16 VGATE (V) 20 24 1642a G36 CRWBR-TMR Threshold Voltage vs Temperature 405 404 403 402 401 400 399 398 397 396 395 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 VCC = 5V TA = 25°C VCC = 12V VCC = 5V VCC = 3.3V 1642a G05 CRWBR Driver Current vs Temperature 1.45 VCC = 5V 1.44 1.43 1.42 1.41 1.40 1.39 1.38 –50 1.224 1.226 FB Threshold Voltage vs Temperature VCC = 5V FB RISING 1.222 1.220 FB FALLING 1.218 1.216 1.214 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1642a G13 1642a G06 OV Threshold Voltage vs Temperature 1.232 VCC = 5V OV Threshold Voltage vs VCC TA = 25°C 1.228 1.224 1.220 1.216 1.212 1.208 3 6 9 VCC (V) 12 15 1642a G28 OV RISING OV FALLING OV FALLING 1.218 1.216 1.214 –50 15 1642a G27 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1642a G07 1642af LTC1642A TYPICAL PERFOR A CE CHARACTERISTICS FAULT and RESET Pull-Up Current (IOH) vs VCC 160 140 PULL-UP CURRENT (µA) 120 100 80 60 40 20 0 3 6 9 VCC (V) 12 15 1642a G14 VOLTAGE (mV) TA = – 55°C TA = 25°C VCC = 3V 300 200 100 0 –50 VCC = 5V VCC = 12V VCC = 15V VOLTAGE (V) TA = 125°C Current Limit Threshold Voltage (Full Foldback) vs Temperature CURRENT LIMIT THRESHOLD VOLTAGE (mV) FB = 0V 27.0 26.5 VCC = 12V 26.0 VCC = 5V 25.5 VCC = 3V 25.0 24.5 –50 VCC = 15V CURRENT LIMIT THRESHOLD VOLTAGE (mV) 27.5 ON PIN THRESHOLD VOLTAGE (V) –25 0 25 50 75 TEMPERATURE (°C) VREF vs VCC 1.232 TA = 25°C 1.228 1.224 1.220 1.216 1.212 1.208 0 3 6 9 VCC (V) 12 15 1642a G24 10 VON = 5V ∆VREF (mV) VREF (V) ICC (mA) UW 100 FAULT and RESET VOL vs Temperature 600 IOL = 1.54mA 500 400 FAULT and RESET VOL vs Temperature 3.5 IOL = 5mA 3.0 2.5 2.0 1.5 1.0 0.5 0 –50 VCC = 3V VCC = 5V VCC = 12V VCC = 15V –25 0 25 50 75 TEMPERATURE (°C) 100 125 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1642a G16 1642a G17 Current Limit Threshold Voltage (Nominal) vs Temperature 57.0 FB = 1V 56.5 56.0 55.5 55.0 54.5 54.0 53.5 –50 VCC = 3V –25 0 25 50 75 TEMPERATURE (°C) 100 125 VCC = 15V VCC = 12V VCC = 5V 1.36 1.40 ON Pin Threshold Voltage vs Temperature VCC = 12V ON RISING 1.32 1.28 1.24 ON FALLING 1.20 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 125 1642a G20 1642a G21 1642a G22 ICC vs VCC 20 TA = 25°C Reference O/P Impedance 0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 – 42 TA = 25°C VCC = 5V VCC = 3.3V VCC = 12V, 15V VON = 0V 0 25 VCC (V) 50 1642a G25 0 2.5 5 7.5 10 12.5 15 17.5 20 IREF (mA) 1642a G37 1642af 5 LTC1642A PI FU CTIO S CRWBR (Pin 1): Overvoltage Crowbar Circuit Timer and Trigger. This pin controls an external overvoltage crowbar circuit. A capacitor from the pin to ground sets a 9ms/µF delay after an overvoltage occurs until an external SCR is triggered. See Applications Information. Ground the CRWBR pin if unused. BRK TMR (Pin 2): Circuit Breaker Timer. Connect a capacitor from BRK TMR to ground to set a 60ms/µF delay from the time the sense resistor current reaches its limit until the FET is shut off. FAULT output is then asserted and the FET remains off until the chip is reset. Ground BRK TMR to allow the part to remain in current limit indefinitely. RST TMR (Pin 3): Analog System/Reset Timer. A capacitor from this pin to ground sets a 0.6s/µF delay from the ON pin going high to the start of the GATE pin’s ramp. It also sets the delay from output voltage good, as sensed by the FB pin, to RESET going high. ON (Pin 4): ON Control Input. When ON is low the GATE pin is grounded and FAULT goes high. The GATE pin voltage starts ramping up one RST TMR timing cycle after ON goes high. Pulsing the ON pin low for at least 2µs resets the chip if it latches off after a sustained overvoltage or current limit. The threshold for a low to high transition is 1.34V with 110mV of hysteresis. A 21V zener clamp limits the voltage at this pin. The pin can be safely tied to VCC > 21V through a series resistor that limits the current below 1mA. RESET (Pin 5): Open Drain Reset Output. RESET is pulled low if the voltage at the FB pin is below its trip point. RESET goes high one RESET timing cycle after the FB voltage exceeds its trip point plus 3mV of hysteresis. RESET has a weak pull-up to one diode drop below VCC and an external resistor can pull the pin above VCC. A 21V zener clamp limits the voltage at this pin. The pin can be safely tied to VCC > 21V through a series resistor that limits the current below 1mA. FAULT (Pin 6): Open Drain Fault Output. FAULT is pulled low when the part turns off following a sustained overvoltage or current limit. It goes high 2µs after the ON pin goes low. FAULT has a weak pull-up to one diode drop below VCC and an external resistor can pull the pin above VCC. A 21V zener clamp limits the voltage at this pin. The pin can be safely tied to VCC > 21V through a series resistor that limits the current below 1mA. FB (Pin 7): Output Voltage Monitor and Foldback Input. The FB comparator can be used with an external resistive divider to monitor the output supply voltage. When the FB voltage is lower than 1.22V the RESET pin is pulled low. RESET goes high one system timing cycle after the voltage at FB exceeds its threshold by 3mV of hysteresis. A low pass filter at the comparator’s output prevents negative voltage glitches from triggering a false reset. GND (Pin 8): Chip Ground. 6 U U U 1642af LTC1642A PI FU CTIO S OV (Pin 9): Overvoltage Input. When the voltage on OV exceeds its trip point the GATE pin is pulled low immediately and the CRWBR timer starts. If OV remains above its trip point (minus 3mV of hysteresis) long enough for CRWBR to reach its trip point, then the part turns off until reset by pulsing the ON pin low. Otherwise, the GATE pin begins ramping up one RST TMR timing cycle after OV goes below its trip point. Ground the OV pin to disable overvoltage protection. COMPOUT (Pin 10): Uncommitted Comparator’s Open Drain Output. COMP + (Pin 11): Uncommitted Comparator’s Noninverting Input. COMP – (Pin 12): Uncommitted Comparator’s Inverting Input. REF (Pin 13): Reference Voltage Output. The 1.22V ± 1% reference should be bypassed with a 0.1µF compensation capacitor. For VCC = 5V it can source 1mA. GATE (Pin 14): Gate Drive for the External N-Channel MOSFET. An internal charge pump provides at least 4.5V of gate drive and sources 25µA. The pin requires an external series RC network to ground to compensate the current limit loop and to limit the ramp rate. A resistor of 100Ω is also recommended in series with the MOSFET gate to suppress high frequency oscillations. GATE is immediately pulled to ground when the overvoltage comparator trips or the input supply is below the undervoltage lockout trip point. During current limit the GATE voltage is adjusted to maintain constant load current until the circuit breaker timer trips. At that point GATE is pulled to ground until the chip is reset. Clamp the GATE pin with a zener diode to ground if the supply is 8V or higher. For the 8V to 12V range use an 18V zener (1N4705), and for supplies exceeding 12V use a 20V zener (TOSHIBA 02DZ20Y). SENSE (Pin 15): Current Sense Input. To use the current limit place a sense resistor in the supply path between VCC and SENSE. When the drop across the resistor exceeds a threshold voltage, the GATE pin is adjusted to maintain a constant load current and the circuit breaker timer is started. A foldback feature reduces the current limit as the voltage at FB approaches ground. Short SENSE to VCC to disable the current limiting. VCC (Pin 16): Positive Supply Voltage. An internal undervoltage lockout circuit holds the GATE pin at ground until VCC exceeds 2.73V. If VCC exceeds 16.5V an internal shunt regulator protects the chip from VCC and SENSE pin voltages up to 33V. In this case the GATE pin voltage will usually be low but this is not guaranteed; use the OV pin to ensure that the pass device is off. The VCC pin also provides a high side connection to the SENSE resistor. U U U 1642af 7 LTC1642A BLOCK DIAGRA W GATE 14 VCC 16 VCC CRWBR 1 21.5V 23mV TO 53mV CHARGE PUMP 25µA 45µA 1.5mA 21V 1.22V + – – SENSE 15 + 13 REF – + 0.41V 21V + – FB 7 21V 1.22V – + RISING DELAY 15µs TO 100µs VCC 10µA AT 5V OV 9 21V 1.22V + – RISING DELAY 15µs TO 100µs LOGIC 5 RESET 21V ON 4 21V 1.22V + – RISING DELAY 2µ s VCC 10µA AT 5V VCC + 2.7V – RISING DELAY 10µs 6 FAULT 21V 20µA 10 COMPOUT COMP + 11 2µA + – 21V 21V 21V 21V 1.22V + – 1.22V + – 21V COMP – 12 2 BRK TMR 3 RST TMR 1642a BD 1642af 8 LTC1642A APPLICATIO S I FOR ATIO Hot Circuit Insertion When a circuit board is inserted into a live backplane its supply bypass capacitors can draw large currents from the backplane power bus as they charge. These currents can permanently damage connector pins and can glitch the backplane supply, resetting other boards in the system. The LTC1642A limits the charging currents drawn by a board’s capacitors, allowing safe insertion into a live backplane. In the circuit shown in Figure 1 the LTC1642A and the external NMOS pass transistor Q1 work together to limit charging currents. Waveforms at board insertion are shown in Figure 2. When power is first applied to VCC the chip holds Q1’s gate at ground. After an adjustable delay a 25µA current source begins to charge the external capacitor C2, so choose C2 to limit the inrush current IINRUSH charging the board’s bypass capacitance CLOAD according to the equation: C2 = CLOAD • 25µA IINRUSH An internal charge pump supplies the 25µA gate current, ensuring sufficient gate drive to Q1. At 3V VCC the minimum gate drive is 4.5V; at 5V VCC the minimum is 10V; at 15V VCC the minimum is again 6.5V, due to an internal zener clamp from the GATE pin to ground. Resistor R3 limits this zener’s transient current during board insertion and removal and protects against high frequency oscillations in Q1. D1 provides additional protection against supply spikes. VIN 12V 2.5A R7 24k R2 0.010Ω 16 VCC 4 ON 15 SENSE GATE 14 Q1 FDS6630A + R3 100Ω R4 330Ω C2 0.047µF 6 VOUT CLOAD LTC1642A 2 R10 30k C4 0.33µF D1 1N4705 18V BRK TMR RST TMR 3 FAULT GND 8 C1 0.33µF ALL RESISTORS ± 5% UNLESS NOTED RESET DELAY = 200ms SHORT-CIRCUIT DURATION = 10ms 1642a F01 Figure 1. Supply Control Circuitry U The delay before the GATE pin voltage begins ramping is determined by the system timer. It comprises an external capacitor C1 from the RST TMR pin to ground; an internal 2µA current source feeding RST TMR from VCC; an internal comparator, with the noninverting input tied to RST TMR and the inverting input tied to the 1.22V reference; and an internal NMOS pull-down. In standby, the NMOS holds RST TMR at ground. When the timer starts the NMOS turns off and the RST TMR voltage ramps up as the current source charges the capacitor. When RST TMR reaches 1.22V the timer comparator trips, the GATE voltage begins ramping up and RST TMR returns to ground. The timer delay is: tRSTTMR = (615ms/µF) C1. The second RST TMR cycle indicates that VOUT is within tolerance; it is discussed in the Undervoltage Monitor section. OV 10V/DIV RST TMR 2V/DIV GATE 20V/DIV VOUT 20V/DIV 100ms/DIV 1642a F02 W U U Figure 2. Timing at Board Insertion Powering-Up in Current Limit Ramping the GATE pin voltage limits the current to I = 25µA • CLOAD/C2, where C2 is the external capacitor connected to the GATE and CLOAD is the load capacitance. If the value of CLOAD is uncertain, then a worst-case design can often result in needlessly long ramp times, and it may be better to limit the charging current by powering up in current limit. Current Limiting and Solid-State Circuit Breaker The current can be limited by connecting a sense resistor between the LTC1642A’s VCC and SENSE pins. When the voltage drop across this resistor reaches a limiting value, 1642af 9 LTC1642A APPLICATIO S I FOR ATIO an internal servo loop adjusts the GATE pin voltage such that Q1 acts as a constant current source. The voltage limit across R2 increases as the output charges; this foldback in the current limit helps to even out Q1’s power dissipation. The output is sensed at the FB pin. When FB is grounded, the sense voltage is limited to 26mV. When FB is greater than 0.7V, the limit is 56mV and the full dependence is shown in Figure 3. When the sense resistor voltage is 3mV below its limit, the circuit breaker timer starts. Once BRK TMR reaches its threshold, the circuit breaker opens, the GATE pin is pulled to ground (cutting off Q1) and FAULT is asserted. The parameter VCB specified in the DC electrical characteristics refers to the voltage difference between the VCC and SENSE pins needed to start the circuit breaker timer. The limiting value maintained by the servo loop is 3mV higher than VCB. Should the sense resistor voltage drop below its limit before the timer trips, the GATE voltage begins ramping back up immediately and the BRK TMR pin returns to ground. However, due to the slow gate ramp, Q1 continues to dissipate substantial power for some time. Connecting R10 in series with timing capacitor C4 (as shown in Figure 1) ensures that the circuit breaker trips in the event of repetitive, but brief, load shorts. The delay before the circuit breaker opens is: tBRKTMR = C4 (61kΩ – R10). Once the circuit breaker trips, GATE and FAULT remain at ground until the chip is restarted. To restart, hold the ON MAXIMUM SENSE RESISTOR VOLTAGE (mV) 70 60 50 VOUT 40 BRK TMR 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FB PIN VOLTAGE (mV) 1 FAULT ON RST TMR 40ms/DIV 1642a F04 1642a F03 Figure 3. Foldback Current Limit 1642af 10 U pin low for at least 2µs and FAULT will go high. Then take ON high again and the GATE will ramp up after a system timing cycle. Or, configure the LTC1642A to restart itself after the circuit breaker trips by connecting FAULT to the ON pin, as shown in the next section. The servo loop controlling Q1 during current limit has a unity-gain frequency of about 125kHz. In Figure 1, R4 and C2 provide compensation. To ensure stability the product 1/(2 • π • R4 • C2) should be kept below the unity-gain frequency, and C2 should be more than Q1’s input capacitance CISS. A good starting point for C2 is 0.047µF and R4 is 330Ω. Keep R4 ≥ 100Ω. Typical waveforms during a load short to ground are shown in Figure 4. The load is shorted to ground at time 1. The GATE voltage drops until the load current equals its maximum limit, and the circuit breaker timer starts. The short is cleared at time 2, before the timer trips. The BRK TMR pin returns to ground, and the GATE voltage begins ramping up. At time 3 the load is shorted again and at time 4 the timer trips, pulling the GATE to ground and asserting FAULT. Although the short is cleared at time 5, FAULT doesn’t go high until the ON pin is pulled low at time 6. At time 7 ON goes high and the system timer starts. When it trips at time 8 the GATE voltage begins ramping. To disable current limit and electronic circuit breaker protection, tie the SENSE pin to VCC, the BRK TMR pin to GND and omit compensating resistor R4. t2 t1 ILOAD t4 t6 t3 t5 t7 t8 5A/DIV GATE 20V/DIV 20V/DIV 2V/DIV 20V/DIV 20V/DIV 2V/DIV W U U Figure 4. Current Limit and Circuit Breaker Timing LTC1642A APPLICATIO S I FOR ATIO Automatic Restart After the Circuit Breaker Opens The LTC1642A will automatically attempt to restart itself after the circuit breaker opens if the FAULT output is tied to the ON pin. The circuit is shown in Figure 5. Diode D1 blocks the weak FAULT pull-up current source from unbalancing the R6-R5 divider. During a continuous current limit such as a load short, Q1’s duty cycle is equal to the circuit breaker timer period, divided by the sum of the circuit breaker and system timer periods: Short - Circuit Duty Cycle = C4 C 4 + 10 • C1 VIN 12V 2.5A R6 464k 1% 4 6 D1 1N4148 R5 60.4k 1% R10 30k C4 0.33µF 2 ON The duty cycle is 9% for the Figure 5 circuit. Waveforms during a load short are shown in Figure 6. Undervoltage Lockout An internal undervoltage lockout circuit holds the charge pump off until VCC exceeds 2.73V. If VCC falls below 2.5V, it turns off the charge pump and clears overvoltage and current limit faults. For higher lockout thresholds tie the ON pin to a resistor divider driven from VCC, as shown in Figure 7. This circuit keeps the charge pump off until VCC exceeds (1+R6/R5) • 1.34V, and also turns it off if VCC falls below (1+R6/R5) • 1.22V. R2 0.015Ω 16 R6 464k 1% UNDERVOLTAGE LOCKOUT THRESHOLD = 10.7V 4 VCC 15 SENSE VGATE 20V/DIV VIN 12V 2.5A ALL RESISTORS ± 5% UNLESS NOTED Figure 7. Setting a Higher Undervoltage Lockout 1642af U R2 0.015Ω 16 VCC 15 SENSE GATE 14 R4 330Ω C2 0.047µF GND 8 D2 1N4705 18V Q1 FDS6630A W U U + R3 100Ω VOUT CLOAD FAULT LTC1642A BRK TMR RST TMR 3 C1 0.33µF ALL RESISTORS ± 5% UNLESS NOTED 1642a F05 Figure 5. Automatic Restart Circuit VOUT 10V/DIV VBRKTMR 1V/DIV VRSTTMR 1V/DIV 40ms/DIV 1642a F06 Figure 6. Automatic Retry Following a Load Short Q1 FDS6630A + R3 100Ω 14 VOUT CLOAD LTC1642A ON GATE R5 60.4k 1% R4 330Ω RST TMR 3 C1 0.33µF GND 8 C2 0.047µF D1 1N4705 18V 1642a F07 11 LTC1642A APPLICATIO S I FOR ATIO Overvoltage Protection The LTC1642A can protect a load from overvoltages by turning off the pass transistor if the supply voltage exceeds an adjustable limit, and by triggering a crowbar SCR if the overvoltage lasts longer than an adjustable time. The part can also be configured to automatically restart when the overvoltage clears. The overvoltage protection circuitry is shown in Figure 8. The external components comprise a resistor divider driving the OV pin, timing capacitor C5, NPN emitter follower Q2, and crowbar SCR Q3. Because the MCR12DC is not a sensitive-gate device, the optional resistor shunting the SCR gate to ground is omitted. The internal components comprise a comparator, 1.22V bandgap reference, two current sources, and a timer at the CRWBR pin. When VCC exceeds (1+R6/R5) • 1.22V the comparator’s output goes high and internal logic turns off Q1 and starts the timer. This timer has a 0.410V threshold and uses the CRWBR pin; when CRWBR reaches 0.410V the timer comparator trips, and the current sourced from VCC increases to 1.5mA. Emitter follower Q2 boosts this current to trigger crowbar SCR Q3. The ramp time ∆t needed to trip the comparator is: tCRWBR = 9.1(ms/µF) C5 VIN 12V 2.5A R2 0.015Ω R6 127k 1% 16 VCC OV GATE 15 SENSE 14 R4 330Ω C2 0.047µF Q2 2N2222 CRWBR GND 8 C5 0.01µF CRWBR * ADD 220Ω RESISTOR IF USING A SENSITIVE-GATE SCR RST TMR ON ALL RESISTORS ± 5% UNLESS NOTED OV COMPARATOR TRIPS AT VIN = 13.85V RESET TIME = 200ms CROWBAR DELAY TIME = 90µs FAULT 1642a F08 Q1 FDS6630A + R3 100Ω CLOAD 9 R5 12.4k 1% LTC1642A D1 1N4705 18V 4 6 ON FAULT RST TMR 3 C1 0.33µF 1 Q3 MCR12DC Figure 8. Overvoltage Protection Circuitry 12 U Once the CRWBR timer trips the LTC1642A latches off: after the overvoltage clears GATE and FAULT remain at ground and CRWBR continues sourcing 1.5mA. To restart the part after the overvoltage clears, hold the ON pin low for at least 2µs and then bring it high. The GATE voltage will begin ramping up one system timing cycle later. The part will restart itself if FAULT and ON are connected. Figure 9 shows typical waveforms when the divider is driven from VCC. The OV comparator goes high at time 1, causing the chip to pull the GATE pin to ground and start the CRWBR timer. At time 2, before the timer’s comparator trips, OV falls below its threshold; the timer resets and GATE begins charging one system timing cycle later at time 3. Another overvoltage begins at time 4, and at time 5 the CRWBR timer trips; FAULT goes low and the CRWBR pin begins sourcing 1.5mA. Even after OV falls below 1.22V at time 6, GATE and FAULT stay low, and CRWBR continues to source 1.5mA. FAULT goes high when ON goes low at time 7, and GATE begins charging at time 8, one RST TMR cycle after FAULT goes high. Figure 10 shows typical waveforms when the OV divider is driven from the N-Channel’s output side. Because the voltage driving the divider collapses after the OV comparator trips, FAULT stays high and CRWBR stays near ground, which prevents the pin from triggering an SCR. The GATE voltage begins ramping up after a RST TMR timing cycle. To disable overvoltage protection completely, tie the OV and CRWBR pins to GND. For overvoltage protection at the GATE pin, but without latch off or a crowbar SCR such as Q3 in Figure 1, tie CRWBR to GND. t1 t2 IN OV VOUT W U U t3 t4 t5 t6 t7 t8 20V/DIV 2V/DIV GATE OUT 50V/DIV 20V/DIV 1V/DIV 2V/DIV 20V/DIV 20V/DIV 100ms/DIV 1642a F09 Figure 9. Overvoltage Timing (Input Side) 1642af LTC1642A APPLICATIO S I FOR ATIO Automatic Restart If there is an overvoltage, and the resistor divider feeding OV is connected to the output of the N-Channel pass transistor, the LTC1642A will automatically restart even if FAULT is not tied to ON. If the divider is connected to the input side, the LTC1642A will restart itself only if FAULT is tied to ON, and only after the overvoltage clears. The OV and FB Comparators The propagation delay through the OV and FB comparators on low to high transitions depends strongly on the differential input voltage. The relationship is shown in Figure 11. The minimum propagation delay for large overdrives is about 20µs. In addition the comparators have 3mV of hysteresis. Internal Voltage Clamp Protection The LTC1642A includes a shunt regulator to protect itself from VCC and SENSE pin voltages up to 33V. The regulator turns on when VCC exceeds 16.5V and limits most of the chip’s circuitry to 15V. When it is on the chip functions normally with one exception: if the charge pump is on, the GATE voltage is usually near ground but this is not guaranteed. Use the OV pin to ensure that GATE is grounded. IN 20V/DIV OV COMPARATOR PROPAGATION DELAY (µs) OV GATE OUT CRWBR RST TMR FAULT 100ms/DIV 1642a F10 Figure 10. Overvoltage Timing (Output Side) U The pull-up voltage on the RESET and FAULT pins follows VCC until the shunt regulator turns on. When the regulator is on the pull-up voltage is 14.4V. Undervoltage Monitor The LTC1642A will assert RESET if a monitored voltage falls below an adjustable minimum. When the monitored voltage has exceeded its minimum for at least one system timing cycle, RESET goes high. The monitoring circuitry comprises an internal 1.22V bandgap reference, an internal precision voltage comparator and an external resistive divider to monitor the output supply voltage. The circuit is shown in Figure 12, and typical waveforms in Figure 13. When the voltage at the FB pin rises above its reset threshold (1.22V), the comparator output goes low and a timing cycle starts (times 1 and 5). Following the cycle RESET is pulled high. At time 2 the voltage at FB drops below the comparator’s threshold and RESET is pulled low. If the FB pin rises above the reset threshold for less than a timing cycle the RESET output will remain low (time 3 to time 4). The 15µA pull-up current source to VCC on RESET has a series diode so the pin can be pulled above VCC by an external pull-up resistor without forcing current back into the supply. 70 60 50 40 30 20 10 0 0 40 80 120 160 OV OVERDRIVE (mV) 200 240 2V/DIV 20V/DIV 20V/DIV 2V/DIV 2V/DIV 20V/DIV 1642a F11 W U U Figure 11. OV Comparator Propagation Delay vs Overdrive Voltage 1642af 13 LTC1642A APPLICATIO S I FOR ATIO The undervoltage monitor behaves differently if FB is above its threshold when the GATE begins ramping: RESET goes high as soon as the GATE ramp begins. RESET goes low immediately if VCC falls below the chip’s 2.5V internal undervoltage lockout threshold. To disable the undervoltage monitor, tie FB to REF and ground RESET. VIN 12V 2.5A R2 0.015Ω 16 VCC 4 ON 15 SENSE GATE Q1 FDS6630A + R3 100Ω 14 R4 330Ω C2 0.047µF CLOAD LTC1642A 7 D1 1N4705 18V R9 95.3k 1% R8 12.4k 1% FB RESET RST TMR GND C1 0.33µF 3 8 5 1642a F12 ALL RESISTORS ± 5% UNLESS NOTED. FB COMPARATOR TRIPS AT VOUT = 10.7V Figure 12. Undervoltage Monitoring Circuitry 10.0 MINIMUM REF COMPENSATION (µF) 4.0 2.0 1.0 0.4 0.2 0.1 100µA Figure 14. Minimum REF Compensation vs REF Current 1642af 14 U Reference The LTC1642A’s internal voltage reference is buffered and brought out to the REF pin. The buffer amplifier should be compensated with a capacitor connected between REF and ground. If no DC current is drawn from REF, 0.1µF ensures an adequate phase margin, but the minimum compensation increases if REF sources a substantial DC current, as shown in Figure 14. VOUT t1 t2 t3 t4 t5 W U U VIN 20V/DIV VRSTTMR 1V/DIV VRESET 10V/DIV 250ms/DIV 1642a F13 Figure 13. Supply Monitor Waveforms 1mA REFERENCE CURRENT 10mA 1642a F14 LTC1642A APPLICATIO S I FOR ATIO Uncommitted Comparator The uncommitted comparator has an open drain output. The comparator has 3mV of hysteresis: the output goes high when the differential input voltage exceeds 1.5mV and goes low when the differential input is less than –1.5mV. The comparator’s input transistors are MOSFETs so the input bias and offset currents are very small: typically picoamps at 25°C, increasing to nanoamps at 90°C. If the auxilliary comparator is unused, the COMP +, COMP – and COMPOUT pins may be left floating. ILOAD SENSE RESISTOR, R2 TO SHORT VCC PIN SENSE VCC R6 R5 ILOAD GND ON Figure 15. Recommended Layout for R1, R2 and R5 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U Layout Considerations One ounce copper exhibits a sheet resistance of 530µΩ per square. To minimize self-heating, traces should be at least 0.02" wide per ampere of current and 0.03" is recommended. In high current applications, the voltage drop along traces can be appreciable. Connect the LTC1642A’s VCC and SENSE pins directly across sense resistor R2 to prevent the power trace’s resistance from adding to R2. It is also a good practice to keep the resistor divider to the ON pin close to the chip and the divider’s connections to the VCC and GND pins short. Figure 15 shows an example layout. R2 LT1642A 1642a F15 W U U 1642af 15 LTC1642A TYPICAL APPLICATIO InfiniBand BACKPLANE LONG VB_In R4 330Ω 5% C2 0.047µF 14 GATE COMPOUT RESET LTC1642A R11 12.4k 1% C7 0.01µF FB FAULT ON REF 13 C5 0.01µF C6 0.1µF LONG VB_Ret LOCAL POWER ENABLE 10k MODULE POWER *INSTALL D1 FOR AUTOMATIC RESTART IF USING D1, INCREASE C1 START-UP DELAY IS 20ms TYPICAL CIRCUIT-BREAKER DELAY IS 1ms TYPICAL † R5 SHORT 10.2k 1% VBxEn_L PACKAGE DESCRIPTIO .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) 0° – 8° TYP .0532 – .0688 (1.35 – 1.75) .008 – .012 (0.203 – 0.305) TYP NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER LTC1421 LTC4211 LT4250 LTC1643 DESCRIPTION Hot Swap Controller Hot Swap Controller with Multifunction Current Control Negative Voltage Hot Swap Controller in SO-8 PCI-Bus Hot Swap Controller COMMENTS Two Supplies from 3V to 12V and –12V Single Supply from 2.5V to 16.5V, MSOP Package – 48V Supplies, Active Current Limit 3.3V, 5V, ±12V Supplies for PCI Bus, Active Current Limit 1642af LT/TP 0605 500 • PRINTED IN USA 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U U 12V Hot Swap Circuit for InfiniBand Modules InfiniBand MODULE R2 Q1 DC/DC CONVERTER INPUT R6 127k 1% R12 84.5k 1% R3 100Ω D2 1N4705 18V 16 9 11 VCC OV COMP+ 15 SENSE R9 681k 1% 10 5 7 6 4 UV TO CONVERTER'S RUN/SS COMP– 12 CRWBR RST TMR BRK TMR 1 C1* 0.033µF C4 0.033µF 3 2 30k GND 8 D1* 1N4148 R8 100k 1% TO DC/DC RETURN R2 0.015Ω,5% 0.007Ω,5% (408) 822-2126 Q1 FDS6612† FDS6680† 1642a TA02 25W 50W FAIRCHILD GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .004 – .0098 (0.102 – 0.249) .009 (0.229) REF 16 15 14 13 12 11 10 9 .045 ± .005 .0250 (0.635) BSC .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .254 MIN .150 – .165 1 23 4 56 7 8 .0165 ± .0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT GN16 (SSOP) 0204 www.linear.com © LINEAR TECHNOLOGY CORPORATION 1999