1664

LTC1664 Micropower Quad 10-Bit DAC FEATURES s s DESCRIPTIO s s s s s s s Tiny: 4 DACs in the Board Space of an SO-8 Micropower: 59µA per DAC Plus 1µA Sleep Mode for Extended Battery Life Wide 2.7V to 5.5V Supply Range Rail-to-Rail Voltage Outputs Drive 1000pF Reference Range Includes Supply for Ratiometric 0V-to-VCC Output Reference Input Impedance is Code-Independent —Eliminates External Reference Buffer Individually Addressable DACs Differential Nonlinearity: ≤ ±0.75LSB Max Pin-Compatible Octal Version Available (LTC1660) The LTC®1664 integrates four accurate, serially addressable 10-bit digital-to-analog converters (DACs) in a tiny 16-pin Narrow SSOP package. Each buffered DAC draws just 59µA total supply current, yet is capable of supplying DC output currents in excess of 5mA and reliably driving capacitive loads of up to 1000pF. Sleep mode further reduces total supply current to 1µA. Linear Technology’s proprietary, inherently monotonic voltage interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. Ultralow supply current, power-saving Sleep mode and extremely compact size make the LTC1664 ideal for battery-powered applications, while its ease of use, high performance and wide supply range make it an excellent choice as a general-purpose converter. , LTC and LT are registered trademarks of Linear Technology Corporation. APPLICATIO S s s s s s Mobile Communications Remote Industrial Devices Automatic Calibration for Manufacturing Portable Battery-Powered Instruments Trim/Adjust Applications BLOCK DIAGRA GND 1 10-BIT DAC A 16 VCC 10-BIT DAC D 5 VOUT D 1.0 0.8 0.6 VCC = 5V VREF = 4.096V VOUT A 2 VOUT B 3 10-BIT DAC B 10-BIT DAC C 4 VOUT C LSB 0.4 0.2 0 –0.2 CONTROL LOGIC REF CS/LD SCK 6 7 8 ADDRESS DECODER 11 10 9 CLR DOUT DIN 1664 BD –0.4 –0.6 –0.8 SHIFT REGISTER –1.0 0 256 512 CODE 768 1023 1664 G08 U Differential Nonlinearity (DNL) W U 1 LTC1664 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW GND VOUT A VOUT B VOUT C VOUT D REF CS/LD SCK 1 2 3 4 5 6 7 8 16 VCC 15 NC 14 NC 13 NC 12 NC 11 CLR 10 DOUT 9 DIN VCC to GND .............................................. – 0.3V to 7.5V Logic Inputs to GND ................................ – 0.3V to 7.5V VOUT A, VOUT B…VOUT D, REF to GND ................................. – 0.3V to (VCC + 0.3V) Maximum Junction Temperature ......................... 125°C Operating Temperature Range LTC1664C ............................................. 0°C to 70°C LTC1664I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................ 300°C ORDER PART NUMBER LTC1664CGN LTC1664CN LTC1664IGN LTC1664IN GN PACKAGE 16-LEAD PLASTIC SSOP N PACKAGE 16-LEAD PDIP GN PART MARKING 1664 1664I TJMAX = 125°C, θJA = 150°C/W (GN) TJMAX = 125°C, θJA = 100°C/W (N) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL Accuracy Resolution Monotonicity DNL INL VOS FSE PSR Differential Nonlinearity Integral Nonlinearity Offset Error VOS Temperature Coefficient Full-Scale Error Full-Scale Error Temperature Coefficient Power Supply Rejection Input Voltage Range Resistance Capacitance IREF VCC ICC Reference Current Positive Supply Voltage Supply Current VCC = 5V (Note 3) VCC = 3V (Note 3) Sleep Mode (Note 3) Sleep Mode q q PARAMETER CONDITONS MIN 10 10 TYP MAX UNITS Bits Bits (Notes 2, 4) (Notes 2, 4) (Notes 2, 4) (Note 7) VCC = 5V, VREF = 4.096V (Note 4) VREF = 2.5V q q q q q q q ± 0.2 ± 0.6 ± 10 ± 15 ±3 ± 30 0.18 ± 0.75 ± 2.5 ± 30 ± 15 µV/°C LSB µV/°C LSB/V VCC V kΩ pF 1 5.5 µA V µA µA µA Reference Input q 0 70 130 12 0.001 2.7 236 186 1 Not in Sleep Mode q Power Supply q q q q 380 290 3 2 U LSB LSB mV W U U WW W LTC1664 ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER Short-Circuit Current Low Short-Circuit Current High AC Performance Voltage Output Slew Rate Voltage Output Settling Time Capacitive Load Driving Digital I/O VIH VIL VOH VOL ILK CIN Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance VCC = 2.7V to 5.5V VCC = 2.7V to 3.6V VCC = 4.5V to 5.5V VCC = 2.7V to 5.5V IOUT = – 1mA, DOUT Only IOUT = 1mA, DOUT Only VIN = GND to VCC q q q q q q q CONDITIONS VOUT = 0V, VCC = 5.5V, VREF = 5.1V, Code = 1023 (Note 9) VOUT = VCC = 5.5V, VREF = 5.1V, Code = 0 (Note 9) Rising (Notes 4, 5) Falling (Notes 4, 5) Rising 0.1VFS to 0.9VFS ± 0.5LSB (Notes 4, 5) Falling 0.9VFS to 0.1VFS ± 0.5LSB (Notes 4, 5) q q MIN 10 10 TYP 30 27 0.60 0.25 6 19 1000 MAX 100 120 UNITS mA mA V/µs V/µs µs µs pF V V DC Performance 2.4 2.0 0.8 0.6 VCC – 1 0.4 0.05 2 ± 10 V V V V µA pF TI I G CHARACTERISTICS SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 PARAMETER DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High DOUT Propagation Delay SCK Low to CS/LD Low CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency VCC = 2.7V to 5.5V t1 t2 t3 t4 DIN Valid to SCK Setup DIN Valid to SCK Hold SCK High Time SCK Low Time VCC = 4.5V to 5.5V The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) CONDITIONS q q UW MIN 40 0 30 30 80 30 80 5 20 100 30 TYP 15 –11 5 7 30 4 26 26 0 37 0 MAX UNITS ns ns ns ns ns ns ns (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) CLOAD = 15pF (Note 6) (Note 6) (Note 6) (Note 6) (Notes 6 and 8) (Note 6) (Note 6) (Note 6) (Note 6) q q q q q q q q q q 80 ns ns ns ns 16.7 60 0 50 50 20 –14 8 12 MHz ns ns ns ns q q q q 3 LTC1664 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) SYMBOL t5 t6 t7 t8 t9 t10 t11 PARAMETER CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK High DOUT Propagation Delay SCK Low to CS/LD Low CLR Pulse Width CS/LD High to SCK Positive Edge SCK Frequency CONDITIONS (Note 6) (Note 6) (Note 6) CLOAD = 15pF (Note 6) (Note 6) (Note 6) (Note 6) (Notes 6 and 8) q q q q q q q q TI I G CHARACTERISTICS Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V, VREF = 4.096V, from code 20 to code 1023. See Rail-to-Rail output considerations. Note 3: Digital inputs at 0V or VCC. Note 4: Load is 10kΩ in parallel with 100pF. TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity (INL) 2.5 2.0 1.5 1.0 0.5 LSB VCC = 5V VREF = 4.096V SUPPLY CURENT (µA) 0 – 0.5 –1.0 –1.5 – 2.0 – 2.5 0 256 512 CODE 768 1023 1664 G07 LSB 4 UW UW MIN 100 50 100 5 30 120 30 TYP 30 5 27 47 0 41 0 MAX UNITS ns ns ns 150 ns ns ns ns 10 MHz Note 5: VCC = VREF = 5V. Note 6: Guaranteed by design and not subject to test. Note 7: Measured at code 20. Note 8: If a continuous clock is used, CS/LD timing (t7 and t9) will limit the maximum clock frequency to 5MHz at 4.5V to 5.5V(3.85MHz at 2.7V to 5.5V). Note 9: Any output shorted. Differential Nonlinearity (DNL) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 256 512 CODE 768 1023 1664 G08 Supply Current vs Temperature 300 VREF = VCC CODE = 1023 VCC = 5.5V VCC = 4.5V VCC = 3.6V VCC = 5V VREF = 4.096V 280 260 240 220 200 180 VCC = 2.7V 160 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 1664 G11 LTC1664 TYPICAL PERFOR A CE CHARACTERISTICS Load Regulation vs Output Current 2 1.5 1 ∆VOUT (LSB) ∆VOUT (LSB) VCC = VREF = 5V CODE = 512 0 –0.5 –1 –1.5 –2 –2 SOURCE –1 0 IOUT (mA) SINK 1 2 1664 G09 0 –0.5 –1 –1.5 –2 –500 SOURCE 0 IOUT (µA) SINK VOUT (V) 0.5 Midscale Output Voltage vs Load Current 3 2.9 2.8 2.7 VOUT (V) VREF = VCC CODE = 512 VCC = 5.5V VOUT (V) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 VCC = 3.6V VCC = 3V SUPPLY CURRENT (mA) 2.6 2.5 2.4 2.3 2.2 2.1 2 –30 –20 SOURCE –10 SINK 20 30 1664 G01 VCC = 5V VCC = 4.5V 0 10 IOUT (mA) Minimum VOUT vs Load Current (Output Sinking) 1400 1200 1000 800 600 –55°C 400 200 0 0 2 VCC = 5V CODE = 0 1400 125°C 1200 1000 VCC – VOUT (mV) VOUT (mV) UW | | Load Regulation vs Output Current 2 1.5 1 0.5 3 Large-Signal Step Response 5 VCC = VREF = 5V 10% TO 90% STEP VCC = VREF = 3V CODE = 512 4 2 1 0 500 1664 G10 0 20 40 60 TIME (µs) 80 100 1664 G05 Midscale Output Voltage vs Load Current 2 1.9 1.8 VREF = VCC CODE = 512 1.2 1.0 0.8 0.6 0.4 0.2 SOURCE –8 SINK 8 12 15 1664 G02 Supply Current vs Logic Input Voltage ALL DIGITAL INPUTS SHORTED TOGETHER VCC = 2.7V 1 –15 –12 –4 0 4 IOUT (mA) 0 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 5 1664 G12 Minimum Supply Headroom vs Load Current (Output Sourcing) VREF = 4.096V ∆VOUT < 1LSB CODE = 1023 125°C 25°C –55°C 400 200 0 25°C 800 600 4 6 IOUT (mA) (Sinking) 8 10 1664 G04 0 2 |IOUT| (mA) (Sourcing) 4 6 8 10 1664 G03 5 LTC1664 PIN FUNCTIONS GND (Pin 1): System Ground. VOUT A to VOUT D (Pins 2–5): DAC Analog Voltage Outputs. The output range is  1023  0 to  V  1024  REF REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC. CS/LD (Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on DIN into the register. When CS/LD is pulled high, SCK is disabled and data is loaded from the shift register into the specified DAC register(s), updating the analog output(s). CMOS and TTL compatible. SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 9): Serial Interface Data Input. Data on the DIN pin is shifted into the 16-bit register on the rising edge of SCK. CMOS and TTL compatible. DOUT (Pin 10): Serial Interface Data Output. Data appears on DOUT 16 positive SCK edges after being applied to DIN. May be tied to DIN of another serial device for daisy-chain operaton. CMOS and TTL compatible. CLR (Pin 11): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible. NC (Pins 12–15): Make no electrical connection to these pins. VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V. 6 U U U LTC1664 BLOCK DIAGRA VOUT A VOUT B TI I G DIAGRA SCK t9 DIN t5 CS/LD DOUT W W GND 1 10-BIT DAC A 10-BIT DAC D 16 VCC 5 VOUT D 2 3 10-BIT DAC B 10-BIT DAC C 4 VOUT C CONTROL LOGIC REF CS/LD SCK 6 7 8 ADDRESS DECODER 11 10 9 CLR DOUT DIN 1664 BD SHIFT REGISTER UW t1 t2 t3 t4 t6 t11 A3 t7 A2 A1 X1 X0 t8 A3 A2 A1 X1 X0 A3 1664 F01 Figure 1 7 LTC1664 OPERATIO Transfer Function The transfer function is k VOUT(IDEAL) =  V  1024  REF where k is the decimal equivalent of the binary DAC input code and VREF is the voltage at REF (Pin 6). Power-On Reset The LTC1664 clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range – 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. If it is not possible to sequence the supplies, connect a Schottky diode from REF (anode) to VCC (cathode). Serial Interface Referring to Figure 2: With CS/LD held low, data on the D IN input is shifted into the 16-bit shift register on the positive edge of SCK. The 4-bit DAC address, A3-A0, is loaded first (see Table 2), then the 10-bit input code, D9-D0, ordered MSB-to-LSB in each case. Two don’t-care bits, X1-X0, are loaded last. When the full 16-bit input word has been shifted in, CS/LD is pulled high, loading the DAC register with the word and causing the addressed DAC output(s) to update. The clock is disabled internally when CS/LD is high. Note: SCK must be low before CS/LD is pulled low. 8 U The buffered serial output of the shift register is available on the DOUT pin, which swings from GND to VCC. Data appears on DOUT 16 positive SCK edges after being applied to DIN. Multiple LTC1664’s can be controlled from a single 3-wire serial port (i.e., SCK, DIN and CS/LD) by using the included “daisy-chain” facility. A series of m chips is configured by connecting each DOUT (except the last) to DIN of the next chip, forming a single 16m-bit shift register. The SCK and CS/LD signals are common to all chips in the chain. In use, CS/LD is held low while m 16-bit words are clocked to DIN of the first chip; CS/LD is then pulled high, updating all of them simultaneously. Sleep Mode DAC address 1110b is reserved for the special Sleep instruction (see Table 2). In this mode, the digital interface stays active while the analog circuits are disabled; static power consumption is thus virtually eliminated. The reference input and analog outputs are set in a high impedance state and all DAC settings are retained in memory so that when Sleep mode is exited, the outputs of DACs not updated by the Wake command are restored to their last active state. Sleep mode is initiated by performing a load sequence to address 1110b (the DAC input word D9-D0 is ignored). Once in Sleep mode, a load sequence to any other address (including “No Change” address 0000b) causes the LTC1664 to Wake. It is possible to keep one or more chips of a daisy chain in continuous Sleep mode by giving the Sleep instruction to these chips each time the active chips in the chain are updated. Table 1. LTC1664 Input Word A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 Address/Control Input Code Don’t Care LTC1664 OPERATIO SCK DIN CS/LD (ENABLE SCK) DOUT U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 ADDRESS/CONTROL INPUT CODE INPUT WORD W0 (UPDATE OUTPUT) DON’T CARE A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0 A3 INPUT WORD W–1 INPUT WORD W0 1664 F02 Figure 2. LTC1664 Register Loading Sequence Table 2. DAC Address/Control Functions ADDRESS/CONTROL A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC STATUS No Change Load DAC A Load DAC B Load DAC C Load DAC D Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved No Change Load ALL DACs with Same 10-Bit Code Sleep Wake SLEEP STATUS Wake Wake Wake Wake Wake 9 LTC1664 OPERATIO Voltage Outputs Each of the four rail-to-rail output amplifiers contained in the LTC1664 can source or sink up to 5mA. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 85Ω when driving a load to the rails. The output amplifiers are stable driving capacitive loads of up to 1000pF. A small resistor placed in series with the output can be used to achieve stability for any load capacitance. A 1µF load can be successfully driven by inserting a 20Ω resistor; a 2.2µF load needs only a 10Ω resistor. In either case, larger values of resistance, capacitance or both may be safely substituted for the values given. 10 U Rail-to-Rail Output Considerations In any rail-to-rail voltage output DAC, the output is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. LTC1664 OPERATIO OUTPUT VOLTAGE 0V NEGATIVE OFFSET INPUT CODE (b) 1665/60 F03 Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC U VREF = VCC POSITIVE FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 512 INPUT CODE (a) 1023 11 LTC1664 TYPICAL APPLICATIONS A Low Power Dual Trim Circuit with Coarse/Fine Adjustment R1 3.3V 110Ω 0.1µF 8 2 R2 11k 0.1µF U1 LTC1664 VCC GND R1 110Ω COARSE VOUT A 1 VOUT1 U2A LT®1490 4 2 DAC A DAC D 5 0.1µF 3.3V 2 LTC1258-2.5 4 1 0.1µF R2 11k FINE VOUT B 3 DAC B DAC C 4 VOUT C R2 11k FINE 0.1µF REF 6 CONTROL LOGIC ADDRESS DECODER 11 CLR CS/LD 7 10 DOUT TO OTHER LTC1664s 3-WIRE SERIAL INTERFACE SCK 8 SHIFT REGISTER 9 DIN 1664 TA01 VOUT 1 = VREF CODE A + R1 CODE B 1024 R2 1024 = 2.5V CODE A + 1 CODE B 1024 100 1024 VOUT 2 = VREF CODE D + R1 CODE C 1024 R2 1024 = 2.5V CODE D + 1 CODE C 1024 100 1024 ) ) ) ) ) ) ) ) 12 + 3 VOUT D R1 110Ω COARSE 5 – 1 U 3.3V R2 11k 6 R1 110Ω 16 – + U2B LT1490 7 VOUT2 LTC1664 TYPICAL APPLICATIONS A 4-Channel Bipolar Output Voltage Circuit Configuration R 0.1µF VS+ 4 VOUT A ′ 1 0.1µF 11 VS– R 6 U2A LT1491 R 0.1µF U1 LTC1664 VCC ± 5V 2 DAC A DAC D 5 R R 9 VOUT B ′ 7 ± 5V U2B LT1491 3 DAC B DAC C 4 REF 6 CONTROL LOGIC ADDRESS DECODER 11 CLR CS/LD 7 10 DOUT DIN 3-WIRE SERIAL INTERFACE CLK 8 SHIFT REGISTER 9 1664 TA02 + 5 VOUT B VOUT C 10 + 3 VOUT A VOUT D 12 – 2 GND – U 5V R R 1 16 13 – – + + U2D LT1491 14 VOUT D′ ± 5V R U2C LT1491 8 VOUT C′ ± 5V CODE VOUT X – 5V 0 0V 512 1023 +4.99V 13 LTC1664 PACKAGE DESCRIPTION 0.007 – 0.0098 (0.178 – 0.249) 0.016 – 0.050 (0.406 – 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 14 U Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0° – 8° TYP 0.053 – 0.068 (1.351 – 1.727) 23 4 56 7 8 0.004 – 0.0098 (0.102 – 0.249) 0.008 – 0.012 (0.203 – 0.305) 0.0250 (0.635) BSC GN16 (SSOP) 1098 LTC1664 PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.770* (19.558) MAX 16 15 14 13 12 11 10 9 0.255 ± 0.015* (6.477 ± 0.381) 1 2 3 4 5 6 7 8 0.300 – 0.325 (7.620 – 8.255) 0.130 ± 0.005 (3.302 ± 0.127) 0.020 (0.508) MIN 0.045 – 0.065 (1.143 – 1.651) 0.009 – 0.015 (0.229 – 0.381) 0.065 (1.651) TYP 0.125 (3.175) MIN 0.018 ± 0.003 (0.457 ± 0.076) ( +0.035 0.325 –0.015 8.255 +0.889 –0.381 ) 0.100 (2.54) BSC *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) N16 1098 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1664 TYPICAL APPLICATION An 11-Bit Pin Driver VH and VL Adjustment Circuit for ATE Applications 5V 0.1µF 11 CLR 16 VCC U1 LTC1664 DAC A DAC B DAC C DAC D CS/LD DIN SCK 7 9 8 GND 1 RELATED PARTS PART NUMBER LTC1665/LTC1660 LTC1661 LTC1662 LTC1663 LTC1446/LTC1446L LTC1448 LTC1454/LTC1454L LTC1458/LTC1458L LT1460 LTC1590 LTC1654 LTC1659 DESCRIPTION Octal 8/10-Bit VOUT DAC in 16-Pin Narrow SSOP Dual 10-Bit VOUT DAC in 8-Pin MSOP Package Ultra Low Power Dual 10-Bit VOUT DAC in 8-Pin MSOP Package Single 10-Bit VOUT DAC with 2-Wire Interface in SOT-23 Package Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference Dual 12-Bit VOUT DAC in SO-8 Package Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Micropower Precision Series Reference, 2.5V, 5V, 10V Versions Dual 12-Bit IOUT DAC in SO-16 Package Dual 14-Bit DAC in SO-8 Footprint Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package VCC: 2.7V to 5.5V COMMENTS VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, 1.5µA per DAC, Rail-to-Rail Output VCC = 2.7V to 5.5V, Internal Reference, 60µA LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 0.075% Max, 10ppm/°C Max, Only 130µA Supply Current VCC = 4.5V to 5.5V, 4-Quadrant Multiplication 1LBS DNL, Selectable Speed/Power Low Power Multiplying VOUT DAC. Output Swings from GND to REF. REF Input Can Be Tied to VCC 1664f LT/TP 0700 4K • PRINTED IN THE USA 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U 6 REF VH (FROM MAIN DAC) RG VA 50k RF 5k 3 10V 8 0.1µF VH′ VL′ 2 + U2A LT1368 1 VH′ = VH + ∆VH 0.1µF 2 RG VB 50k – 4 – 5V 0.1µF RF 5k 3 VL (FROM MAIN DAC) RG VC 50k RF 5k 5 VH VL VOUT 4 + U2B LT1368 7 VL′ = VL + ∆VL 0.1µF PIN DRIVER 6 RG VD 50k – RF 5k LOGIC DRIVE 1664 TA03 5 CODE A CODE B 1023 1023 1023 512 1023 0 512 1023 512 512 512 0 0 1023 0 512 0 0 ∆VH, ∆VL 0 + 250mV +500mV – 250mV 0 + 250mV –500mV –250mV 0 VA = VC = 2.5V VH′ = VH + RF (V – V ) B RG A VL′ = VL + RF (V – V ) D RG C For Resistor Values Shown: Adjustment Range = ±500mV Adjustment Step Size = 500µV © LINEAR TECHNOLOGY CORPORATION 2000