LTC1879

LTC1879 1.2A Synchronous Step-Down Regulator with 15µA Quiescent Current FEATURES s s s s s s s s s s DESCRIPTIO s s s s High Efficiency: Up to 95% Low Quiescent Current: Only 15µA with No Load 550kHz Constant Frequency Operation 2.65V to 10V Input Voltage Range VOUT from 0.8V to VIN, IOUT to 1.2A True PLL Frequency Locking from 350kHz to 750kHz Power Good Output Voltage Monitor Low Dropout Operation: 100% Duty Cycle Burst Mode® or Pulse Skipping Operation Current Mode Operation for Excellent Line and Load Transient Response Shutdown Mode Draws < 1µA Supply Current ± 2% Output Voltage Accuracy Overcurrent and Overtemperature Protected Available in 16-Lead SSOP Package The LTC®1879 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. Operating supply current is only 15µA with no load and drops to < 1µA in shutdown. The input supply voltage range of 2.65V to 10V makes the LTC1879 ideally suited for both single and dual Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. The switching frequency is internally set to 550kHz, allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC1879 can be externally synchronized from 350kHz to 750kHz. Burst Mode operation is inhibited during synchronization or when the SYNC/MODE pin is pulled low. The internal synchronous rectifier switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with a 0.8V feedback reference voltage. The LTC1879 is available in a 16-lead SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. APPLICATIO S s s s Cellular Telephones Portable Computers Wireless Modems TYPICAL APPLICATIO VIN 2.65V TO 10V CIN 10µF 2 15 High Efficiency Step-Down Converter 13 SVIN RUN/SS PVIN 8, 9 5, 12 L1 6.2µH Efficiency vs Output Load Current 100 90 80 VIN = 3.6V EFFICIENCY (%) SYNC/MODE SWP LTC1879 14 6, 11 PGOOD SWN 150k 47pF 220pF SGND 1 4 ITH PGND VFB 7, 10 3 70 VIN = 10V 60 50 40 Burst Mode OPERATION VOUT = 3.1V L = 6.2µH 1 10 100 OUPUT CURRENT (mA) 1000 1879 TA01b VOUT* 3.1V COUT 47µF 28.0k 80.6k 30 0.1 1879 TA01a CIN: TAIYO YUDEN CERAMIC LMK325BJ106MN COUT: TDK CERAMIC C4532X5ROJ476M L1: TOKO A921CY6R2M *VOUT CONNECTED TO VIN (MINUS SWITCH AND L1 VOLTAGE DROP) FOR 2.65V < VIN < 3.1V U VIN = 7.2V 1879f U U 1 LTC1879 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW SGND 1 RUN/SS 2 VFB 3 ITH 4 SWP1 5 SWN1 6 PGND1 7 PVIN1 8 16 PLL_LPF 15 SYNC/MODE 14 PGOOD 13 SVIN 12 SWP2 11 SWN2 10 PGND2 9 PVIN2 Input Supply Voltage ................................ – 0.3V to 11V ITH, PLL_LPF Voltages ............................. – 0.3V to 2.7V RUN/SS, VFB Voltages ............................... – 0.3V to VIN SYNC/MODE Voltage ................................. – 0.3V to VIN (VPVIN – VSWP) Voltage ............................. – 0.3V to 11V VSWN Voltage ............................................ – 0.3V to 11V P-Channel Switch Source Current (DC) .................... 2A N-Channel Switch Sink Current (DC) ........................ 2A Peak Switching Sink and Source Current ................. 3A Operating Ambient Temperature Range (Note 2) ............................................. – 40°C to 85°C Junction Temperature (Notes 3, 6) ...................... 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC1879EGN GN PART MARKING 1879 GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 140°C/ W, θJC = 40°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 5V unless otherwise noted. SYMBOL IVFB VFB ∆VOVL ∆VUVL ∆VFB/VFB VLOADREG VIN IQ PARAMETER Feedback Current Regulated Output Voltage Overvoltage Trip Limit with Respect to VFB Reference Voltage Line Regulation Output Voltage Load Regulation Input Voltage Range Input DC Bias Current Pulse Skipping Mode Burst Mode Operation Shutdown SYNC Capture Range Oscillator Frequency Phase Detector Output Current Sinking Capability Sourcing Capability RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET Peak Inductor Current SW Leakage SYNC/MODE Leakage Current VFB ≥ 0.7V VFB = 0V fPLLIN < fOSC fPPLIN > fSOC ISW = 100mA, VIN = 5V ISW = – 100mA, VIN = 5V VFB = 0.7V, Duty Cycle < 35%, VIN = 5V VRUN = 0V, VSW = 0V or 10V, VIN = 10V q q q CONDITIONS (Note 4) (Note 4) 0°C ≤ TA ≤ 85°C (Note 4) – 40°C ≤ TA ≤ 85°C ∆VOVL = VOVL – VFB VIN = 2.65V to 10V (Note 4) Measured in Servo Loop, VITH = 0.9V to 1.2V Measured in Servo Loop, VITH = 1.6V to 1.2V (Note 5) 2.65V < VIN < 10V, VSYNC/MODE = 0V, IOUT = 0A VSYNC/MODE = VIN, IOUT = 0A VRUN = 0V, VIN = 10V q q q q q q q MIN 0.784 0.740 20 20 TYP 8 0.80 0.80 60 60 0.05 0.1 – 0.1 MAX 60 0.816 0.840 110 110 0.25 0.6 – 0.6 10 UNITS nA V V mV mV %/V % % V µA µA µA kHz kHz kHz µA µA Ω Ω A µA V µA 1879f Undervoltage Trip Limit with Respect to VFB ∆VUVL = VFB – VUVL 2.65 270 15 0 350 495 550 80 10 – 10 0.35 0.37 1.8 0.2 2.2 ± 0.01 1.0 ± 0.01 365 22 1 750 605 fSYNC fOSC IPLLLPF 3 –3 20 – 20 0.45 0.5 2.7 ± 2.5 1.5 ±1 RPFET RNFET IPK ILSW ISYNC/MODE VSYNC/MODE SYNC/MODE Threshold 2 U W U U WW W LTC1879 ELECTRICAL CHARACTERISTICS SYMBOL VRUN IRUN PARAMETER RUN Threshold RUN Input Current The q denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 5V unless otherwise noted. CONDITIONS VRUN Ramping Up VRUN = 0V q MIN 0.2 TYP 0.7 ± 0.01 MAX 1.5 ±1 UNITS V µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1879E is guaranteed to meet specified performance from 0°C to 70°C. Specifications over the – 40°C to 85°C operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC1879: TJ = TA + (PD × 140°C/W) Note 4: The LTC1879 is tested in a feedback loop which servos VFB to the balance point for the error amplifier (VITH = 1.2V) Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFOR A CE CHARACTERISTICS RDS(ON) vs Temperature 0.7 0.6 0.5 RDS(ON) (Ω) 0.4 0.3 0.2 0.1 0 –50 495 –50 VIN = 10V VIN = 5V SYNCHRONOUS SWITCH MAIN SWITCH VIN = 5V FREQUENCY (kHz) VIN = 10V 575 595 OSCILLATOR FREQUENCY (kHz) –25 0 25 50 75 TEMPERATURE (°C) 100 125 –25 0 25 50 75 TEMPERATURE (°C) DC Supply Current vs Temperature 300 VIN = 5V 250 300 250 DC SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) PULSE SKIPPING MODE 200 150 100 50 Burst Mode OPERATON 0 –50 150 100 50 Burst Mode OPERATION 0 RDS(ON) (Ω) 0 50 TEMPERATURE (°C) UW 100 1879 G01 Oscillator Frequency vs Temperature VIN = 5V 600 590 580 570 560 550 540 530 520 510 500 125 Oscillator Frequency vs Supply Voltage 555 535 515 2 4 6 8 SUPPLY VOLTAGE (V) 10 1879 G03 1879 G02 DC Supply Current vs Input Voltage 0.6 0.5 PULSE SKIPPING MODE 200 0.4 0.3 0.2 0.1 0 RDS(ON) vs Input Voltage SYNCHRONOUS SWITCH MAIN SWITCH 100 125 0 2 4 6 INPUT VOLTAGE (V) 8 10 1879 G05 2 3 4 8 7 6 5 INPUT VOLTAGE (V) 9 10 1879 G04 1879 G06 1879f 3 LTC1879 TYPICAL PERFOR A CE CHARACTERISTICS Switch Leakage vs Temperature 20 18 16 VIN = 10V 50 45 40 SWITCH LEAKAGE (µA) SWITCH LEAKAGE (nA) OUTPUT VOLTAGE (V) 14 12 10 8 6 4 2 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 SYNCHRONOUS SWITCH MAIN SWITCH Reference Voltage vs Temperature 804 803 REFERENCE VOLTAGE (mV) 802 EFFICIENCY (%) VIN = 6V EFFICIENCY (%) 801 800 799 798 797 796 795 794 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 Efficiency vs Output Current 100 90 80 VIN = 7.2V VIN = 4.2V EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 EFFICIENCY (%) 4 UW 1879 G07 Switch Leakage vs Input Voltage 2.51 RUN = 0V TA = 25°C 2.50 2.49 2.48 2.47 2.46 2.45 2.44 2.43 2.42 SYNCHRONOUS SWITCH 0 2 6 4 INPUT VOLTAGE (V) 8 10 1879 G08 Output Voltage vs Load Current 35 30 25 20 15 10 5 0 MAIN SWITCH 2.41 0 PULSE SKIPPING MODE VIN = 5V L = 6.2µH 200 400 600 800 1000 1200 1400 1600 LOAD CURRENT (mA) 1879 G09 Efficiency vs Output Current 100 90 80 70 60 50 40 30 0.1 VIN = 10V VOUT = 1.8V L = 6.2µH Burst Mode OPERATION 10 100 1 OUTPUT CURRENT (mA) 1000 1879 G11 Efficiency vs Output Current 100 90 80 VIN = 3.6V VIN = 3.6V VIN = 5V VIN = 7.2V VIN = 5V 70 VIN = 7.2V 60 VIN = 10V 50 40 30 0.1 VOUT = 2.5V L = 6.2µH Burst Mode OPERATION 10 100 1 OUTPUT CURRENT (mA) 1000 1879 G12 1879 G10 Efficiency vs Input Voltage 100 100mA 90 1mA 80 70 60 50 10mA VIN = 4.2V VIN = 7.2V 0.1mA VOUT = 3.1V L = 6.2µH Burst Mode OPERATION PULSE SKIPPING MODE 1 10 100 OUTPUT CURRENT (mA) 1000 1879 G13 40 30 2 VOUT = 2.5V L = 6.2µH Burst Mode OPERATION 4 6 INPUT VOLTAGE (V) 1879 G14 8 10 1879f LTC1879 TYPICAL PERFOR A CE CHARACTERISTICS Load Step (Burst Mode Operation) IL 1A/DIV IL 1A/DIV IVIN 500mA/DIV RUN/SS 1V/DIV VOUT 100mV/DIV VIN = 5V VOUT = 2.5V L = 4.7µH 50µs/DIV CIN = 20µF COUT = 47µF ILOAD = 50mA to 1200mA Burst Mode Operation IL 200mA/DIV IL 200mA/DIV VOUT 20mV/DIV VOUT 50mV/DIV SW 5V/DIV 25µs/DIV CIN = 20µF COUT = 47µF ILOAD = 15mA VIN = 5V VOUT = 2.5V L = 4.7µH UW Load Step (Pulse Skipping Mode) Soft-Start with Shorted Output VOUT 100mV/DIV 1879 G15 VIN = 5V VOUT = 2.5V L = 4.7µH 50µs/DIV CIN = 20µF COUT = 47µF ILOAD = 50mA to 1200mA 1879 G16 VIN = 5V VOUT = 0V L = 4.7µH 5ms/DIV CIN = 20µF COUT = 47µF ILOAD = 0A 1879 G19 Pulse Skipping Mode Operation SW 5V/DIV 2.5µs/DIV CIN = 20µF COUT = 47µF ILOAD = 15mA 1879 G18 1879 G17 VIN = 5V VOUT = 2.5V L = 4.7µH 1879f 5 LTC1879 PI FU CTIO S SGND (Pin 1): Signal Ground Pin. RUN/SS (Pin 2): Combination of Soft-Start and Run Control Inputs. Forcing this pin below 0.7V shuts down the device. In shutdown all functions are disabled and device draws zero supply current. For the proper operation of the part, force this pin above 2.5V. Do not leave this pin floating. Soft-start can be accomplished by raising the voltage on this pin gradually with an RC circuit. VFB (Pin 3): Feedback Pin. Receives the feedback voltage from an external resistor divider across the output. ITH (Pin 4): Error Amplifier Compensation Point. The current output increases with this control voltage. Nominal voltage range for this pin is 0.5V to 1.8V. SWP1, SWP2 (Pins 5, 12): Upper Switch Nodes. These pins connect to the drains of the internal main PMOS switches and should always be connected together externally. SWN1, SWN2 (Pins 6, 11): Lower Switch Nodes. These pins connect to the drains of the internal synchronous NMOS switches and should always be connected together externally. PGND1, PGND2 (Pins 7, 10): Power Ground Pins. Ground pins for the internal drivers and switches. These pins should always be tied together. PVIN1, PVIN2 (Pins 8, 9): Power Supply Pins for the Internal Drivers and Switches. These pins should always be tied together. SVIN (Pin 13): Signal Power Supply Pin. PGOOD (Pin 14): Power Good Indicator Pin. Power good is an open-drain logic output. The PGOOD pin is pulled to ground when the voltage on the VFB pin is not within ± 7.5% of its nominally regulated potential. This pin requires a pull-up resistor for power good indication. Power good indication works in all modes of operation. SYNC/MODE (Pin 15): External Clock Synchronization and Mode Select Input. To synchronize, apply an external clock with a frequency between 350kHz and 750kHz. To select Burst Mode operation, tie pin to SVIN. Grounding this pin selects pulse skipping mode. Do not leave this pin floating. PLL_LPF (Pin 16): Output of the Phase Detector and Control Input of Oscillator. Connect a series RC lowpass network from this pin to ground if externally synchronized. If unused, this pin may be left open. 6 U U U 1879f BURST DEFEAT Y X Y = “0” ONLY WHEN X IS A CONSTANT “1” BLOCK DIAGRA 16 SLOPE COMP 0.8V OSC PLL_LPF SVIN 13 SYNC/MODE VCO AND OSC EA BURST SLEEP SVIN ITH 4 RS LATCH R Q S Q SWITCHING LOGIC AND BLANKING CIRCUIT – THERMAL SHUTDOWN SVIN OV 0.86V OVDET + BOTTOM MOSFET RUN/SS 2 0.8V REF – SOFT-START – 0.74V UVDET + + 0.8V 0.45V + – – + + 3 EN SLEEP VFB – 0.6V FREQ SHIFT – ICOMP + PVIN 8, 9 2.9Ω TOP MOSFET ANTISHOOTTHROUGH SWP 5, 12 SWN 6, 11 SHUTDOWN + RCMP PGND – 14 PGOOD 1879 BD 7, 10 1 SGND W LTC1879 15 7 1879f LTC1879 OPERATIO Main Control Loop The LTC1879 uses a constant frequency, current mode step-down architecture. Both the top MOSFET and synchronous bottom MOSFET switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP turns the top MOSFET off is controlled by the voltage on the ITH pin, which is the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage, VFB, relative to the 0.8V internal reference, which, in turn, causes the ITH voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse direction or the next clock cycle begins. Comparator OVDET guards against transient overshoots > 7.5% by turning the main switch off and keeping it off until the fault is removed. Burst Mode Operation The LTC1879 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. To enable Burst Mode operation, simply tie the SYNC/MODE pin to SVIN or connect it to a logic high (VSYNC/MODE > 1.5V). To disable Burst Mode operation and enable PWM pulse skipping mode, connect the SYNC/ MODE pin to SGND. In this mode, the efficiency is lower at light loads but becomes comparable to Burst Mode operation when the output load exceeds 100mA. The advantage of pulse skipping mode is lower output ripple. When the converter is in Burst Mode operation, the peak current of the inductor is set to approximately 400mA, even though the voltage at the ITH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As 8 U (Refer to Block Diagram) the ITH voltage drops below approximately 0.45V, the BURST comparator trips, turning off both power MOSFETs. The ITH pin is then disconnected from the output of the EA amplifier and held 0.65V above ground. In sleep mode, both power MOSFETs are held off and the internal circuitry is partially turned off, reducing the quiescent current to 15µA. The load current is now being supplied from the output capacitor. When the output voltage drops, the ITH pin reconnects to the output of the EA amplifier and the top MOSFET is again turned on and this process repeats. Soft-Start/Run Function The RUN/SS pin provides a soft-start function and a means to shut down the LTC1879. Soft-start reduces the input current surge by gradually increasing the regulator’s maximum output current. This pin can also be used for power supply sequencing. Pulling the RUN/SS pin below 0.7V shuts down the LTC1879, which then draws < 1µA current from the supply. This pin can be driven directly from logic circuits as shown in Figure 1. It is recommended that this pin is driven to VIN during normal operation. Note that there is no current flowing out of this pin. Soft-start action is accomplished by connecting an external RC network to the RUN/ SS pin as shown in Figure 1. The LTC1879 actively pulls the RUN/SS pin to ground under low input supply voltage conditions. VIN 3.3V OR 5V D1* 0.32V RSS RUN/SS CSS *ZETEX BAT54 1879 F01 Figure 1. RUN/SS Pin Interfacing 1879f LTC1879 OPERATIO Power Good Indicator The power good function monitors the output voltage in all modes of operation. Its open-drain output is pulled low when the output voltage is not within ± 7.5% of its nominally regulated voltage. The feedback voltage is filtered before it is fed to a power good window comparator in order to prevent false tripping of the power good signal during fast transients. The window comparator monitors the output voltage even in Burst Mode operation. In shutdown mode, open drain is actively pulled low to indicate that the output voltage is invalid. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 80kHz, 1/7 the nominal frequency. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will progressively increase to 550kHz (or to the synchronized frequency) when VFB rises above 0.3V. Frequency Synchronization The LTC1879 can be synchronized to an external clock source connected to the SYNC/MODE pin. The turn-on of the top MOSFET is synchronized to the rising edge of the external clock. When the LTC1879 is clocked by an external source, Burst Mode operation is disabled. In this synchronized mode, when the output load current is very low, current comparator, ICOMP, may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. Increasing the output load slightly allows constant frequency PWM operation to resume. Frequency synchronization is inhibited when the feedback voltage VFB is below 0.6V. This prevents the external clock from interfering with the frequency foldback for shortcircuit protection. MAXIMUM OUTPUT CURRENT (mA) U (Refer to Block Diagram) Low Dropout Operation When the input supply voltage decreases toward the output voltage in a buck regulator, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the top MOSFET and the inductor. Low Supply Operation The LTC1879 is designed to operate down to an input supply voltage of 2.65V although the maximum allowable output current is reduced at this low voltage. Figure 2 shows the reduction in the maximum output current as a function of input voltage. Another important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases. Therefore, the user should calculate the power dissipation when the LTC1879 is used at 100% duty cycle with low supply voltage (see Thermal Considerations in the Applications Information section). 1800 1600 1400 1200 VOUT = 3.1V 1000 800 600 400 2 3 4 5 6 7 8 9 10 INPUT VOLTAGE (V) 1879 F02 VOUT = 2.5V VOUT = 1.8V Figure 2. Maximum Output Current vs Input Voltage 1879f 9 LTC1879 OPERATIO MAXIMUM INDUCTOR PEAK CURRENT (mA) Slope Compensation and Inductor Peak Current Slope compensation is required in order to prevent subharmonic oscillation at high duty cycles. It is accomplished by internally adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. As a result, the maximum inductor peak current is reduced for duty cycles > 40%. This is shown in the decrease of the inductor peak current as a function of duty cycle graph in Figure 3. APPLICATIO S I FOR ATIO The basic LTC1879 application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Value Calculation The inductor selection will depend on the operating frequency of the LTC1879. The internal nominal frequency is 550kHz, but can be externally synchronized from 350kHz to 750kHz. The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. However, operating at a higher frequency results in lower efficiency because of increased switching losses. The inductor value has a direct effect on ripple current. The ripple current ∆IL decreases with higher inductance or frequency and increases with higher input voltages. ∆IL = V 1 VOUT  1– OUT  ( f)(L)  VIN  Accepting larger values of ∆IL allows the use of smaller inductors, but results in higher output voltage ripple. 10 U W UU U 2400 2200 2000 1800 1600 1400 1200 1000 VIN = 5V 0 20 40 60 DUTY CYCLE (%) 80 100 1879 F03 Figure 3. Maximum Inductor Peak Current vs Duty Cycle A reasonable starting point for setting ripple current is ∆IL = 0.3(IMAX). The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 500mA. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Selection The inductor should have a saturation current rating greater than the peak inductor current set by the current comparator of LTC1879. Also, consideration should be given to the resistance of the inductor. Inductor conduction losses are directly proportional to the DC resistance of the inductor. Manufacturers sometimes provide maximum current ratings based on the allowable losses in the inductor. Suitable inductors are available from Coilcraft, Cooper, Dale, Sumida, Toko, Murata, Panasonic and other manufacturers. (1) 1879f LTC1879 APPLICATIO S I FOR ATIO CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a trapezoidal waveform of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS input capacitor current is given by: IRMS(CIN) ≅ IOMAX [VOUT(VIN – VOUT )]1/2 VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there are any questions. Depending on how the LTC1879 circuit is powered up, you may need to check for input voltage transients. Input voltage transients may be caused by input voltage steps or by connecting the circuit to an already powered up source such as a wall adapter. The sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic inductance of the leads. This energy will cause the input voltage to swing above the DC level of the input power source and it may exceed the maximum voltage rating of the input capacitor and LTC1879. The easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low ESR input capacitor. The selected capacitor needs to have the right amount of ESR in order to critically dampen the resonant circuit formed by the input lead inductance and the input capacitor. The typical values of ESR will fall in the range of 0.5Ω to 2Ω and capacitance will fall in the range of 5µF to 50µF. U The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple ∆VOUT is determined by:  1 ∆VOUT ≅ ∆IL  ESR +   8 fCOUT  W UU where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. For the LTC1879, the general rule for proper operation is: ESRCOUT < 0.125Ω The choice of using a smaller output capacitance increases the output ripple voltage due to the frequency dependent term but can be compensated for by using capacitor(s) of very low ESR to maintain low ripple voltage. The ITH pin compensation components can be optimized to provide stable high performance transient response regardless of the output capacitor selected. Manufacturers such as Taiyo Yuden, AVX, Kemet and Sanyo should be considered for low ESR, high performance capacitors. The POSCAP solid electrolytic chip capacitor available from Sanyo is an excellent choice for output bulk capacitors due to its low ESR/size ratio. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. Output Voltage Programming The output voltage is set by a resistor divider according to the following formula:  R1 VOUT = 0.8 V 1 +   R2  (2) The external resistor divider is connected to the output, allowing remote voltage sensing as shown in Figure 4. 1879f 11 LTC1879 APPLICATIO S I FOR ATIO 0.8V ≤ VOUT ≤ 10V R1 VFB LTC1879 SGND 1879 F04 R2 Figure 4. Setting the LTC1879 Output Voltage Phase-Locked Loop and Frequency Synchronization The LTC1879 has an internal voltage-controlled oscillator and phase detector comprising a phase-locked loop. This allows the MOSFET turn-on to be locked to the rising edge of an external frequency source. The frequency range of the voltage-controlled oscillator is 350kHz to 750kHz. The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the harmonics of the VCO center frequency. The PLL hold-in range ∆fH is equal to the capture range, ∆fH = ∆fC = ± 200kHz. The output of the phase detector is a pair of complementary current sources charging or discharging the external filter network on the PLL_LPF pin. The relationship between the voltage on the PLL_LPF pin and operating frequency is shown in Figure 5. A simplified block diagram is shown in Figure 6. 1000 900 800 OSC FREQUECNY (kHz) 700 600 500 400 300 200 100 0 0 0.5 1 VPLLLPF (V) 1.5 2 1879 F05 Figure 5. Relationship Between Oscillator Frequency and Voltage at PLL_LPF Pin 12 U RLP 2.4V CLP PLL_LPF SYNC/ MODE DIGITAL PHASE/ FREQUENCY DETECTOR VCO 1879 F06 W UU Figure 6. Phase-Locked Loop Block Diagram If the external frequency (VSYNC/MODE) is greater than 550kHz, the center frequency, current is sourced continuously, pulling up the PLL_LPF pin. When the external frequency is less than 550kHz, current is sunk continuously, pulling down the PLL_LPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus the voltage on the PLL_LPF pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operating point the phase comparator output is open and the filter capacitor CLP holds the voltage. The loop filter components CLP and RLP smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01µF. When not synchronized to an external clock, the internal connection to the VCO is disconnected. This disallows setting the internal oscillation frequency by a DC voltage on the VPLLLPF pin. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (ρ1 + ρ2 + ρ3 + ...) 1879f LTC1879 APPLICATIO S I FOR ATIO Where ρ1, ρ2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC1879 circuits: supply quiescent currents and I2R losses. The supply quiescent current loss dominates the efficiency loss at very low load current whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 7. 1. The supply quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from PVIN to ground. The resulting dQ/dt is the current out of PVIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to supply voltage and thus their effects will be more pronounced at higher supply voltages. 1 VIN = 6V VOUT = 3.3V L = 6.8µH Burst Mode OPERATION 0.1 POWER LOST (W) 0.01 0.001 0.0001 0.1 1 10 100 LOAD CURRENT (mA) 1000 1879 F07 Figure 7. Power Lost vs Load Current U 2. I2R losses are calculated from the resistances of the internal switches RSW and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into SW pins is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In most applications, the LTC1879 does not dissipate much heat due to its high efficiency. But, in applications where the LTC1879 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW nodes will become high impedance. To avoid the LTC1879 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. Normally, some iterative calculation is required to determine a reasonably accurate value. The temperature rise is given by: TR = P • θJA where P is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature is given by: TJ = TA + TR 1879f W UU 13 LTC1879 APPLICATIO S I FOR ATIO where TA is the ambient temperature. Because the power transistor RDS(ON) is a function of temperature, it is usually necessary to iterate 2 to 3 times through the equations to achieve a reasonably accurate value for the junction temperature. As an example, consider the LTC1879 in dropout at an input voltage of 5V, a load current of 0.8A and an ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 70°C is 0.38Ω. Therefore, power dissipated by the IC is: P = I2 • RDS(ON) = 0.243W For the SSOP package, the θJA is 140°C/W. Thus the junction temperature of the regulator is: TJ = 70°C + (0.243)(140) = 104°C However, at this temperature, the RDS(ON) is actually 0.42Ω. Therefore: TJ = 70°C + (0.269)(140) = 108°C which is below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). 14 U Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, generating a feedback error signal. The regulator loop then acts to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin can be used for external compensation as shown in Figure 9. (The capacitor, CC2, is typically needed for noise decoupling.) A second, more severe transient is caused by switching in loads with large (> 1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. 1879f W UU LTC1879 APPLICATIO S I FOR ATIO PC Board Layout Checklist As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. Figure 8 is a sample of PC board layout for the design example shown in Figure 9. A 4-layer PC board is used in this design. Several guidelines are followed in this layout: 1. In order to minimize switching noise and improve output load regulation, the PGND pins of the LTC1879 should be connected directly to 1) the negative terminal of the output decoupling capacitors, 2) the negative terminal of the input capacitor and 3) vias to the ground plane immediately adjacent to Pins 1, 7 and 10. The ground trace on the top layer of the PC board should be as wide and short as possible to minimize series resistance and inductance. 2. Beware of ground loops in multiple layer PC boards. Try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. If the ground is to be used for high DC currents, choose a path away from the small-signal components. VIAS TO GND PLANE RC CC2 CPL CSS RPG RSS RFB2 RFB1 DUT L1 CIN1 VIN Figure 8. Typical Application and Suggested Layout (Topside Only) 1879f U 3. The high di/dt loop from the top terminal of the input capacitor, through the power MOSFETs and back to the input capacitor should be kept as tight as possible to reduce inductive ringing. Excess inductance can cause increased stress on the power MOSFET and increase noise on the input. If low ESR ceramic capacitors are used to reduce input noise, place these capacitors close to the DUT in order to keep the series inductance to a minimum. 4. Place the small-signal components away from high frequency switching nodes. In the layout shown in Figure 8, all of the small-signal components have been placed on one side of the IC and all of the power components have been placed on the other. 5. For optimum load regulation and true sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC1879 in order to keep the high impedance FB node short. CC1 RPL RSVIN VIA CONNECTION TO RFB1 CIN2 PGND COUT VOUT 1879 F08 W UU VIAS TO GND PLANE 15 LTC1879 APPLICATIO S I FOR ATIO Design Example As a design example, assume the LTC1879 is used in a dual lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 8.4V down to about 2.65V. The load current requirement is a maximum of 0.7A but most of the time it will be on standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using equation (1), L= V 1 VOUT  1– OUT  ( f)(∆IL )  VIN  Substituting VOUT = 2.5V, VIN = 8.4V, ∆IL = 210mA and f = 550kHz in equation (3) gives: L= 2.5V  2.5V   1–  = 15.2µH 550kHz • 210mA  8.4V  16 U An 15µH inductor works well for this application. For good efficiency choose a 1.5A inductor with less than 0.125Ω series resistance. CIN will require an RMS current rating of at least 0.35A at temperature and COUT will require an ESR of less than 0.125Ω. In most applications, the requirements for these capacitors are fairly similar. For the feedback resistors, choose R2 = 412k. R1 can then be calculated from equation (2) to be: V  R1 =  OUT – 1 • R2 = 875.5k, use 887k  0.8  Figure 9 shows the complete circuit along with its efficiency curve. (3) 1879f W UU LTC1879 APPLICATIO S I FOR ATIO CSVIN 0.1µF RPG 100k 14 RSS 1M 2 CSS 0.1µF RUN/SS 13 SVIN PGOOD SYNC/MODE PVIN PVIN PGND PGND 8 9 7 10 COUT 47µF VOUT 2.5V 0.7A CIN1 10µF CIN2 10µF VIN 2.65V TO 8.4V GND LTC1879 16 PLL_LPF 4 CC1 47pF RC 150k ITH CC2 220pF BOLD LINES INDICATE HIGH CURRENT PATHS CIN1, CIN2: TAIYO YUDEN CERAMIC JMK316BJ106ML COUT: TDK CERAMIC C4532X5R0J476M L1: TOKO A921CY-150M VOUT: 0.7A IS THE MAXIMUM OUTPUT CURRENT Figure 9a. Dual Lithium-Ion/8V Wall Adapter to 2.5V/0.7A Regulator from Design Example 100 VIN = 3.6V VOUT = 2.5V L = 15µH 90 EFFICIENCY (%) 80 70 60 0.1 Figure 9b. Efficiency vs Output Current for Design Example U RSVIN 10Ω 15 SWP SWP SWN SWN VFB SGND 5 12 6 11 3 R1 887k R2 412k 1879 F09a W UU L1 15µH 1 1 10 100 OUTPUT CURRENT (mA) 1000 1879 F09b 1879f 17 LTC1879 TYPICAL APPLICATIO Dual Li-Ion to 1.8V/1A Regulator Using All Ceramic Capacitors RSVIN 10Ω CSVIN 0.1µF 13 SVIN 14 RSS 1M 2 CSS 0.1µF LTC1879 16 RUN/SS PGOOD 15 SYNC/MODE PVIN PVIN PGND PGND 8 9 7 10 COUT 47µF L1 8.2µH VOUT 1.8V 1A CIN1 10µF CIN2 10µF VIN 3V TO 8.4V GND RPG 100k CC2 220pF CC1 47pF RC 150k BOLD LINES INDICATE HIGH CURRENT PATHS CIN1, CIN2: TAIYO YUDEN CERAMIC LMK325BJ106MN COUT: TDK CERAMIC C4532X5R0J476M L1: TOKO A916CY-8R2M VOUT: 1A IS THE MAXIMUM OUTPUT CURRENT EFFICIENCY (%) 18 U SWP SWP SWN SWN 4 ITH VFB SGND 5 12 6 11 3 R2 412k 1879 TA02 PLL_LPF R1 523k 1 Efficiency vs Output Current 100 90 80 VIN = 5V 70 VIN = 7.2V 60 50 40 0.1 VIN = 3.6V VOUT = 1.8V Burst Mode OPERATION 10 100 1 OUTPUT CURRENT (mA) 1000 1879 TA04 1879f LTC1879 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0° – 8° TYP .053 – .068 (1.351 – 1.727) 23 4 56 7 8 .004 – .0098 (0.102 – 0.249) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U .045 ± .005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0250 TYP .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC GN16 (SSOP) 0502 1879f 19 LTC1879 TYPICAL APPLICATIO 5-Cell NiMH to 3.3V/0.25A ZETA Regulator Using All Ceramic Capacitors RSVIN 10Ω CSVIN 0.1µF 13 SVIN 14 RSS 1M 2 CSS 0.1µF LTC1879 16 RUN/SS PGOOD 15 SYNC/MODE PVIN PVIN PGND PGND 8 9 7 10 L1 SWP SWP SWN SWN 4 CC1 47pF RC 150k ITH VFB SGND 1 5 12 6 11 3 CC 10µF R1 1.3M R2 412k 1879 TA03 RPG 100k CC2 220pF BOLD LINES INDICATE HIGH CURRENT PATHS CC: TAIYO YUDEN CERAMIC LMK325BJ106MN CIN1, CIN2: TAIYO YUDEN CERAMIC LMK325BJ106MN COUT: TDK CERAMIC C4532X5R0J476M L1: COILTRONICS CTX5-4 RELATED PARTS PART NUMBER LT1616 DESCRIPTION 25V, 500mA (IOUT), 1.4MHz, High Efficiency Step-Down DC/DC Converter LT1676 60V, 440mA (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converter LT1765 25V, 2.75A (IOUT), 1.25MHz, High Efficiency Step-Down DC/DC Converter LT1766/LT1956 60V, 1.2A (IOUT), 200kHz/500kHz, High Efficiency Step-Down DC/DC Converter LT1767 25V, 1.2A (IOUT), 1.25kHz, High Efficiency Step-Down DC/DC Converter LTC®1875 1.5A, (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter LTC1877 600mA, (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter LT1940 Dual Output 1.4A (IOUT), Constant 1.1MHz, High Efficiency Step-Down DC/DC Converter LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter LTC3430 2.5A (IOUT), 4MHz Synchronous Step-Down DC/DC Converter ThinSOT is a trademark of Linear Technology Corporation. COMMENTS VIN = 3.6V to 25V, VOUT(MIN) = 1.25V, IO = 1.9mA, ISD =