LTC2183IUPPBF

LTC2185/LTC2184/LTC2183 16-Bit, 125/105/80Msps Low Power Dual ADCs FeaTures n n n n DescripTion The LTC®2185/LTC2184/LTC2183 are two-channel simultaneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 76.8dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.4LSBRMS. The digital outputs can be either full rate CMOS, Double Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n n n n n n n n n Two-Channel Simultaneously Sampling ADC 76.8dB SNR 90dB SFDR Low Power: 370mW/308mW/200mW Total 185mW/154mW/100mW per Channel Single 1.8V Supply CMOS, DDR CMOS, or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 550MHz Full Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration 64-Pin (9mm × 9mm) QFN Package applicaTions n n n n n n Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing Typical applicaTion 1.8V VDD 1.8V OVDD 0 –10 CH 1 ANALOG INPUT –20 AMPLITUDE (dBFS) S/H 16-BIT ADC CORE D1_15 • • • D1_0 OUTPUT DRIVERS D2_15 • • • D2_0 –30 –40 –50 –60 –70 –80 CMOS, DDR CMOS OR DDR LVDS OUTPUTS 2-Tone FFT, fIN = 70MHz and 69MHz CH 2 ANALOG INPUT S/H 16-BIT ADC CORE –90 –100 –110 –120 125MHz CLOCK GND CLOCK CONTROL 218543 TA01a 0 10 20 30 40 FREQUENCY (MHz) 50 60 218543 TA01b OGND 218543f 1 LTC2185/LTC2184/LTC2183 absoluTe MaxiMuM raTings (Notes 1, 2) Supply Voltages (VDD, OVDD) ....................... –0.3V to 2V Analog Input Voltage (AIN+, AIN–, PAR/SER, SENSE) (Note 3) .......... – 0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4) .................................... – 0.3V to 3.9V SDO (Note 4) ............................................ – 0.3V to 3.9V Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2185C, 2184C, 2183C ........................ 0°C to 70°C LTC2185I, 2184I, 2183I ....................... – 40°C to 85°C Storage Temperature Range................... – 65°C to 150°C pin conFiguraTions FULL-RATE CMOS OUTPUT MODE TOP VIEW 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF1 59 OF2 58 D1_15 57 D1_14 56 D1_13 55 D1_12 54 D1_11 53 D1_10 52 D1_9 51 D1_8 50 D1_7 49 D1_6 DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF2_1 59 DNC 58 D1_14_15 57 DNC 56 D1_12_13 55 DNC 54 D1_10_11 53 DNC 52 D1_8_9 51 DNC 50 D1_6_7 49 DNC 48 D1_5 47 D1_4 46 D1_3 45 D1_2 44 D1_1 43 D1_0 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT– 38 D2_15 37 D2_14 36 D2_13 35 D2_12 34 D2_11 33 D2_10 VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1– 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2– 13 GND 14 VCM2 15 VDD 16 65 GND 48 D1_4_5 47 DNC 46 D1_2_3 45 DNC 44 D1_0_1 43 DNC 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT– 38 D2_14_15 37 DNC 36 D2_12_13 35 DNC 34 D2_10_11 33 DNC UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB VDD 17 ENC+ 18 ENC– 19 CS 20 SCK 21 SDI 22 DNC 23 D2_0_1 24 DNC 25 D2_2_3 26 DNC 27 D2_4_5 28 DNC 29 D2_6_7 30 DNC 31 D2_8_9 32 VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1– 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2– 13 GND 14 VCM2 15 VDD 16 65 GND UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB VDD 17 ENC+ 18 ENC– 19 CS 20 SCK 21 SDI 22 D2_0 23 D2_1 24 D2_2 25 D2_3 26 D2_4 27 D2_5 28 D2_6 29 D2_7 30 D2_8 31 D2_9 32 218543f 2 LTC2185/LTC2184/LTC2183 pin conFiguraTions DOUBLE DATA RATE LVDS OUTPUT MODE TOP VIEW 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF2_1+ 59 OF2_1– 58 D1_14_15+ 57 D1_14_15– 56 D1_12_13+ 55 D1_12_13– 54 D1_10_11+ 53 D1_10_11– 52 D1_8_9+ 51 D1_8_9– 50 D1_6_7+ 49 D1_6_7– VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1– 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2– 13 GND 14 VCM2 15 VDD 16 65 GND 48 D1_4_5+ 47 D1_4_5– 46 D1_2_3+ 45 D1_2_3– 44 D1_0_1+ 43 D1_0_1– 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT– 38 D2_14_15+ 37 D2_14_15– 36 D2_12_13+ 35 D2_12_13– 34 D2_10_11+ 33 D2_10_11– UP PACKAGE 64-LEAD (9mm × 9mm) PLASTIC QFN TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH LTC2185CUP#PBF LTC2185IUP#PBF LTC2184CUP#PBF LTC2184IUP#PBF LTC2183CUP#PBF LTC2183IUP#PBF TAPE AND REEL LTC2185CUP#TRPBF LTC2185IUP#TRPBF LTC2184CUP#TRPBF LTC2184IUP#TRPBF LTC2183CUP#TRPBF LTC2183IUP#TRPBF PART MARKING* LTC2185UP LTC2185UP LTC2184UP LTC2184UP LTC2183UP LTC2183UP PACKAGE DESCRIPTION 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN 64-Lead (9mm × 9mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ VDD 17 ENC+ 18 ENC– 19 CS 20 SCK 21 SDI 22 D2_0_1– 23 D2_0_1+ 24 D2_2_3– 25 D2_2_3+ 26 D2_4_5– 27 D2_4_5+ 28 D2_6_7– 29 D2_6_7+ 30 D2_8_9– 31 D2_8_9+ 32 218543f 3 LTC2185/LTC2184/LTC2183 converTer characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Gain Matching Offset Matching Transition Noise Internal Reference External Reference Differential Analog Input (Note 7) Internal Reference External Reference CONDITIONS l LTC2185 MIN 16 –7.5 –0.9 –7 –2.3 ±2 ±0.5 ±1.5 ±1.5 –0.9 ±10 ±30 ±10 ±0.3 ±1.5 3.4 7.5 0.9 7 0.3 TYP MAX MIN 16 –7.5 –0.9 –7 –2.1 LTC2184 TYP ±2 ±0.5 ±1.5 ±1.5 –0.8 ±10 ±30 ±10 ±0.3 ±1.5 3.5 MAX 7.5 0.9 7 0.4 MIN 16 –7.5 –0.9 –7 –1.8 LTC2183 TYP ±2 ±0.5 ±1.5 ±1.5 –0.5 ±10 ±30 ±10 ±0.3 ±1.5 3.2 MAX 7.5 0.9 7 0.8 UNITS Bits LSB LSB mV %FS %FS µV/°C ppm/°C ppm/°C %FS mV LSBRMS Differential Analog Input (Note 6) l l l l analog inpuT SYMBOL PARAMETER VIN VIN(CM) VSENSE IINCM IIN1 IIN2 IIN3 tAP tJITTER CMRR BW-3B The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS 1.7V < VDD < 1.9V Differential Analog Input (Note 8) Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps 0 < AIN+, AIN– < VDD 0 < PAR/SER < VDD 0.625 < SENSE < 1.3V Single-Ended Encode Differential Encode Figure 6 Test Circuit l l l l l l MIN 0.7 0.625 TYP 1 to 2 VCM 1.250 200 170 130 MAX 1.25 1.300 UNITS VP-P V V µA µA µA Analog Input Range (AIN+ – AIN–) Analog Input Common Mode (AIN+ + AIN–)/2 Analog Input Common Mode Current External Voltage Reference Applied to SENSE External Reference Mode Analog Input Leakage Current (No Encode) PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth –1.5 –3 –3 0 0.07 0.09 80 550 1.5 3 3 µA µA µA ns psRMS psRMS dB MHz 218543f 4 LTC2185/LTC2184/LTC2183 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) LTC2185 SYMBOL SNR PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 70MHz Input 140MHz Input l DynaMic accuracy LTC2184 MAX MIN 74.8 TYP 76.7 76.5 76 90 89 84 90 89 84 95 95 95 76.5 76.1 75 –110 MAX MIN 75.1 LTC2183 TYP 77.1 76.9 76.4 90 89 84 90 89 84 95 95 95 76.9 76.5 75.3 –110 MAX UNITS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc MIN 74.8 TYP 76.8 76.6 76.1 90 89 84 90 89 84 95 95 95 76.6 76.2 75.1 –110 SFDR Spurious Free Dynamic Range 5MHz Input 2nd Harmonic 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 3rd Harmonic 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 70MHz Input 140MHz Input l 79 81 81 l 82 81 82 l 89 89 89 S/(N+D) Signal-to-Noise Plus Distortion Ratio Crosstalk 5MHz Input 70MHz Input 140MHz Input 10MHz Input l 73.3 73.9 74.4 inTernal reFerence characTerisTics PARAMETER VCM Output Voltage VCM Output Temperature Drift VCM Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation –400µA < IOUT < 1mA 1.7V < VDD < 1.9V –600µA < IOUT < 1mA IOUT = 0 CONDITIONS IOUT = 0 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN 0.5 • VDD – 25mV TYP 0.5 • VDD ±25 4 1.225 1.250 ±25 7 0.6 1.275 MAX 0.5 • VDD + 25mV UNITS V ppm/°C Ω V ppm/°C Ω mV/V 218543f 5 LTC2185/LTC2184/LTC2183 DigiTal inpuTs anD ouTpuTs SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID VICM VIN RIN CIN VIH VIL VIN RIN CIN VIH VIL IIN CIN ROL IOH COUT Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance Logic Low Output Resistance to GND Logic High Output Leakage Current Output Capacitance (Note 8) Internally Set Externally Set (Note 8) ENC+, ENC– to GND (See Figure 10) (Note 8) VDD = 1.8V VDD = 1.8V ENC+ to GND (See Figure 11) (Note 8) VDD = 1.8V VDD = 1.8V VIN = 0V to 3.6V (Note 8) VDD = 1.8V, SDO = 0V SDO = 0V to 3.6V (Note 8) l l l l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS MIN TYP MAX UNITS 0.2 1.1 0.2 10 3.5 1.2 0.6 0 30 3.5 1.3 0.6 –10 3 200 –10 3 10 10 3.6 1.2 1.6 3.6 V V V V kΩ pF V V V kΩ pF V V µA pF Ω µA pF Single-Ended Encode Mode (ENC– Tied to GND) DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OVDD = 1.8V VOH VOL VOH VOL VOH VOL VOD VOS RTERM High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage High Level Output Voltage Low Level Output Voltage Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance IO = –500µA IO = 500µA IO = –500µA IO = 500µA IO = –500µA IO = 500µA 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode Termination Enabled, OVDD = 1.8V l l l l 1.750 1.790 0.010 1.488 0.010 1.185 0.010 0.050 V V V V V V 454 1.375 mV mV V V Ω OVDD = 1.5V OVDD = 1.2V DIGITAL DATA OUTPUTS (LVDS MODE) 247 1.125 350 175 1.250 1.250 100 218543f 6 LTC2185/LTC2184/LTC2183 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2185 SYMBOL PARAMETER VDD OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation CONDITIONS (Note 10) (Note 10) DC Input Sine Wave Input Sine Wave Input, OVDD = 1.2V l DC Input Sine Wave Input, OVDD = 1.2V l l l power requireMenTs LTC2184 MAX 1.9 1.9 228 MIN 1.7 1.1 TYP 1.8 1.8 171 173 8 410 308 321 1.7 1.7 1.8 1.8 175 177 40 75 387 454 1 16 20 339 MAX 1.9 1.9 188 MIN 1.7 1.1 LTC2183 TYP 1.8 1.8 111 113 6 200 211 1.7 1.7 1.8 1.8 115 117 39 75 277 346 1 16 20 223 MAX 1.9 1.9 124 UNITS V V mA mA mA mW mW V V mA mA mA mA mW mW mW mW mW MIN 1.7 1.1 TYP 1.8 1.8 206 209 10 370 388 CMOS Output Modes: Full Data Rate and Double Data Rate LVDS Output Mode VDD OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current (0VDD = 1.8V) Power Dissipation (Note 10) (Note 10) Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l l l l l 1.7 1.7 1.8 1.8 211 213 40 76 452 520 1 16 20 1.9 1.9 233 86 574 1.9 1.9 193 85 500 1.9 1.9 128 84 382 All Output Modes PSLEEP PNAP PDIFFCLK Sleep Mode Power Nap Mode Power Power Increase with Differential Encode Mode Enabled (No increase for Nap or Sleep Modes) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2185 SYMBOL fS tL tH tAP PARAMETER Sampling Frequency ENC Low Time (Note 8) ENC High Time (Note 8) Sample-and-Hold Acquisition Delay Time PARAMETER ENC to Data Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Pipeline Latency CONDITIONS CL = 5pF (Note 8) CL = 5pF (Note 8) tD – tC (Note 8) Full Data Rate Mode Double Data Rate Mode l l l TiMing characTerisTics CONDITIONS (Note 10) LTC2184 MAX 125 500 500 500 500 MIN 1 4.52 2 4.52 2 4.76 4.76 4.76 4.76 0 TYP MAX 105 500 500 500 500 MIN 1 5.93 2 5.93 2 LTC2183 TYP 6.25 6.25 6.25 6.25 0 MAX 80 500 500 500 500 UNITS MHz ns ns ns ns ns MIN l l l l l TYP 4 4 4 4 0 1 3.8 2 3.8 2 Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On SYMBOL tD tC tSKEW MIN 1.1 1 0 TYP 1.7 1.4 0.3 6 6.5 MAX 3.1 2.6 0.6 UNITS ns ns ns Cycles Cycles Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate) 218543f 7 LTC2185/LTC2184/LTC2183 TiMing characTerisTics SYMBOL tD tC tSKEW PARAMETER ENC to Data Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Pipeline Latency SPI Port Timing (Note 8) tSCK tS tH tDS tDH tDO SCK Period CS to SCK Setup Time SCK to CS Setup Time SDI Setup Time SDI Hold Time SCK Falling to SDO Valid Readback Mode, CSDO = 20pF RPULLUP = 2k , Write Mode Readback Mode, CSDO = 20pF RPULLUP = 2k , l l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS CL = 5pF (Note 8) CL = 5pF (Note 8) tD – tC (Note 8) l l l MIN 1.1 1 0 TYP 1.8 1.5 0.3 6.5 MAX 3.2 2.7 0.6 UNITS ns ns ns Cycles ns ns ns ns ns ns Digital Data Outputs (LVDS Mode) 40 250 5 5 5 5 125 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2185), 105MHz (LTC2184), or 80MHz (LTC2183), LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = 1.8V, fSAMPLE = 125MHz (LTC2185), 105MHz (LTC2184), or 80MHz (LTC2183), CMOS outputs, ENC+ = single-ended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on each digital output unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel. Note 10: Recommended operating conditions. 218543f 8 LTC2185/LTC2184/LTC2183 TiMing DiagraMs Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP CH 1 ANALOG INPUT CH 2 ANALOG INPUT A tAP B tH ENC– ENC+ tD D1_0 - D1_15, OF1 A–6 A–5 A–4 A–3 A–2 B+1 A+1 B+2 B+3 tL B+4 A+2 A+3 A+4 D2_0 - D2_15, OF2 CLKOUT + CLKOUT – tC B–6 B–5 B–4 B–3 B–2 218543 TD01 Double Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP CH 1 ANALOG INPUT CH 2 ANALOG INPUT A tAP B tH ENC– ENC+ tD D1_0_1 BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 tD BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 B+1 A+1 B+2 B+3 tL B+4 A+2 A+3 A+4 • • • D1_14_15 BIT 14 A-6 BIT 15 A-6 BIT 14 A-5 BIT 15 A-5 BIT 14 A-4 BIT 15 A-4 BIT 14 A-3 BIT 15 A-3 BIT 14 A-2 D2_0_1 BIT 0 B-6 BIT 1 B-6 BIT 0 B-5 BIT 1 B-5 BIT 0 B-4 BIT 1 B-4 BIT 0 B-3 BIT 1 B-3 BIT 0 B-2 • • • D2_14_15 BIT 14 B-6 BIT 15 B-6 BIT 14 B-5 BIT 15 B-5 BIT 14 B-4 BIT 15 B-4 BIT 14 B-3 BIT 15 B-3 BIT 14 B-2 OF2_1 CLKOUT+ CLKOUT – OF B-6 tC OF A-6 OF B-5 OF A-5 tC OF B-4 OF A-4 OF B-3 OF A-3 OF B-2 218543 TD02 218543f 9 LTC2185/LTC2184/LTC2183 TiMing DiagraMs Double Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP CH 1 ANALOG INPUT CH 2 ANALOG INPUT A tAP B tH ENC– ENC+ D1_0_1+ D1_0_1– D1_14_15+ D1_14_15– D2_0_1+ D2_0_1– D2_14_15+ D2_14_15– OF2_1+ OF2_1– CLKOUT+ CLKOUT – tD BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 tD BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 B+1 A+1 B+2 B+3 tL B+4 A+2 A+3 A+4 • • • BIT 14 A-6 BIT 15 A-6 BIT 14 A-5 BIT 15 A-5 BIT 14 A-4 BIT 15 A-4 BIT 14 A-3 BIT 15 A-3 BIT 14 A-2 BIT 0 B-6 BIT 1 B-6 BIT 0 B-5 BIT 1 B-5 BIT 0 B-4 BIT 1 B-4 BIT 0 B-3 BIT 1 B-3 BIT 0 B-2 • • • BIT 14 B-6 BIT 15 B-6 BIT 14 B-5 BIT 15 B-5 BIT 14 B-4 BIT 15 B-4 BIT 14 B-3 BIT 15 B-3 BIT 14 B-2 OF B-6 tC OF A-6 OF B-5 OF A-5 tC OF B-4 OF A-4 OF B-3 OF A-3 OF B-2 218543 TD03 SPI Port Timing (Readback Mode) tS CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 XX D6 XX D5 XX D4 XX D3 XX D2 XX D1 XX D0 tDS tDH tSCK tH HIGH IMPEDANCE SPI Port Timing (Write Mode) CS SCK SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE 218543 TD04 218543f 10 LTC2185/LTC2184/LTC2183 Typical perForMance characTerisTics LTC2185: Integral Non-Linearity (INL) 4.0 3.0 2.0 DNL ERROR (LSB) INL ERROR (LSB) 1.0 0 –1.0 –2.0 –3.0 –4.0 0 16384 32768 49152 OUTPUT CODE 65536 218543 G01 LTC2185: Differential Non-Linearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 49152 OUTPUT CODE 65536 218543 G02 LTC2185: 64k Point FFT, fIN = 5MHz, –1dBFS, 125Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 218543 G03 LTC2185: 64k Point FFT, fIN = 30MHz, –1dBFS, 125Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2185: 64k Point FFT, fIN = 70MHz, –1dBFS, 125Msps 0 –10 –20 –30 AMPLITUDE (dBFS) 0 20 30 40 FREQUENCY (MHz) 50 60 218543 G05 LTC2185: 64k Point FFT, fIN = 140MHz, –1dBFS, 125Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 218543 G04 10 0 10 20 30 40 FREQUENCY (MHz) 50 60 218543 G06 LTC2185: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, –7dBFS, 125Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 10000 9000 8000 7000 LTC2185: Shorted Input Histogram 78 77 76 SNR (dBFS) 75 74 73 72 71 32756 32762 32768 OUTPUT CODE 32774 218543 G08 LTC2185: SNR vs Input Frequency, –1dBFS, 125Msps, 2V Range SINGLE-ENDED ENCODE 6000 5000 4000 3000 2000 1000 DIFFERENTIAL ENCODE –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 218543 G07 0 32750 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 218543 G09 218543f 11 LTC2185/LTC2184/LTC2183 Typical perForMance characTerisTics LTC2185: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 125Msps, 2V Range 100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 2ND 3RD 100 95 SFDR (dBc AND dBFS) 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 3RD LTC2185: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 125Msps, 1V Range 130 120 110 100 90 80 70 60 50 40 30 LTC2185: SFDR vs Input Level, fIN = 70MHz, 125Msps, 2V Range dBFS 2ND dBc 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 218543 G10 218543 G11 218543 G12 LTC2185: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 220 210 3.5mA LVDS OUTPUTS 200 IOVDD (mA) IVDD (mA) 190 180 170 160 CMOS OUTPUTS 80 70 60 LTC2185: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 3.5mA LVDS 78 77 76 SNR (dBFS) 1.2V CMOS 0 25 50 75 100 SAMPLE RATE (Msps) 125 218543 G14 LTC2185: SNR vs SENSE, fIN = 5MHz, –1dBFS 50 40 30 20 10 1.8V CMOS 1.75mA LVDS 75 74 73 72 71 70 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0 25 50 75 100 SAMPLE RATE (Msps) 125 218543 G13 0 218543 G15 LTC2184: Integral Non-Linearity (INL) 4.0 3.0 2.0 DNL ERROR (LSB) INL ERROR (LSB) 1.0 0 –1.0 –2.0 –3.0 –4.0 0 16384 32768 49152 OUTPUT CODE 65536 218543 G16 LTC2184: Differential Non-Linearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 32768 49152 OUTPUT CODE 65536 218543 G17 LTC2184: 64k Point FFT, fIN = 5MHz, –1dBFS, 105Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 16384 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 218543 G18 218543f 12 LTC2185/LTC2184/LTC2183 Typical perForMance characTerisTics 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 LTC2184: 64k Point FFT, fIN = 30MHz, –1dBFS, 105Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2184: 64k Point FFT, fIN = 70MHz, –1dBFS, 105Msps LTC2184: 64k Point FFT, fIN = 140MHz, –1dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 218543 G19 0 10 20 30 40 FREQUENCY (MHz) 50 218543 G20 0 10 20 30 40 FREQUENCY (MHz) 50 218543 G21 LTC2184: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, –7dBFS, 105Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 10000 9000 8000 7000 LTC2184: Shorted Input Histogram 78 77 76 SNR (dBFS) 75 74 73 72 71 32796 32802 32808 OUTPUT CODE 32814 218543 G23 LTC2184: SNR vs Input Frequency, –1dBFS, 105Msps, 2V Range SINGLE-ENDED ENCODE 6000 5000 4000 3000 2000 1000 DIFFERENTIAL ENCODE –90 –100 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 218543 G22 0 32790 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 218543 G24 LTC2184: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 105Msps, 2V Range 100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 2ND 3RD 100 95 LTC2184: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 105Msps, 1V Range 130 120 3RD 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 LTC2184: SFDR vs Input Level, fIN = 70MHz, 105Msps, 2V Range dBFS 90 85 80 75 70 65 2ND dBc 218543 G25 218543 G26 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 218543 G27 218543f 13 LTC2185/LTC2184/LTC2183 Typical perForMance characTerisTics LTC2184: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 180 3.5mA LVDS OUTPUTS 80 70 60 IOVDD (mA) SNR (dBFS) 1.2V CMOS 0 25 50 75 SAMPLE RATE (Msps) 100 218543 G29 LTC2184: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 3.5mA LVDS 78 77 76 75 74 73 72 1.8V CMOS 71 70 LTC2184: SNR vs SENSE, fIN = 5MHz, –1dBFS 170 IVDD (mA) 160 CMOS OUTPUTS 150 50 40 30 20 10 1.75mA LVDS 140 130 0 25 50 75 SAMPLE RATE (Msps) 100 218543 G28 0 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 218543 G30 LTC2183: Integral Non-Linearity (INL) 4.0 3.0 2.0 DNL ERROR (LSB) INL ERROR (LSB) 1.0 0 –1.0 –2.0 –3.0 –4.0 0 16384 32768 49152 OUTPUT CODE 65536 218543 G31 LTC2183: Differential Non-Linearity (DNL) 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 32768 49152 OUTPUT CODE 65536 218543 G32 LTC2183: 64k Point FFT, fIN = 5MHz, –1dBFS, 80Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 16384 –90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40 218543 G33 LTC2183: 64k Point FFT, fIN = 30MHz, –1dBFS, 80Msps 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 0 –10 –20 –30 –40 –50 –60 –70 –80 LTC2183: 64k Point FFT, fIN = 70MHz, –1dBFS, 80Msps 0 –10 –20 –30 AMPLITUDE (dBFS) 10 20 30 FREQUENCY (MHz) 40 218543 G35 LTC2183: 64k Point FFT, fIN = 140MHz, –1dBFS, 80Msps –40 –50 –60 –70 –80 –90 –100 –110 –120 –90 –100 –110 –120 –90 –100 –110 –120 0 10 20 30 FREQUENCY (MHz) 40 218543 G34 0 0 10 20 30 FREQUENCY (MHz) 40 218543 G36 218543f 14 LTC2185/LTC2184/LTC2183 Typical perForMance characTerisTics LTC2183: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, –7dBFS, 80Msps 0 –10 –20 –30 AMPLITUDE (dBFS) –40 COUNT –50 –60 –70 –80 10000 9000 8000 7000 SNR (dBFS) 6000 5000 4000 3000 2000 1000 0 10 20 30 FREQUENCY (MHz) 40 218543 G37 LTC2183: Shorted Input Histogram 78 77 76 75 74 73 72 71 32823 32829 32835 OUTPUT CODE 32841 218543 G38 LTC2183: SNR vs Input Frequency, –1dBFS, 80Msps, 2V Range SINGLE-ENDED ENCODE DIFFERENTIAL ENCODE –90 –100 –110 –120 0 32817 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 218543 G39 LTC2183: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 80Msps, 2V Range 100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) 95 90 85 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 2ND 3RD 100 95 LTC2183: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 80Msps, 1V Range 130 120 3RD 110 SFDR (dBc AND dBFS) 100 90 80 70 60 50 40 30 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 LTC2183: SFDR vs Input Level, fIN = 70MHz, 80Msps, 2V Range dBFS 90 85 80 75 70 65 2ND dBc 218543 G40 218543 G41 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 218543 G27 LTC2183: IVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 130 80 70 120 3.5mA LVDS OUTPUTS IOVDD (mA) IVDD (mA) 110 60 LTC2183: IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input on Each Channel 3.5mA LVDS 78 77 76 SNR (dBFS) 1.2V CMOS 0 20 40 60 SAMPLE RATE (Msps) 80 218543 G44 LTC2183: SNR vs SENSE, fIN = 5MHz, –1dBFS 50 40 30 20 10 1.8V CMOS 1.75mA LVDS 75 74 73 72 71 70 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 100 CMOS OUTPUTS 90 80 0 20 40 60 SAMPLE RATE (Msps) 80 218543 G43 0 218543 G45 218543f 15 LTC2185/LTC2184/LTC2183 pin FuncTions PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT MODES VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to 1.9V. Bypass to ground with 0.1µF ceramic capacitors. Adjacent pins can share a bypass capacitor. VCM1 (Pin 2): Common Mode Bias Output, nominally equal to VDD/2. VCM1 should be used to bias the common mode of the analog inputs to channel 1. Bypass to ground with a 0.1µF ceramic capacitor. GND (Pins 3, 6, 14): ADC Power Ground. AIN1+ (Pin 4): Channel 1 Positive Differential Analog Input. AIN1– (Pin 5): Channel 1 Negative Differential Analog Input. REFH (Pins 7, 9): ADC High Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. REFL (Pins 8, 10): ADC Low Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. PAR/SER (Pin 11): Programming Mode selection pin. Connect to ground to enable the Serial Programming Mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the Parallel Programming Mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or VDD and not be driven by a logic signal. AIN2+ (Pin 12): Channel 2 Positive Differential Analog Input. AIN2– (Pin 13): Channel 2 Negative Differential Analog Input. VCM2 (Pin 15): Common Mode Bias Output, nominally equal to VDD/2. VCM2 should be used to bias the common mode of the analog inputs to channel 2. Bypass to ground with a 0.1µF ceramic capacitor. ENC+ (Pin 18): Encode Input. Conversion starts on the rising edge. ENC– (Pin 19): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 20): In Serial Programming Mode, (PAR/SER = 0V), CS is the Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the Parallel Programming Mode (PAR/SER = VDD), CS controls the Clock Duty Cycle Stabilizer (See Table 2). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 21): In Serial Programming Mode, (PAR/SER = 0V), SCK is the Serial Interface Clock Input. In the Parallel Programming Mode (PAR/SER = VDD), SCK controls the Digital Output Mode (See Table 2). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 22): In Serial Programming Mode, (PAR/SER = 0V), SDI is the Serial Interface Data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the Parallel Programming Mode (PAR/SER = VDD), SDI can be used together with SDO to power down the part (see Table 2). SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 41): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 42): Output Driver Supply. Bypass to ground with a 0.1µF ceramic capacitor. SDO (Pin 61): In Serial Programming Mode, (PAR/SER = 0V), SDO is the optional Serial Interface Data Output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the Parallel Programming Mode (PAR/SER = VDD), SDO can be used together with SDI to power down the part (see Table 2). When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. VREF (Pin 62): Reference Voltage Output. Bypass to ground with a 2.2µF ceramic capacitor. The output voltage is nominally 1.25V. 218543f 16 LTC2185/LTC2184/LTC2183 pin FuncTions SENSE (Pin 63): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. Ground (Exposed Pad Pin 65): The exposed pad must be soldered to the PCB ground. FULL-RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D2_0 to D2_15 (Pins 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_15 is the MSB. CLKOUT– (Pin 39): Inverted version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The Digital Outputs normally transition at the same time as the falling edge of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the Digital Outputs by programming the mode control registers. D1_0 to D1_15 (Pins 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_15 is the MSB. OF2 (Pin 59): Channel 2 Over/Under Flow Digital Output. OF2 is high when an overflow or underflow has occurred. OF1 (Pin 60): Channel 1 Over/Under Flow Digital Output. OF1 is high when an overflow or underflow has occurred. DOUBLE DATA RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D2_0_1 to D2_14_15 (Pins 24, 26, 28, 30, 32, 34, 36, 38): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. DNC (Pins 23, 25, 27, 29, 31, 33, 35, 37, 43, 45, 47, 49, 51, 53, 55, 57, 59): Do not connect these pins. CLKOUT– (Pin 39): Inverted version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The Digital Outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the Digital Outputs by programming the mode control registers. D1_0_1 to D1_14_15 (Pins 44, 46, 48, 50, 52, 54, 56, 58): Channel 1 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. OF2_1 (Pin 60): Over/Under Flow Digital Output. OF2_1 is high when an overflow or underflow has occurred. The over/under flow for both channels are multiplexed onto this pin. Channel 2 appears when CLKOUT+ is low, and Channel 1 appears when CLKOUT+ is high. DOUBLE DATA RATE LVDS OUTPUT MODE All Pins Below Have LVDS Output Levels. The Output Current Level Is Programmable. There Is an Optional Internal 100Ω Termination Resistor Between the Pins of Each LVDS Output Pair. D2_0_1–/D2_0_1+ to D2_14_15–/D2_14_15+ (Pins 23/24, 25/26, 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock. The Digital Outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the Digital Outputs by programming the mode control registers. 218543f 17 LTC2185/LTC2184/LTC2183 pin FuncTions D1_0_1–/D1_0_1+ to D1_14_15–/D1_14_15+ (Pins 43/44, 45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. OF2_1–/OF2_1+ (Pins 59/60): Over/Under Flow Digital Output. OF2_1+ is high when an overflow or underflow has occurred. The over/under flow for both channels are multiplexed onto this pin. Channel 2 appears when CLKOUT+ is low, and Channel 1 appears when CLKOUT+ is high. FuncTional block DiagraM OVDD CH 1 ANALOG INPUT S/H 16-BIT ADC CORE CORRECTION LOGIC CH 2 ANALOG INPUT 16-BIT ADC CORE OF1 OF2 D1_15 • • • D1_0 CLKOUT + CLKOUT – VREF 2.2µF 1.25V REFERENCE RANGE SELECT D2_15 • • • D2_0 OGND S/H OUTPUT DRIVERS SENSE REF BUF DIFF REF AMP REFH REFL INTERNAL CLOCK SIGNALS VDD CLOCK/DUTY CYCLE CONTROL MODE CONTROL REGISTERS VCM1 0.1µF VCM2 0.1µF VDD/2 GND REFH 2.2µF 0.1µF REFL ENC+ ENC– PAR/SER CS SCK SDI SDO 218543 F01 0.1µF Figure 1. Functional Block Diagram 218543f 18 LTC2185/LTC2184/LTC2183 applicaTions inForMaTion CONVERTER OPERATION The LTC2185/LTC2184/LTC2183 are low power, two-channel, 16-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially, or single ended for lower power consumption. The digital outputs can be CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) Many additional features can be chosen by programming the mode control registers through a serial SPI port. ANALOG INPUT The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or VCM2 output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs. LTC2185 VDD AIN+ 10 CPARASITIC 1.8pF RON 15 CPARASITIC 1.8pF VDD 0.1µF 1.2V 10k ENC+ ENC– 10k 1.2V 218543 F02 The two channels are simultaneously sampled by a shared encode circuit (Figure 2). Single-Ended Input For applications less sensitive to harmonic distortion, the AIN+ input can be driven single-ended with a 1VP-P signal centered around VCM. The AIN– input should be connected to VCM. With a single-ended input the harmonic distortion and INL will degrade, but the noise and DNL will remain unchanged. INPUT DRIVE CIRCUITS Input filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency. Transformer Coupled Circuits RON 15 CSAMPLE 5pF VDD AIN– 10Ω CSAMPLE 5pF Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figure 4 to Figure 6) has better balance, resulting in lower A/D distortion. 50 VCM 0.1µF ANALOG INPUT T1 1:1 25 25 25 0.1µF 12pF 25 AIN– 218543 F03 AIN+ LTC2185 T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 2. Equivalent Input Circuit. Only One of the Two Analog Channels Is Shown Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 218543f 19 LTC2185/LTC2184/LTC2183 applicaTions inForMaTion Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figure 4 to Figure 6) should convert the signal to differential before driving the A/D. 50 VCM 0.1µF 0.1µF ANALOG INPUT T2 T1 25 25 12 0.1µF 8.2pF 0.1µF 12 AIN– 218543 F04 Reference The LTC2185/LTC2184/LTC2183 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The VREF, REFH and REFL pins should be bypassed as shown in Figure 8. A low inductance 2.2µF interdigitated capacitor is recommended for the bypass between REFH and REFL. This type of capacitor is available at a low cost from multiple suppliers. 50 VCM 0.1µF 0.1µF ANALOG INPUT T1 4.7nH 25 25 0.1µF AIN+ LTC2185 AIN+ LTC2185 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front-End Circuit for Input Frequencies from 5MHz to 150MHz 50 VCM 0.1µF 0.1µF ANALOG INPUT T2 T1 25 25 0.1µF 1.8pF 0.1µF AIN– 218543 F05 0.1µF 4.7nH AIN– 218543 F06 T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN+ LTC2185 Figure 6. Recommended Front-End Circuit for Input Frequencies Above 250MHz VCM HIGH SPEED DIFFERENTIAL 0.1µF AMPLIFIER ANALOG INPUT 200 200 25 0.1µF AIN+ 12pF 0.1µF LTC2185 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE + – + – 25 Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz to 250MHz AIN– 12pF 218543 F07 Figure 7. Front-End Circuit Using a High Speed Differential Amplifier 218543f 20 LTC2185/LTC2184/LTC2183 applicaTions inForMaTion LTC2185 1.25V VREF 2.2µF 5 1.25V BANDGAP REFERENCE 0.625V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE C2 0.1µF in some vendors’ capacitors. In Figure 8d the REFH and REFL pins are connected by short jumpers in an internal layer. To minimize the inductance of these jumpers they can be placed in a small hole in the GND plane on the second board layer. TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.625V < VSENSE < 1.300V – + C1 + – + – REFH REFL 0.8x DIFF AMP Figure 8c. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8a – C3 0.1µF REFH REFL + INTERNAL ADC LOW REFERENCE C1: 2.2µF LOW INDUCTANCE INTERDIGITATED CAPACITOR TDK CLLE1AX7S0G225M MURATA LLA219C70G225M AVX W2L14Z225M OR EQUIVALENT 218543 F08a Figure 8d. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8b. VREF 2.2µF 1.25V EXTERNAL REFERENCE SENSE 1µF 218543 F09 Figure 8a. Reference Circuit At sample rates below 110Msps an interdigitated capacitor is not necessary for good performance and C1 can be replaced by a standard 2.2µF capacitor between REFH and REFL (see Figure 8b). The capacitors should be as close to the pins as possible (not on the back side of the circuit board). Figure 8c and Figure 8d show the recommended circuit board layout for the REFH/REFL bypass capacitors. Note that in Figure 8c, every pin of the interdigitated capacitor (C1) is connected since the pins are not internally connected C3 0.1µF C1 2.2µF C2 0.1µF REFH REFL LTC2185 LTC2185 Figure 9. Using an External 1.25V Reference Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals – do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figure 12 and Figure 13). The encode inputs are internally biased to 1.2V 218543f REFH REFL 218543 F08b CAPACITORS ARE 0402 PACKAGE SIZE Figure 8b. Alternative REFH/REFL Bypass Circuit 21 LTC2185/LTC2184/LTC2183 applicaTions inForMaTion LTC2185 VDD DIFFERENTIAL COMPARATOR VDD 15k ENC+ ENC– 30k through 10kΩ equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single ended encode mode. For good jitter performance ENC+ and ENC– should have fast rise and fall times. The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. If the encode signal is turned off or drops below approximately 500kHz, the A/D enters nap mode. 218543 F10 Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode LTC2185 1.8V TO 3.3V 0V ENC+ ENC– 30k CMOS LOGIC BUFFER 218543 F11 Clock Duty Cycle Stabilizer For good performance the encode signal should have a 50% (±5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled by mode control register A2 (Serial Programming Mode), or by CS (Parallel Programming Mode). For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle. The duty cycle stabilizer should not be used below 5Msps. DIGITAL OUTPUTS Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode 0.1µF T1 ENC+ 50Ω LTC2185 100Ω 0.1µF 50Ω 0.1µF ENC– 218543 F12 T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive 0.1µF ENC+ PECL OR LVDS CLOCK LTC2185 0.1µF ENC– 218543 F13 Digital Output Modes The LTC2185/LTC2184/LTC2183 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) The output mode is set by mode control register A3 (Serial Programming 218543f Figure 13. PECL or LVDS Encode Drive 22 LTC2185/LTC2184/LTC2183 applicaTions inForMaTion Mode), or by SCK (Parallel Programming Mode). Note that double data rate CMOS cannot be selected in the Parallel Programming Mode. Full Rate CMOS Mode In Full Rate CMOS Mode the data outputs (D1_0 to D1_15 and D2_0 to D2_15), overflow (OF2, OF1), and the data output clocks (CLKOUT+, CLKOUT–) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Double Data Rate CMOS Mode In Double Data Rate CMOS Mode, two data bits are multiplexed and output on each data pin. This reduces the number of digital lines by seventeen, simplifying board routing and reducing the number of input pins needed to receive the data. The data outputs (D1_0_1, D1_2_3, D1_4_5, D1_6_7, D1_8_9, D1_10_11, D1_12_13, D1_14_15, D2_0_1, D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11, D2_12_13, D2_14_15), overflow (OF2_1), and the data output clocks (CLKOUT+, CLKOUT–) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. Note that the overflow for both ADC channels is multiplexed onto the OF2_1 pin. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. When using Double Data Rate CMOS at sample rates above 100Msps the SNR may degrade slightly, about 0.2dB to 0.5dB depending on load capacitance and board layout. Double Data Rate LVDS Mode In Double Data Rate LVDS Mode, two data bits are multiplexed and output on each differential output pair. There are eight LVDS output pairs per ADC channel (D1_0_1+/ D1_0_1– through D1_14_15+/D1_14_15– and D2_0_1+/ D2_0_1– through D2_14_15+/D2_14_15–) for the digital output data. Overflow (OF2_1+/OF2_1–) and the data output clock (CLKOUT+/CLKOUT–) each have an LVDS output pair. Note that the overflow for both ADC channels is multiplexed onto the OF2_1+/OF2_1– output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. In LVDS mode, OVDD must be 1.8V. Programmable LVDS Output Current In LVDS Mode, the default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit outputs a logic high when the analog input is either over-ranged or under-ranged. The overflow bit has the same pipeline latency as the data bits. In Full-Rate CMOS mode each ADC channel has its own overflow pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS or DDR LVDS mode the overflow for both ADC channels is multiplexed onto the OF2_1 output. 218543f 23 LTC2185/LTC2184/LTC2183 applicaTions inForMaTion Phase Shifting the Output Clock In Full Rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT+, so the rising edge of CLKOUT+ can be used to latch the output data. In Double Data Rate CMOS and LVDS Modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT+. To allow adequate set-up and hold time when latching the data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2185/LTC2184/LTC2183 can also phase shift the CLKOUT+/CLKOUT– signals by serially programming mode control register A2. The output clock can be shifted by 0°, 45°, 90°, or 135°. To use the phase shifting feature the Clock Duty Cycle Stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT–, independently of the phase shift. The combination of these two features enables phase shifts of 45° up to 315° (Figure 14). ENC+ DATA FORMAT Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A4. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) >1.000000V +0.999970V +0.999939V +0.000030V +0.000000V –0.000030V –0.000061V –0.999939V –1.000000V