LTC2308CUF-TRPBF

LTC2308 Low Noise, 500ksps, 8-Channel, 12-Bit ADC FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTION The LTC®2308 is a low noise, 500ksps, 8-channel, 12-bit ADC with an SPI/MICROWIRE compatible serial interface. This ADC includes an internal reference and a fully differential sample-and-hold circuit to reduce common-mode noise. The internal conversion clock allows the external serial output data clock (SCK) to operate at any frequency up to 40MHz. The LTC2308 operates from a single 5V supply and draws just 3.5mA at a sample rate of 500ksps. The auto-shutdown feature reduces the supply current to 200μA at a sample rate of 1ksps. The LTC2308 is packaged in a small 24-pin 4mm × 4mm QFN. The internal 2.5V reference and 8-channel multiplexer further reduce PCB board space requirements. The low power consumption and small size make the LTC2308 ideal for battery operated and portable applications, while the 4-wire SPI compatible serial interface makes this ADC a good match for isolated or remote data acquisition systems. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ■ ■ ■ ■ ■ ■ ■ ■ 12-Bit Resolution 500ksps Sampling Rate Low Noise: SINAD = 73.3dB Guaranteed No Missing Codes Single 5V Supply Auto-Shutdown Scales Supply Current with Sample Rate Low Power: 17.5mW at 500ksps 0.9mW Nap Mode 35μW Sleep Mode Internal Reference Internal 8-Channel Multiplexer Internal Conversion Clock SPI/MICROWIRETM Compatible Serial Interface Unipolar or Bipolar Input Ranges (Software Selectable) Separate Output Supply OVDD (2.7V to 5.25V) 24-Pin 4mm × 4mm QFN Package APPLICATIONS ■ ■ ■ ■ ■ ■ High Speed Data Acquisition Industrial Process Control Motor Control Accelerometer Measurements Battery Operated Instruments Isolated and/or Remote Data Acquisition TYPICAL APPLICATION 5V 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 8192 Point FFT, fIN = 1kHz 0.1μF OVDD 0.1μF SDI 2.7V TO 5.25 V fSMPL = 500kHz SINAD = 73.6dB THD = –89.5dB 0.1μF 10μF AVDD 10μF DVDD LTC2308 CH0 CH1 CH2 CH3 CH0-CH7 CH4 ANALOG INPUTS 0V TO 4.096V UNIPOLAR CH5 2.048V BIPOLAR CH6 CH7 COM ANALOG INPUT MUX + – 12-BIT 500ksps ADC SERIAL PORT SDO SCK CONVST VREF SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTER INTERNAL 2.5V REF 2.2μF MAGNITUDE (dB) 0 50 150 100 FREQUENCY (kHz) 200 250 2308 G03 REFCOMP GND 0.1μF 10μF 2308 TA01 2308f 1 LTC2308 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW DVDD OVDD 18 GND 17 SD0 25 16 SCK 15 SDI 14 CONVST 13 AVDD 7 VREF 8 REFCOMP 9 10 11 12 GND GND GND AVDD GND CH2 CH1 CH0 Supply Voltage (AVDD, DVDD, OVDD) ...........................6V Analog Input Voltage (Note 3) CH0 - CH7, COM, REF, REFCOMP ....................(GND –0.3V) to (AVDD + 0.3V) Digital Input Voltage (Note 3) ...................... (GND –0.3V) to (DVDD + 0.3V) Digital Output Voltage ..... (GND –0.3V) to (OVDD + 0.3V) Power Dissipation ...............................................500mW Operating Temperature Range LTC2308C ................................................ 0°C to 70°C LTC2308I ............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C 24 23 22 21 20 19 CH3 1 CH4 2 CH5 3 CH6 4 CH7 5 COM 6 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH LTC2308CUF#PBF LTC2308IUF#PBF TAPE AND REEL LTC2308CUF#TRPBF LTC2308IUF#TRPBF PART MARKING* 2308 2308 PACKAGE DESCRIPTION 24-Lead (4mm × 4mm) Plastic QFN 24-Lead (4mm × 4mm) Plastic QFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ CONVERTER AND MULTIPLEXER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Bipolar Zero Error Match Unipolar Zero Error Unipolar Zero Error Drift Unipolar Zero Error Match (Note 7) (Note 7) (Note 6) CONDITIONS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5) MIN ● ● ● ● TYP ±0.3 ±0.25 ±1 0.002 ±0.3 ±0.5 0.002 ±0.3 MAX ±1 ±1 ±6 ±3 ±3 ±2 UNITS Bits LSB LSB LSB LSB/°C LSB LSB LSB/°C LSB 12 ● ● ● 2308f 2 LTC2308 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 4, 5) PARAMETER Bipolar Full-Scale Error Bipolar Full-Scale Error Drift Bipolar Full-Scale Error Match Unipolar Full-Scale Error Unipolar Full-Scale Error Drift Unipolar Full-Scale Error Match External Reference (Note 8) External Reference ● CONVERTER AND MULTIPLEXER CHARACTERISTICS CONDITIONS External Reference (Note 8) External Reference MIN ● TYP ±1 0.05 ±0.5 ±1.5 0.05 ±0.4 MAX ±9 ±3 ±8 ±3 UNITS LSB LSB/°C LSB LSB LSB/°C LSB ● ● ANALOG INPUT SYMBOL VIN VIN + – The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Absolute Input Range (CH0 to CH7) Absolute Input Range (CH0 to CH7, COM) Input Differential Voltage Range Analog Input Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio Sample Mode Hold Mode CONDITIONS (Note 9) Unipolar (Note 9) Bipolar (Note 9) VIN = VIN+ – VIN– (Unipolar) VIN = VIN+ – VIN– (Bipolar) ● ● ● ● ● ● MIN –0.05 –0.05 –0.05 TYP MAX AVDD AVDD/2 AVDD UNITS V V V V V VIN+ – VIN– IIN CIN CMRR 0 to REFCOMP ±REFCOMP/2 ±1 55 5 70 μA pF pF dB The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 10) SYMBOL SINAD SNR THD SFDR PARAMETER Signal-to-(Noise + Distortion) Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range Channel-to-Channel Isolation Full Linear Bandwidth –3dB Input Linear Bandwidth Aperture Delay Transient Reponse Full-Scale Step CONDITIONS fIN = 1kHz fIN = 1kHz fIN = 1kHz, First 5 Harmonics fIN = 1kHz fIN = 1kHz (Note 11) ● ● ● ● DYNAMIC ACCURACY MIN 71 71 TYP 73.3 73.4 –90 –90 –109 700 25 13 240 MAX UNITS dB dB –78 –80 dB dB dB kHz MHz ns ns 2308f 3 LTC2308 The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER VREF Output Voltage VREF Output Tempco VREF Output Impedance VREFCOMP Output Voltage VREF Line Regulation CONDITIONS IOUT = 0 IOUT = 0 –0.1mA ≤ IOUT ≤ 0.1mA IOUT = 0 AVDD = 4.75V to 5.25V ● INTERNAL REFERENCE CHARACTERISTICS MIN 2.47 TYP 2.50 ±25 8 4.096 0.8 MAX 2.53 UNITS V ppm/°C kΩ V mV/V The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Digital Input Capacitance High Level Output Voltage Low Level Input Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current OVDD = 4.75V, IOUT = –10μA OVDD = 4.75V, IOUT = –200μA OVDD = 4.75V, IOUT = 160μA OVDD = 4.75V, IOUT = 1.6mA VOUT = 0V to OVDD, CONVST High CONVST High VOUT = 0V VOUT = OVDD ● ● ● DIGITAL INPUTS AND DIGITAL OUTPUTS CONDITIONS DVDD = 5.25V DVDD = 4.75V VIN = VDD MIN ● ● ● TYP MAX 0.8 ±10 UNITS V V μA pF V V 2.4 5 4.74 4 0.05 0.4 ±10 15 –10 10 V V μA pF mA mA POWER REQUIREMENTS SYMBOL AVDD DVDD OVDD IDD PARAMETER Analog Supply Voltage Digital Supply Voltage Output Driver Supply Voltage Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS MIN 4.75 4.75 2.7 CL = 25pF CONVST = 5V, Conversion Done CONVST = 5V, Conversion Done ● ● ● TYP 5 5 3.5 180 7 17.5 0.9 35 MAX 5.25 5.25 5.25 4.2 400 20 UNITS V V V mA μA μA mW mW μW PD 2308f 4 LTC2308 TIMING CHARACTERISTICS SYMBOL fSMPL(MAX) fSCK tWHCONV tHD tSUDI tWHCLK tWLCLK tWLCONVST tHCONVST tCONV tACQ tREFWAKE tdDO thDO ten tdis tr tf tCYC PARAMETER Maximum Sampling Frequency Shift Clock Frequency CONVST High Time Hold Time SDI After SCK↑ Setup Time SDI Valid Before SCK↑ SCK High Time SCK Low Time CONVST Low Time During Data Transfer Hold Time CONVST Low After Last SCK↓ Conversion Time Acquisition Time REFCOMP Wakeup Time (Note 12) SDO Data Valid After SCK↓ SDO Hold Time After SCK↓ SDO Valid After CONVST↓ Bus Relinquish Time SDO Rise Time SDO Fall Time Total Cycle Time 7th SCK↑ to CONVST↑ (Note 9) CREFCOMP = 10μF, CREF = 2.2μF CL = 25pF (Note 9) CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF ● ● ● ● The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) CONDITIONS ● ● MIN TYP MAX 500 40 UNITS kHz MHz ns ns ns ns ns ns ns (Note 9) ● ● ● 20 2.5 0 10 10 410 20 1.3 240 200 10.8 4 11 11 4 4 2 15 15 12.5 1.6 fSCK = fSCK(MAX) fSCK = fSCK(MAX) (Note 9) (Note 9) ● ● ● ● ● ● μs ns ms ns ns ns ns ns ns μs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with AVDD, DVDD and OVDD wired together (unless otherwise noted). Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. These products can handle input currents greater than 100mA below ground or above VDD without latchup. Note 4: AVDD = 5V, DVDD = 5V, OVDD = 5V, fSMPL = 500kHz, internal reference unless otherwise specified. Note 5: Linearity, offset and full-scale specifications apply for a singleended analog input with respect to COM. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Unipolar zero error is the offset voltage measured from +0.5LSB when the output code flickers between 0000 0000 0000 and 0000 0000 0001. Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. Unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. Note 9: Guaranteed by design, not subject to test. Note 10: All specifications in dB are referred to a full-scale ±2.048V input with a 2.5V reference voltage. Note 11: Full linear bandwidth is defined as the full-scale input frequency at which the SINAD degrades to 60dB or 10 bits of accuracy. Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin to settle within 0.5LSB at 12-bit resolution of its final value after waking up from SLEEP mode. 2308f 5 LTC2308 fSMPL = 500ksps, Internal Reference, unless otherwise noted. Integral Nonlinearity vs Output Code 1.00 0.75 0.50 INL (LSB) DNL (LSB) 0.25 0 –0.25 –0.50 –0.75 –1.00 0 1024 2048 OUTPUT CODE 2308 G01 TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity vs Output Code 1.00 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 3072 4096 –1.00 0 1024 2048 OUTPUT CODE 3072 TA = 25°C, AVDD = DVDD = OVDD = 5V, 1kHz Sine Wave 8192 Point FFt Plot 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 SNR = 73.7dB SINAD = 73.6dB THD = –89.5dB MAGNITUDE (dB) 4096 2308 G02 0 50 150 100 FREQUENCY (kHz) 200 250 2308 G03 Crosstalk vs Frequency for an Adjacent Pair –60 –70 –80 CROSSTALK (dB) 80 75 70 65 60 55 50 SNR vs Input Frequency 80 75 70 SINAD (dB) 1 10 100 FREQUENCY (kHz) 1000 3208 G05 SINAD vs Input Frequency –100 –110 –120 –130 –140 0.1 1 10 100 FREQUENCY (kHz) 1000 3208 G04 SNR (dB) –90 65 60 55 50 1 10 100 FREQUENCY (kHz) 1000 3208 G06 THD vs Input Frequency –60 –65 SUPPLY CURRENT (mA) –70 THD (dB) –75 –80 –85 –90 –95 –100 1 10 100 FREQUENCY (kHz) 1000 3208 G07 Supply Current vs Sampling Frequency 3.5 3.0 4 2.5 2.0 1.5 1.0 0.5 0 SUPPLY CURRENT (mA) 1 10 100 SAMPLING FREQUENCY (ksps) 1000 3208 G08 Supply Current vs Temperature 5 3 2 1 0 –50 –25 50 25 0 75 TEMPERATURE ( C) 100 125 3208 G09 2308f 6 LTC2308 TYPICAL PERFORMANCE CHARACTERISTICS fSMPL = 500ksps, Internal Reference, unless otherwise noted. Sleep Current vs Temperature 10 1000 TA = 25°C, AVDD = DVDD = OVDD = 5V, Analog Input Leakage Current vs Temperature fSMPL = 0ksps 6 LEAKAGE CURRENT (nA) 8 SLEEP CURRENT (μA) 800 600 CH (ON) 400 CH (OFF) 200 4 2 0 –50 –25 50 25 0 75 TEMPERATURE ( C) 100 125 0 –50 –25 50 25 0 75 TEMPERATURE ( C) 100 125 3208 G10 3208 G11 Offset vs Temperature 1.5 4 Full-Scale Error vs Temperature FULL-SCALE ERROR (LSB) 2 BIPOLAR 0 UNIPOLAR OFFSET (LSB) 1.0 BIPOLAR UNIPOLAR –2 0.5 –4 EXTERNAL REFERENCE –25 50 25 0 75 TEMPERATURE ( C) 100 125 0 –50 EXTERNAL REFERENCE –25 0 25 50 75 TEMPERATURE (°C) 100 125 –6 –50 2308 G12 2308 G13 2308f 7 LTC2308 PIN FUNCTIONS CH3-CH7 (Pins 1, 2, 3, 4, 5): Channel 3 to Channel 7 Analog Inputs. CH3 – CH7 can be configured as singleended or differential input channels. See the Analog Input Multiplexer section. COM (Pin 6): Common Input. This is the reference point for all single-ended inputs. It must be free of noise and connected to ground for unipolar conversions and midway between GND and REFCOMP for bipolar conversions. VREF (Pin 7): 2.5V Reference Output. Bypass to GND with a minimum 2.2μF tantalum capacitor or low ESR ceramic capacitor. The internal reference may be over driven by an external 2.5V reference at this pin. REFCOMP (Pin 8): Reference Buffer Output. Bypass to GND with a 10μF tantalum and 0.1μF ceramic capacitor in parallel. Nominal output voltage is 4.096V. GND (Pins 9, 10, 11, 18, 20): Ground. All GND pins must be connected to a solid ground plane. AVDD (Pins 12, 13): 5V Analog Supply. The range of AVDD is 4.75V to 5.25V. Bypass AVDD to GND with a 0.1μF ceramic and a 10μF tantalum capacitor in parallel. CONVST (Pin 14): Conversion Start. A rising edge at CONVST begins a conversion. For best performance, ensure that CONVST returns low within 40ns after the conversion starts or after the conversion ends. SDI (Pin 15): Serial Data Input. The SDI serial bit stream configures the ADC and is latched on the rising edge of the first 6 SCK pulses. SCK (Pin 16): Serial Data Clock. SCK synchronizes the serial data transfer. The serial data input at SDI is latched on the rising edge of SCK. The serial data output at SDO transitions on the falling edge of SCK. SDO (Pin 17): Serial Data Out. SDO outputs the data from the previous conversion. SDO is shifted out serially on the falling edge of each SCK pulse. OVDD (Pin 19): Output Driver Supply. Bypass OVDD to GND with a 0.1μF ceramic capacitor close to the pin. The range of OVDD is 2.7V to 5.25V. DVDD (Pin 21): 5V Digital Supply. The range of DVDD is 4.75V to 5.25V. Bypass DVDD to GND with a 0.1 μF ceramic and a 10μF tantalum capacitor in parallel. CH0-CH2 (Pins 22, 23, 24): Channel 0 to Channel 2 Analog Inputs. CH0 – CH2 can be configured as singleended or differential input channels. See the Analog Input Multiplexer section. GND (Pin 25): Exposed Pad Ground. Must be soldered directly to ground plane. 2308f 8 LTC2308 BLOCK DIAGRAM AVDD CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM INTERNAL 2.5V REF ANALOG INPUT MUX DVDD OVDD LTC2308 + – SDI 12-BIT 500ksps ADC SERIAL PORT SDO SCK CONVST 8k VREF GAIN = 1.6384x REFCOMP 2308 BD GND TEST CIRCUIT Load Circuit for tdis WAVEFORM 1 VDD 3k SDO CL 2308 TC01 Load Circuit for tdis WAVEFORM 2, ten SDO TEST POINT 3k CL TEST POINT 2308 TC02 2308f 9 LTC2308 TIMING DIAGRAM Voltage Waveforms for SDO Delay Times, tdDO and thDO SCK VIL tdDO thDO SDO 2308 TD01 tWLCLK (SCK Low Time) tWHCLK (SCK High Time) tHD (Hold Time SDI After SCK↑) tSUDI (Setup Time SDI Stable Before SCK↑) tWLCLK tWHCLK VOH VOL SCK tHD SDI tSUDI 2308 TD03 Voltage Waveforms for tdis VIH CONVST SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2) 10% 90% SDO ten 2308 TD04 CONVST Voltage Waveforms for ten NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL 2308 TD02 Voltage Waveforms for SDO Rise and Fall Times tr, tf SDO VOH VOL tr tf 2308 TD05 2308f 10 LTC2308 APPLICATIONS INFORMATION Overview The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit successive approximation register (SAR) A/D converter. The LTC2308 includes a precision internal reference, a configurable 8-channel analog input multiplexer (MUX) and an SPI-compatible serial port for easy data transfers. The ADC may be configured to accept single-ended or differential signals and can operate in either unipolar or bipolar mode. A sleep mode option is also provided to save power during inactive periods. Conversions are initiated by a rising edge on the CONVST input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, a 6-bit input word (DIN) at the SDI input configures the MUX and programs various modes of operation. As the DIN bits are shifted in, data from the previous conversion is shifted out on SDO. After the 6 bits of the DIN word have been shifted in, the ADC begins acquiring the analog input in preparation for the next conversion as the rest of the data is shifted out. The acquire phase requires a minimum time of 240ns for the sample-and-hold capacitors to acquire the analog input signal. During the conversion, the internal 12-bit capacitive charge-redistribution DAC output is sequenced through a successive approximation algorithm by the SAR starting from the most significant bit (MSB) to the least significant bit (LSB). The sampled input is successively compared with binary weighted charges supplied by the capacitive DAC using a differential comparator. At the end of a conversion, the DAC output balances the analog input. The SAR contents (a 12-bit data word) that represent the sampled analog input are loaded into 12 output latches that allow the data to be shifted out. Programming the LTC2308 The various modes of operation of the LTC2308 are programmed by a 6-bit DIN word. The SDI data bits are loaded on the rising edge of SCK, with the S/D bit loaded on the first rising edge and the SLP bit on the sixth rising edge (see Figure 8 in the Timing and Control section). The input data word is defined as follows: S/D O/S S1 S0 UNI SLP S/D = SINGLE-ENDED/DIFFERENTIAL BIT O/S = ODD/SIGN BIT S1 = ADDRESS SELECT BIT 1 S0 = ADDRESS SELECT BIT 0 UNI = UNIPOLAR/BIPOLAR BIT SLP = SLEEP MODE BIT 2308f 11 LTC2308 APPLICATIONS INFORMATION Analog Input Multiplexer The analog input MUX is programmed by the S/D, O/S, S1 and S0 bits of the DIN word. Table 1 lists the MUX configurations for all combinations of the configuration bits. Figure 1a shows several possible MUX configurations and Figure 1b shows how the MUX can be reconfigured from one conversion to the next. Driving the Analog Inputs The analog inputs of the LTC2308 are easy to drive. Each of the analog inputs can be used as a single-ended input relative to the COM pin (CH0-COM, CH1-COM, etc.) or in differential input pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7). Figure 2 shows how to drive COM for single-ended inputs in unipolar and bipolar modes. Regardless of the MUX configuration, the “+” and “–“ inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors during the acquire mode. In conversion mode, the analog inputs draw only a small leakage current. If the source impedance of the Table 1. Channel Configuration S/D O/S S1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + + + + + + + + – + – + – + – + – – – – – – – – 2308f 4 Differential 8 Single-Ended + (–) – (+) { + (–) – (+) { + (–) – (+) { + (–) – (+) { CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 + + + + + + + + CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM (–) Combinations of Differential and Single-Ended + –{ – +{ + + + + CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM (–) 2308 F01a Figure 1a. Example MUX Configurations 1st Conversion 2nd Conversion 0 + 1 – 2 + 3 – 4 5 6 7 COM + –{ + –{ CH2 CH3 CH4 CH5 COM (UNUSED) – + + + { { CH2 CH3 CH4 CH5 COM (–) 2308 F01b + – + – Figure 1b. Changing the MUX Assignment “On the Fly” Unipolar Mode Bipolar Mode COM REFCOMP/2 + – COM 2308 F02 Figure 2. Driving COM in UNIPOLAR and BIPOLAR Modes 12 LTC2308 APPLICATIONS INFORMATION driving circuit is low, the ADC inputs can be driven directly. Otherwise, more acquisition time should be allowed for a source with higher impedance. Input Filtering The noise and distortion of the input amplifier and other circuitry must be considered since they will add to the ADC noise and distortion. Therefore, noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. The analog inputs of the LTC2308 can be modeled as a 55pF capacitor (CIN) in series with a 100Ω resistor (RON) as shown in Figure 3a. CIN gets switched to the selected input once during each conversion. Large filter RC time constants will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (tACQ) if DC accuracy is important. When using a filter with a large CFILTER value (e.g. 1μF), the inputs do not completely settle and the capacitive input switching currents are averaged into a net DC current (IDC). In this case, the analog input can be modeled by an INPUT CH0-CH7 LTC2308 equivalent resistance (REQ = 1/(fSMPL • CIN)) in series with an ideal voltage source (VREFCOMP/2) as shown in Figure 3b. The magnitude of the DC current is then approximately IDC = (VIN - VREFCOMP/2)/REQ, which is roughly proportional to VIN. To prevent large DC drops across the resistor RFILTER, a filter with a small resistor and large capacitor should be chosen. When running at the minimum cycle time of 2μs, the input current equals 106μA at VIN = 5V, which amounts to a full-scale error of 0.5LSBs when using a filter resistor (RFILTER) of 4.7Ω. Applications requiring lower sample rates can tolerate a larger filter resistor for the same amount of full-scale error. Figures 4a and 4b show respective examples of input filtering for single-ended and differential inputs. For the single-ended case in Figure 4a, a 50Ω source resistor and a 2000pF capacitor to ground on the input will limit the input bandwidth to 1.6MHz. High quality capacitors and resistors should be used in the RC filter since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. ANALOG INPUT 50Ω 2000pF COM CH0 LTC2308 RSOURCE VIN C1 RON = 100Ω CIN = 55pF REFCOMP 10μF 2308 F03a 0.1μF 2308 F04a Figure 3a. Analog Input Equivalent Circuit Figure 4a. Optional RC Input Filtering for Single-Ended Input 1000pF 50Ω RFILTER VIN IDC INPUT CH0-CH7 LTC2308 CFILTER REQ = 1/(fSMPL • CIN) DIFFERENTIAL ANALOG INPUTS CH0 1000pF CH1 1000pF LTC2308 50Ω + – VREFCOMP/2 10μF 2308 F03b REFCOMP 0.1μF 2308 F04b Figure 3b. Analog Input Equivalent Circuit for Large Filter Capacitances Figure 4b. Optional RC Input Filtering for Differential Inputs 2308f 13 LTC2308 APPLICATIONS INFORMATION Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 5 shows a typical SINAD of 73.3dB with a 500kHz sampling rate and a 1kHz input. A SNR of 73.4dB can be achieved with the LTC2308. Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency(fSMPL /2). THD is expressed as: THD = 20 log V22 + V32 + V42... + VN2 V1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. Internal Reference The LTC2308 has an on-chip, temperature compensated bandgap reference that is factory trimmed to 2.5V (Refer to Figure 6a). It is internally connected to a reference amplifier and is available at VREF (Pin 7). VREF should be bypassed to GND with a 2.2μF tantalum capacitor for stability and to minimize noise. An 8k resistor is in series with the output so that it can be easily overdriven by an external reference if more accuracy and/or lower drift are required as shown in Figure 6b. The reference amplifier gains the VREF voltage by 1.638 to 4.096V at REFCOMP (Pin 8). To compensate the reference amplifier, bypass REFCOMP with a 10μF ceramic or tantalum capacitor in parallel with a 0.1μF ceramic capacitor for best noise performance. Internal Conversion Clock The internal conversion clock is factory trimmed to achieve a typical conversion time (tCONV) of 1.3μs and a maximum conversion time of 1.6μs over the full operating temperature range. With a typical acquisition time of 240ns, a throughput sampling rate of 500ksps is tested and guaranteed. MAGNITUDE (dB) 0 50 150 100 FREQUENCY (kHz) 200 250 2308 F05 Figure 5. 1kHz Sine Wave 8192 Point FFT Plot 2308f 14 LTC2308 APPLICATIONS INFORMATION Digital Interface The LTC2308 communicates via a standard 4-wire SPI compatible digital interface. The rising edge of CONVST initiates a conversion. After the conversion is finished, pull CONVST low to enable the serial output (SDO). The ADC shifts out the digital data in 2’s complement format when operating in bipolar mode or in straight binary format when in unipolar mode, based on the setting of the UNI bit. For best performance, ensure that CONVST returns low within 40ns after the conversion starts (i.e., before the first bit decision) or after the conversion ends. If CONVST is low when the conversion ends, the MSB bit will appear at SDO at the end of the conversion and the ADC will remain powered up. Timing and Control The start of a conversion is triggered by a rising edge at CONVST. Once initiated, a new conversion cannot be restarted until the current conversion is complete. Figures 8 and 9 show the timing diagrams for two different examples of CONVST pulses. Example 1 (Figure 8) shows CONVST staying HIGH after the conversion ends. If CONVST is high VREF 2.2μF 4.096V REFCOMP R1 8k BANDGAP REFERENCE 0.1 F REFERENCE AMP after the tCONV period, the LTC2308 enters NAP or SLEEP mode, depending on the setting of SLP bit from the DIN word that was shifted in after the previous conversion. (see Nap Mode and Sleep Mode for more detail). When CONVST returns low, the ADC wakes up and the most significant bit (MSB) of the output data sequence at SDO becomes valid after the serial data bus is enabled. All other data bits from SDO transition on the falling edge of each SCK pulse. Configuration data (DIN) is loaded into the LTC2308 at SDI, starting with the first SCK rising edge after CONVST returns low. The S/D bit is loaded on the first SCK rising edge. Example 2 (Figure 9) shows CONVST returning low before the conversion ends. In this mode, the ADC and all internal circuitry remain powered up. When the conversion is complete, the MSB of the output data sequence at SDO becomes valid after the data bus is enabled. At this point(tCONV 1.3μs after the rising edge of CONVST), pulsing SCK will shift data out at SDO and load configuration data (DIN) into the LTC2308 at SDI. The first SCK rising edge loads the S/D bit into the LTC2308. SDO transitions on the falling edge of each SCK pulse. 5V VIN LT1790A-2.5 VOUT 2.2μF VREF LTC2308 2.5V 10μF R2 0.1μF GND R3 LTC2308 2308 F06a + REFCOMP 10μF 0.1μF GND 2308 F06b Figure 6a. LTC2308 Reference Circuit Figure 6b. Using the LT1790A-2.5 as an External Reference 2308f 15 LTC2308 APPLICATIONS INFORMATION Figures 8 and 9 are the transfer characteristics for the bipolar and unipolar modes. Data is output at SDO in 2’s complement format for bipolar readings and in straight binary for unipolar readings. Nap Mode The ADC enters nap mode when CONVST is held high after the conversion is complete (tCONV) if the SLP bit is set to a logic 0. The supply current decreases to 180μA in nap mode between conversions, thereby reducing the average power dissipation as the sample rate decreases. For example, the LTC2308 draws an average of 200μA with a 1ksps sampling rate. The LTC2308 keeps only the reference(VREF) and reference buffer(REFCOMP) circuitry active when in nap mode. Sleep Mode The ADC enters sleep mode when CONVST is held high after the conversion is complete (tCONV) if the SLP bit is set to a logic 1. The ADC draws only 7μA in sleep mode, provided that none of the digital inputs are switching. When CONVST returns low, the LTC2308 is released from the SLEEP mode and requires 200ms to wake up and charge the respective 2.2μF and 10μF bypass capacitors on the VREF and REFCOMP pins. 0VDD, BYPASS 10μF 0603 , Board Layout and Bypassing To obtain the best performance, a printed circuit board with a solid ground plane is required. Layout for the printed circuit board should ensure digital and analog signal lines are separated as much as possible. Care should be taken not to run any digital signal alongside an analog signal. All analog inputs should be shielded by GND. VREF, REFCOMP and AVDD should be bypassed to the ground plane as close to the pin as possible. Maintaining a low impedance path for the common return of these bypass capacitors is essential to the low noise operation of the ADC. These traces should be as wide as possible. See Figure 7 for a suggested layout. DVDD, BYPASS 10μF 0603 , AVDD, BYPASS 10μF || 0.1μF 0603 , VREF, BYPASS 2.2μF 1206 , REFCOMP BYPASS , 10μF || 0.1μF 0603 , NOTE: SECOND LAYER OF BOARD IS A SOLID GROUND PLANE. Figure 7. Suggested Layout 2308f 16 LTC2308 APPLICATIONS INFORMATION tWLCONVST tACQ CONVST tCONV NAP OR SLEEP tCYC 1 SCK 2 3 4 5 6 7 8 9 10 11 12 SDI S/D O/S S1 S0 UNI SLP MSB Hi-Z SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 LSB B0 Hi-Z 2308 F08 Figure 8. LTC2308 Timing with a Long CONVST Pulse tWHCONV CONVST tCYC 1 2 3 4 5 6 7 8 9 tHCONVST tACQ tCONV 10 11 12 SCK SDI S/D O/S S1 S0 UNI SLP MSB Hi-Z SDO B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 LSB B1 B0 Hi-Z 2308 F09 Figure 9. LTC2308 Timing with a Short CONVST Pulse 2308f 17 LTC2308 APPLICATIONS INFORMATION OUTPUT CODE (TWO’S COMPLEMENT) 011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 –FS/2 FS = 4.096V 1LSB = FS/2N 1LSB = 1mV –1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 – 1LSB 2308 F10 111...111 BIPOLAR ZERO OUTPUT CODE 111...110 100...001 100...000 011...111 UNIPOLAR ZERO 011...110 FS = 4.096V 1LSB = FS/2N 1LSB = 1mV 0V INPUT VOLTAGE (V) 2308 F11 000...001 000...000 FS – 1LSB Figure 10. LTC2308 Bipolar Transfer Characteristics (2’s Complement) Figure 11. LTC2308 Unipolar Transfer Characteristics (Straight Binary) 2308f 18 LTC2308 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ± 0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ± 0.05 BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 4.00 ± 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 23 24 0.40 ± 0.10 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 2308f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2308 TYPICAL APPLICATION Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator, Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing 5V 2.7V TO 5V 10 F 0.1 F AVDD 10 F DVDD 0.1 F OVDD 0.1 F LTC2308 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM ANALOG INPUT MUX SDI + – 12-BIT 500ksps ADC SERIAL PORT SDO SCK CONVST VREF VCC NL17SZ74 PRE Q Q CLR CONVERT ENABLE REFCOMP D CONTROL LOGIC (FPGA, CPLD, DSP ETC.) , INTERNAL 2.5V REF 2.2 F GND 0.1 F 10 F VCC RF SIGNAL GENERATOR OR OTHER LOW-JITTER SOURCE 0.1 F 1k MASTER CLOCK NC7SVU04P5X 50 1k MASTER CLOCK •••••• •••••• CONVERT ENABLE •••••• JITTER •••••• CONVST •••••• DATA TRANSFER •••••• 2308 TA02 RELATED PARTS PART NUMBER LTC1417 LTC1468/LT1469 LTC1609 LTC1790 LTC1850/LTC1851 LTC1852/LTC1853 LTC1860/LTC1861 LTC1860L/LTC1861L LTC1863/LTC1867 LTC1863L/LTC1867L LTC1864/LTC1865 LTC1864L/LTC1865L DESCRIPTION 14-Bit, 400ksps Serial ADC Single/Dual 90MHz, 22V/μs, 16-Bit Accurate Op Amps 16-Bit, 200ksps Serial ADC Micropower Low Dropout Reference 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC 10-Bit/12-Bit, 8-Channel, 400ksps ADC 12-Bit, 1-/2-Channel, 250ksps ADC in MSOP 3V, 12-Bit, 1-/2-Channel, 150ksps ADC 12-/16-Bit, 8-Channel, 200ksps ADC 3V, 12-/16-Bit, 8-Channel, 175ksps ADC 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP COMMENTS 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package Low Input Offset: 75μV/125μV 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply 60μA Supple Current, 10ppm/°C, SOT-23 Package Parallel Output, Programmable MUX and Sequencer, 5V Supply Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply 850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages 450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages 6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package 850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages 450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages 2308f 20 Linear Technology Corporation (408) 432-1900 ● FAX: (408) 434-0507 ● LT 0807 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007