LTC2445IUHF

FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LTC2444/LTC2445/ LTC2448/LTC2449 24-Bit High Speed 8-/16-Channel ∆Σ ADCs with Selectable Speed/Resolution DESCRIPTIO The LTC®2444/LTC2445/LTC2448/LTC2449 are 8-/16channel (4-/8-differential) high speed 24-bit No Latency ∆ΣTM ADCs. They use a proprietary delta-sigma architecture enabling variable speed/resolution. Through a simple 4-wire serial interface, ten speed/resolution combinations 6.9Hz/280nVRMS to 3.5kHz/25µVRMS (4kHz with external oscillator) can be selected with no latency between conversion results or shift in DC accuracy (offset, full-scale, linearity, drift). Additionally, a 2X speed mode can be selected enabling output rates up to 7kHz (8kHz if an external oscillator is used) with one cycle latency. Any combination of single-ended or differential inputs can be selected with a common mode input range from ground to VCC, independent of VREF. While operating in the 1X speed mode the first conversion following a new speed, resolution, or channel selection is valid. Since there is no settling time between conversions, all 8 differential channels can be scanned at a rate of 500Hz. At the conclusion of each conversion, the converter is internally reset eliminating any memory effects between successive conversions and assuring stability of the high order delta-sigma modulator. , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency ∆Σ is a trademark of Linear Technology Corporation. Up to 8 Differential or 16 Single-Ended Input Channels Up to 8kHz Output Rate Up to 4kHz Multiplexing Rate Selectable Speed/Resolution 2µVRMS Noise at 1.76kHz Output Rate 200nVRMS Noise at 13.8Hz Output Rate with Simultaneous 50/60Hz Rejection Guaranteed Modulator Stability and Lock-Up Immunity for any Input and Reference Conditions 0.0005% INL, No Missing Codes Autosleep Enables 20µA Operation at 6.9Hz < 5µV Offset (4.5V < VCC < 5.5V, – 40°C to 85°C) Differential Input and Differential Reference with GND to VCC Common Mode Range No Latency Mode, Each Conversion is Accurate Even After a New Channel is Selected Internal Oscillator—No External Components LTC2445/LTC2449 Include MUXOUT/ADCIN for External Buffering or Gain Tiny QFN 5mm x 7mm Package APPLICATIO S ■ ■ ■ ■ ■ High Speed Multiplexing Weight Scales Auto Ranging 6-Digit DVMs Direct Temperature Measurement High Speed Data Acquisition TYPICAL APPLICATIO Simple 24-Bit Variable Speed Data Acquisition System 4.5V TO 5.5V 1µ F CH0 CH1 • • • CH7 CH8 • • • CH15 COM REF – GND LTC2448 2444 TA01 REF + VCC FO RMS NOISE (µV) = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR (SIMULTANEOUS 50Hz/60Hz REJECTION AT 6.9Hz OUTPUT RATE) 4-WIRE SPI INTERFACE THERMOCOUPLE 16-CHANNEL MUX + – VARIABLE SPEED/ RESOLUTION DIFFERENTIAL 24-BIT ∆Σ ADC SDI SCK SDO CS U U U LTC2444/LTC2448 Speed vs RMS Noise 100 VCC = 5V VREF = 5V VIN+ = VIN– = 0V 2X SPEED MODE NO LATENCY MODE 2.8µV AT 880Hz 280nV AT 6.9Hz (50/60Hz REJECTION) 10 1 0.1 1 1000 10 100 CONVERSION RATE (Hz) 10000 2440 TA02 sn2444589 2444589fs 1 LTC2444/LTC2445/ LTC2448/LTC2449 ABSOLUTE (Notes 1, 2) AXI U RATI GS Operating Temperature Range LTC2444C/LTC2445C/ LTC2448C/LTC2449C .............................. 0°C to 70°C LTC2444I/LTC2445I/ LTC2448I/LTC2449I ........................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 125°C Supply Voltage (VCC) to GND .......................– 0.3V to 6V Analog Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) PACKAGE/ORDER I FOR ATIO TOP VIEW GND GND SDO SCK SDI CS FO GND 38 37 36 35 34 33 32 GND 1 BUSY 2 EXT 3 GND 4 GND 5 GND 6 COM 7 NC 8 CH0 9 CH1 10 NC 11 NC 12 13 14 15 16 17 18 19 NC NC CH2 CH3 CH4 CH5 NC 31 GND 30 REF– 29 REF+ 28 VCC 27 NC 26 NC 25 NC 24 NC 23 NC 22 CH7 21 CH6 20 NC LTC2444CUHF LTC2444IUHF 38 37 36 35 34 33 32 GND 1 BUSY 2 EXT 3 GND 4 GND 5 GND 6 COM 7 NC 8 31 GND 30 REF– 29 REF+ 28 VCC 27 MUXOUTN 26 ADCINN 25 ADCINP 24 MUXOUTP 23 NC 22 CH7 21 CH6 20 NC 13 14 15 16 17 18 19 NC NC CH2 CH3 CH4 CH5 NC GND SDO SCK SDI CS FO ORDER PART NUMBER QFN PART MARKING* 2444 UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W TOP VIEW GND GND SDO SCK SDI CS FO 38 37 36 35 34 33 32 GND 1 BUSY 2 EXT 3 GND 4 GND 5 GND 6 COM 7 CH0 8 CH1 9 CH2 10 CH3 11 CH4 12 13 14 15 16 17 18 19 CH5 CH6 CH7 CH8 CH9 CH10 CH11 31 GND 30 REF– 29 REF+ 28 VCC 27 NC 26 NC 25 NC 24 NC 23 CH15 22 CH14 21 CH13 20 CH12 ORDER PART NUMBER LTC2448CUHF LTC2448IUHF GND 38 37 36 35 34 33 32 GND 1 BUSY 2 EXT 3 GND 4 GND 5 GND 6 COM 7 CH0 8 31 GND 30 REF– 29 REF+ 28 VCC 27 MUXOUTN 26 ADCINN 25 ADCINP 24 MUXOUTP 23 CH15 22 CH14 21 CH13 20 CH12 13 14 15 16 17 18 19 GND SDO SCK SDI CS FO QFN PART MARKING* 2448 CH5 CH6 CH7 CH8 CH9 CH10 UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W TJMAX = 125°C, θJA = 34°C/W *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. sn2444589 2444589fs 2 CH11 U U W WW U W TOP VIEW ORDER PART NUMBER LTC2445CUHF LTC2445IUHF CH0 9 CH1 10 NC 11 NC 12 QFN PART MARKING* 2445 UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W TOP VIEW ORDER PART NUMBER LTC2449CUHF LTC2449IUHF CH1 9 CH2 10 CH3 11 CH4 12 QFN PART MARKING* 2449 LTC2444/LTC2445/ LTC2448/LTC2449 The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error CONDITIONS 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5) VCC = 5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6) REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC (Note 12) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC REF + = 5V, REF – = GND, IN + = 3.75V, IN – = 1.25V REF + = 2.5V, REF – = GND, IN + = 1.875V, IN – = 0.625V 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ REF + = 5V, REF – = GND, IN + = 1.25V, IN – = 3.75V REF + = 2.5V, REF – = GND, IN + = 0.625V, IN – = 1.875V 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN– = IN+ ≤ VCC ● ● ● ● ● ● ● ELECTRICAL CHARACTERISTICS MIN 24 TYP 5 3 2.5 20 10 10 0.2 10 10 0.2 15 15 15 120 MAX 15 5 UNITS Bits ppm of VREF ppm of VREF µV nV/°C 50 50 ppm of VREF ppm of VREF ppm of VREF/°C 50 50 ppm of VREF ppm of VREF ppm of VREF/°C ppm of VREF ppm of VREF ppm of VREF dB Input Common Mode Rejection DC A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL IN+ IN– VIN REF+ REF– VREF CS(IN+) CS(IN–) CS(REF+) CS(REF–) IDC_LEAK(IN+, IN–, REF+, REF–) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN– Voltage Input Differential Voltage Range (IN+ – IN–) Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF– Voltage Reference Differential Voltage Range (REF+ – REF–) IN+ Sampling Capacitance IN– Sampling Capacitance REF+ Sampling Capacitance REF– Sampling Capacitance Leakage Current, Inputs and Reference Average Input/Reference Current During Sampling MUX Break-Before-Make MUX Off Isolation ISAMPLE(IN+, IN–, REF+, REF–) tOPEN QIRR U U U U CONDITIONS ● ● ● ● ● ● MIN GND – 0.3V GND – 0.3V –VREF/2 0.1 GND 0.1 TYP MAX VCC + 0.3V VCC + 0.3V VREF/2 VCC VCC – 0.1V VCC UNITS V V V V V V pF pF pF pF 2 2 2 2 CS = VCC, IN+ = GND, IN– REF+ = 5V, REF– = GND = GND, ● –15 1 15 nA nA ns dB Varies, See Applications Section 50 VIN = 2VP-P DC to 1.8MHz 120 sn2444589 2444589fs 3 LTC2444/LTC2445/ LTC2448/LTC2449 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO, EXT, SOI Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO, BUSY Low Level Output Voltage SDO, BUSY High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO (Note 8) IO = –800µA IO = 1.6mA IO = –800µA (Note 9) IO = 1.6mA (Note 9) ● ● ● ● ● The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V (Note 8) 4.5V ≤ VCC ≤ 5.5V (Note 8) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC (Note 8) ● ● ● ● ● ● POWER REQUIRE E TS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● TI I G CHARACTERISTICS SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS ● ● ● fISCK Internal SCK Frequency 4 UW U U MIN 2.5 TYP MAX UNITS V 0.8 2.5 0.8 –10 –10 10 10 VCC – 0.5V 0.4V VCC – 0.5V 0.4V –10 10 10 10 V V V µA µA pF pF V V V V µA MIN 4.5 TYP MAX 5.5 UNITS V mA µA CS = 0V (Note 7) CS = VCC (Note 7) ● ● 8 8 11 30 UW MIN 0.1 25 25 0.99 126 TYP MAX 20 10000 10000 UNITS MHz ns ns ms ms ms OSR = 256 (SDI = 0) OSR = 32768 (SDI = 1) External Oscillator (Notes 10, 13) Internal Oscillator (Note 9) External Oscillator (Notes 9, 10) ● ● ● ● 1.13 145 40 • OSR +170 fEOSC (kHz) 1.33 170 0.8 0.9 fEOSC/10 1 MHz Hz sn2444589 2444589fs LTC2444/LTC2445/ LTC2448/LTC2449 TI I G CHARACTERISTICS SYMBOL DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 t7 t8 PARAMETER Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS ↓ to SDO Low Z CS ↑ to SDO High Z CS ↓ to SCK ↓ CS ↓ to SCK ↑ SCK ↓ to SDO Valid SDO Hold After SCK ↓ SCK Set-Up Before CS ↓ SCK Hold After CS ↓ SDI Setup Before SCK ↑ SDI Hold After SCK ↑ The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) CONDITIONS (Note 9) (Note 8) (Note 8) (Note 8) Internal Oscillator (Notes 9, 11) External Oscillator (Notes 9, 10) (Note 8) (Note 12) (Note 12) (Note 9) (Notes 8, 12) (Note 5) ● ● ● ● ● ● ● ● ● ● ● ● ● ● Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 4.5V to 5.5V unless otherwise specified. VREF = REF + – REF –, VREFCM = (REF + + REF –)/2; VIN = IN + – IN –, VINCM = (IN + + IN –)/2. Note 4: FO pin tied to GND or to external conversion clock source with fEOSC = 10MHz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. PI FU CTIO S GND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a common ground plane through a low impedance connection. All 7 pins must be connected to ground for proper operation. BUSY (Pin 2): Conversion in Progress Indicator. This pin is HIGH while the conversion is in progress and goes LOW indicating the conversion is complete and data is ready. It remains LOW during the sleep and data output states. At the conclusion of the data output state, it goes HIGH indicating a new conversion has begun. EXT (Pin 3): Internal/External SCK Selection Pin. This pin is used to select internal or external SCK for outputting/ inputting data. If EXT is tied low, the device is in the external SCK mode and data is shifted out of the device under the control of a user applied serial clock. If EXT is tied high, the internal serial clock mode is selected. The device generates its own SCK signal and outputs this on the SCK pin. A framing signal BUSY (Pin 2) goes low indicating data is being output. COM (Pin 7): The common negative input (IN –) for all single ended multiplexer configurations. The voltage on CH0-CH15 and COM pins can have any value between sn2444589 2444589fs U U UW MIN 45 25 25 41.6 TYP MAX 55 20 UNITS % MHz ns ns 35.3 320/fEOSC 32/fESCK 30.9 µs s s ns ns µs ns 0 0 5 25 25 25 25 15 50 50 10 10 ns ns ns ns ns ns (Note 5) (Note 5) ● ● Note 7: The converter uses the internal oscillator. Note 8: The converter is in external SCK mode of operation such that the SCK pin is used as a digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in Hz. Note 9: The converter is in internal SCK mode of operation such that the SCK pin is used as a digital output. In this mode of operation, the SCK pin has a total equivalent load capacitance of CLOAD = 20pF. Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in Hz. Note 11: The converter uses the internal oscillator. FO = 0V. Note 12: Guaranteed by design and test correlation. Note 13: There is an internal reset that adds an additional 1µs (typ) to the conversion time. U 5 LTC2444/LTC2445/ LTC2448/LTC2449 PI FU CTIO S GND – 0.3V to VCC + 0.3V. Within these limits, the two selected inputs (IN+ and IN–) provide a bipolar input range (VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside this input range, the converter produces unique over-range and under-range output codes. CH0 to CH15 (Pins 8-23): LTC2448/LTC2449 Analog Inputs. May be programmed for single-ended or differential mode. CH0 to CH7 (Pins 9, 10, 13, 14, 17, 18, 21, 22): LTC2444/ LTC2445 Analog Inputs. May be programmed for singleended or differential mode. NC (Pins 8, 11, 12, 15, 16, 19, 20, 23): LTC2444/ LTC2445 No Connect/Channel Isolation Shield. May be left floating or tied to any voltage 0 to VCC in order to provide isolation for pairs of differential input channels. NC (Pins 24, 25, 26, 27): LTC2444/LTC2448 No Connect. These pins can either be tied to ground or left floating. MUXOUTP (Pin 24): LTC2445/LTC2449 Positive Multiplexer Output. Used to drive the input to an external buffer/ amplifier. ADCINP (Pin 25): LTC2445/LTC2449 Positive ADC Input. Tie to output of buffer/amplifier driven by MUXOUTP. ADCINN (Pin 26): LTC2445/LTC2449 Negative ADC Input. Tie to output of buffer/amplifier driven by MUXOUTN. MUXOUTN (Pin 27): LTC2445/LTC2449 Negative Multiplexer Output. Used to drive the input to an external buffer/ amplifier. VCC (Pin 28): Positive Supply Voltage. Bypass to GND with a 10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor as close to the part as possible. REF + (Pin 29), REF – (Pin 30): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is maintained more positive than the negative reference input, REF+, by at least 0.1V. SDI (Pin 34): Serial Data Input. This pin is used to select the speed, 1X or 2X mode, resolution, and input channel, for the next conversion cycle. At initial power up, the default mode of operation is CH0-CH1, OSR of 256, and 1X mode. The serial data input contains an enable bit which determines if a new channel/speed is selected. If this bit is low the following conversion remains at the same speed and selected channel. The serial data input is applied to the device under control of the serial clock (SCK) during the data output cycle. The first conversion following a new channel/speed is valid. FO (Pin 35): Frequency Control Pin. Digital input that controls the internal conversion clock. When FO is connected to VCC or GND, the converter uses its internal oscillator running at 9MHz. The conversion rate is determined by the selected OSR such that tCONV (ms) = 40 • OSR + 170/fOSC (kHz). The first digital filter null is located at 8/tCONV, 7kHz at OSR = 256 and 55Hz (Simultaneous 50/ 60Hz) at OSR = 32768. This pin may be driven with a maximum external clock of 10.24MHz resulting in a maximum 8kHz output rate (OSR = 64, 2X Mode). CS (Pin 36): Active Low Chip Select. A LOW on this pin enables the SDO ditital output and wakes up the ADC. Following each conversion the ADC automatically enters the sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output aborts the data transfer and starts a new conversion. SDO (Pin 37): Three-State Digital Output. During the data output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the conversion and sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. This signal is HIGH while the conversion is in progress and goes LOW once the conversion is complete. SCK (Pin 38): Bidirectional Digital Clock Pin. In internal serial clock operation mode, SCK is used as a digital output for the internal serial interface clock during the data output period. In the external serial clock operation mode, SCK is used as the digital input for the external serial interface clock during the data output period. The serial clock operation mode is determined by the logic level applied to the EXT pin. sn2444589 2444589fs 6 U U U LTC2444/LTC2445/ LTC2448/LTC2449 FU CTIO AL BLOCK DIAGRA VCC GND REF + REF – CH0 CH1 • • • MUX AUTOCALIBRATION AND CONTROL IN + IN – – CH15 COM DIFFERENTIAL 3RD ORDER ∆Σ MODULATOR Figure 1. Functional Block Diagram TEST CIRCUITS SDO 1.69k CLOAD = 20pF SDO Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z 2440 TA03 APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2444/LTC2445/LTC2448/LTC2449 are multichannel, high speed, delta-sigma analog-to-digital converters with an easy to use 3- or 4-wire serial interface (see Figure 1). Their operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output/input (see Figure 2). The 4-wire interface consists of serial data input (SDI), serial data output (SDO), serial clock (SCK) and chip select (CS). The interface, timing, operation cycle and data out format is compatible with Linear’s entire family of ∆Σ converters. W INTERNAL OSCILLATOR FO (INT/EXT) U W U U U U + SERIAL INTERFACE DECIMATING FIR ADDRESS 2444 F01 SDI SCK SDO CS VCC 1.69k CLOAD = 20pF Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2440 TA04 POWER UP IN+=CH0, IN–=CH1 OSR=256,1X MODE CONVERT SLEEP CS = LOW AND SCK CHANNEL SELECT SPEED SELECT DATA OUTPUT 2444 F02 Figure 2. LTC2444/LTC2445/LTC2448/LTC2449 State Transition Diagram sn2444589 2444589fs 7 LTC2444/LTC2445/ LTC2448/LTC2449 APPLICATIO S I FOR ATIO Initially, the LTC2444/LTC2445/LTC2448/LTC2449 perform a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced below 10µA. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result while operating in the 1x mode. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS, SCK and EXT pins, the LTC2444/LTC2445/LTC2448/LTC2449 offer several flexible modes of operation (internal or external SCK). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Ease of Use The LTC2444/LTC2445/LTC2448/LTC2449 data output has no latency, filter settling delay or redundant data associated with the conversion cycle while operating in the 1X mode. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. Speed/ resolution adjustments may be made seamlessly between two conversions without settling errors. The LTC2444/LTC2445/LTC2448/LTC2449 perform offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. 8 U Power-Up Sequence The LTC2444/LTC2445/LTC2448/LTC2449 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. The conversion immediately following a POR is performed on the input channel IN+ = CH0, IN– = CH1 at an OSR = 256 in the 1X mode. Following the POR signal, the LTC2444/LTC2445/LTC2448/ LTC2449 start a normal conversion cycle and follow the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (4.5V to 5.5V) before the end of the POR time interval. Reference Voltage Range These converters accept a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF – pin. The LTC2444/LTC2445/LTC2448/LTC2449 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter’s effective resolution. On the other hand, a reduced reference voltage will improve the converter’s overall INL performance. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the CH0-CH15 and COM input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2444/LTC2445/ sn2444589 2444589fs W U U LTC2444/LTC2445/ LTC2448/LTC2449 APPLICATIO S I FOR ATIO LTC2448/LTC2449 convert the bipolar differential input signal, VIN = IN+ – IN– (where IN+ and IN– are the selected input channels), from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. MUXOUT/ADCIN There are two differences between the LTC2444/LTC2448 and the LTC2445/LTC2449. The first is the RMS noise performance. For a given OSR, the LTC2445/LTC2449 noise level is approximately √2 times lower (0.5 effective bits)than that of the LTC2444/LTC2448. The second difference is the LTC2445/LTC2449 includes MUXOUT/ADCIN pins. These pins enable an external buffer or gain block to be inserted between the output of the multiplexer and the input to the ADC. Since the buffer is driven by the output of the multiplexer, only one circuit is required for all 16 input channels. Additionally, the transparent calibration feature of the LTC244X family automatically removes the offset errors of the external buffer. In order to achieve optimum performance, the MUXOUT and ADCIN pins should not be shorted together. In applications where the MUXOUT and ADCIN need to be shorted together, the LTC2444/LTC2448 should be used because the MUXOUT and ADCIN are internally connected for optimum performance. Output Data Format The LTC2444/LTC2445/LTC2448/LTC2449 serial output data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. In the case of ultrahigh resolution modes, more than 24 effective bits of performance are possible (see Table 5). Under these conditions, sub LSBs are included in the conversion result and represent useful information beyond the 24-bit level. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS). U Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is